Texas Instruments XIO2001 Manuel utilisateur

XIO2001

Evaluation Module (EVM)

User's Guide

Literature Number: SCPU031February 2009

2 SCPU031 – February 2009Submit Documentation Feedback

Contents

1 Read This First .................................................................................................................... 41.1 About This Manual ........................................................................................................ 41.2 How to Use This Manual ................................................................................................. 41.3 Information About Cautions and Warnings ............................................................................ 41.4 Related Documentation from Texas Instruments ..................................................................... 42 Overview ............................................................................................................................. 53 EVM Features ...................................................................................................................... 53.1 PCI Express Connector .................................................................................................. 53.2 PCI Add-In Slots .......................................................................................................... 53.3 EEPROM Interface ....................................................................................................... 63.4 Test Header ................................................................................................................ 63.5 Clock Run ( CLKRUN) .................................................................................................... 73.6 JTAG Header .............................................................................................................. 73.7 LEDs ....................................................................................................................... 74 FAQ/Troubleshooting ........................................................................................................... 84.1 BIOS Fails to Assign Memory Window to Bridge ..................................................................... 84.2 ×16 Slots Only Support INTA ............................................................................................ 84.3 System Turns On When PCI Card Is Inserted Into EVM Or When EVM Is Plugged Into Slot.................. 84.4 What To Do If EVM Is Not Working .................................................................................... 85 Schematics ........................................................................................................................ 106 Bill of Materials ................................................................................................................. 14

Important Notices ............................................................................................................... 16

SCPU031 – February 2009 Table of Contents 3Submit Documentation Feedback

1 Read This First

1.1 About This Manual

1.2 How to Use This Manual

1.3 Information About Cautions and Warnings

1.4 Related Documentation from Texas Instruments

User's GuideSCPU031 – February 2009

XIO2001 Evaluation Module (EVM)

This manual describes the operation of the XIO2001 evaluation module (EVM) from Texas Instruments.

This document contains the following sections:•Overview

•EVM Features•FAQ/Troubleshooting

•Schematics

•Bill of Materials

This manual may contain cautions and warnings.

CAUTION

This is an example of a caution statement.

A caution statement describes a situation that could potentially damage yoursoftware or equipment.

WARNINGThis is an example of a warning statement.

A warning statement describes a situation that could potentiallycause harm to you.

Table 1 contains a list of data manuals that have detailed descriptions of the integrated circuits used in thedesign of the TAS3208EVM-LC. The data manuals can be obtained at www.ti.com .

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2 Overview

3 EVM Features

3.1 PCI Express Connector

3.2 PCI Add-In Slots

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Overview

Table 1. Related TI Documentation

DOCUMENT LITERATURE NUMBER

XIO2001 Implementation Guide SCPA045XIO2001 Data Manual SCPS212

The XIO2001 evaluation board (EVM) implements a peripheral component interconnect (PCI) express toPCI bridge circuit using the Texas Instruments XIO2001 PCI Express to PCI Bus Translation Bridge.Designed as an ×1 add-in card, it is routed on FR4 as a 8-layer (4 signals, 2 power, and 2 ground) boardwith a 100- Ωdifferential impedance (50- Ωsingle-ended) using standard routing guidelines andrequirements .

(1)

Power for the XIO2001 EVM and any PCI add-in card connected to the EVM is provided or derived fromthe standard voltages provided on the PCI Express connector. Power for the 3.3-V rail is provided directlyfrom the add-in connector, 5-V and 12-V is provided from the IDE power connector, while regulators arepresent to derive 1.5-V for the XIO2001 and -12-V for the PCI connectors.

Upon request, gerber files for the EVM can be provided that illustrate techniques that achieve fan-out ofthe µ*BGA, use of split power planes, placement of filters and other critical components, and methodsused to match lengths on PCI and PCI Express signals on a standard 8-layer board.

Schematics and a Bill of Materials are provided to illustrate the design of this EVM.

Note: Observe proper ESD procedures when handling the EVM. Failure to observe properprocedures may result in damage either to the EVM or the XIO2001 silicon which may causethe board to malfunction.

(1)

As specified in PCI Express Electromechanical Specification, Revision 1.0a and PCI Local Bus Specification, Revision 2.3

The EVM is designed as a half-width PCI Express add-in card. The card fits into any standard ×1, ×2, ×4,×8, or ×16 add-in connector that is compliant with the PCI Express Electromechanical Specification,Revision 2.0 or earlier. In addition to the standard transmit-and-receive pairs, the connector must supply3.3 V, 12 V, PERST, a 100-MHz differential clock, and V

AUX

. The WAKE signal is also supported by theEVM although, as an optional pin, the system is not required to support this signal.

The height of the board is nonstandard due to the presence of PCI slots. Inserting PCI add-in cards intothe EVM will, in most cases, prohibit the EVM from being placed in a case. If possible, provide somemechanical support to the EVM. Otherwise, the weight of PCI add-in cards can strain the board in the PCIExpress add-in slot and may result in the board making poor contact with the connector. Poor connectorcontact can lead to signal integrity issues.

The XIO2001 EVM provides three standard PCI add-in slots. While reversible, these slots, as shipped, arekeyed as 5-V slots and provide a 5-V V

clamping voltage that provides accessibility to any 5-V oruniversally keyed PCI add-in cards. All standard voltages (3.3 V, 5 V, 12 V, and –12 V) are providedthrough the PCI connectors, enabling standard PCI add-in cards to function without requiring externalpower.

Cards placed into the PCI add-in slots must be inserted into the slots in accordance with labeling on theEVM. Referencing the component side of the EVM as front and the PCI express edge connector as down,boards must be inserted with the component side of the board down and the mounting bracket to the leftof the EVM.

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3.3 EEPROM Interface

3.4 Test Header

EVM Features

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WARNINGInserting either a 3.3-V card or a universally keyed card into theEVM backwards will damage the EVM and possibly the add-in cardas well.

The PCI bus operates at 66 MHz only when 66-MHz-capable PCI add-in cards are placed in the socket. Ifa 33-MHz card is inserted into the socket, then the XIO2001 detects the presence of the lower speeddevice and automatically sets the bus speed to 33 MHz. If 66-MHz operation is desired, place no morethan two add-in cards into board slots. (This limitation is due to bus loading issues inherent to the PCIspecification.) If a third 66-MHz device is added to the bus, signal integrity may still permit properfunctioning of the interface, but such functionality cannot be assured and is beyond the scope of thisdocument.

Two of the reserved pins on the PCI add-in connectors are used to route PME and V

AUX

to any add-incards. These assignments, while not part of the PCI Local Bus Specification, are used by many in theindustry as de facto standards and must not interfere with any add-in cards. If cards are used that usethese terminals for other purposes, the following modifications may be made to the EVM to isolate thesignals from the PCI add-in connectors:•PME (routed to reserved terminal A19 on each connector). Remove resistors R55, R53, and R54 (forslots 0, 1, and 2, respectively).•V

AUX

(routed to reserved terminal A14 on each connector). Remove resistors R50, R51, and R52 (forslots 0, 1, and 2, respectively).

Each XIO2001 EVM provides an on-board EEPROM. As shipped, each EEPROM is programmed withvalues that will allow the EVM to function in most systems. The EEPROM interface is left asprogrammable (not write-protected) so that EEPROM contents may be modified for testing other optionalsettings. TI recommends that you do not change the EEPROM values. To change EEPROM contents, usethe EEPROM access registers as detailed in the XIO2001 data manual or request the WinROM accesstool.

Each XIO2001 EVM provides accessibility to the GPIO pins on the XIO2001. From header J1, all fiveGPIOs have external visibility and can be used in any manner consistent with their functionality as detailedin the XIO2001 data manual. All GPIO signals are labeled on the header and are terminated with anon-board pullup resistor.

By default, GPIO3 and GPIO4 are configured as the EEPROM interface which was detailed in theprevious section. The EEPROM interface can be removed from the XIO2001 by removing resistors R28and R29. This allows these GPIO pins to be used for another purpose, although any configuration done bythe EEPROM will then have to be done in some other fashion. While removing R28 and R29 willphysically disconnect the EEPROM from GPIO3/GPIO4, in order to release the pins from this functionality,GPIO4 (SCL) must be held low at the deassertion of PERST. As no pulldown is available for this purpose,the pin must be externally shorted at boot time (deassertion of reset) by shorting J1 pin 5 to J1 pin 11.Once the system has booted, this short may be removed and GPIO3 and GPIO4 will be available for otheruses.

Pin 9 on the J1 header is a global reset (GRST ) for the XIO2001. Driving this pin low will cause allregisters and state machines within the XIO2001 to return to a default power-up state. This pin generallymust remain disconnected.

Pin 10 is an access point for the PME signal and may be used to externally wire this signal to any PCIadd-in card that has the signal available but does not route the signal to pin A19 on the PCI expansionconnector.

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3.5 Clock Run ( CLKRUN)

3.6 JTAG Header

3.7 LEDs

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EVM Features

Pin 8 on header J1 is CLKREQ for the XIO2001. Driving this pin low will allow the REFCLK to stop whenthe XIO2001 is in PCI PM L1. The CLKREQ protocol as described in the PCI Express Base Specificationand Express Card standard is supported.

Pin 7 on header J1 is PERST for the XIO2001. When asserted, this signal generates an internal PCIExpress reset, clears all non-sticky bit registers and is deasserted when system power is stable.

Pin 12 on header J1 is PCLK66_SEL for the XIO2001 controlling the PCI clock frequency. When thissignal is pulled high, the PCI clock will operate at 33 or 66 Mz depending on the state of M66EN. Whenthis signal is low, the PCI clock will operate at 25 MHz or 50 MHz, depending on the state of M66EN. Mostapplications will pull this pin high.

Pin 2 on the connector is a 3.3-V test point and pin 11 is a ground test point. These signals may be usedto externally toggle GPIOs for any required testing.

The CLKRUN signal is a power-saving mechanism (defined in the PCI Mobile Design Guide) that stopsthe PCI bus clock when the bus is idle. Because devices that do not support this protocol are unable torestart the system clock, this feature is disabled by default on the XIO2001 EVM. This feature may beenabled to function with PCI add-in cards that also support this feature.

Enabling CLKRUN requires that resistor R24 be populated with a 0805 form factor 10-k Ωresistor. Whenthis option is populated at the de-assertion of the reset pin, GPIO0 will internally map to CLKRUN. Whenthis happens, GPIO0 will be unavailable for other purposes. An external wire must then be connected fromGPIO0/ CLKRUN (available on J1 pin 1) to all add-in cards being tested with this functionality.

Each XIO2001 EVM provides access to JTAG interface pins for boundary scan testing on test header JP1.The JTAG interface for the XI02001 complies with IEEE standard 1149 using the standard 5 pin interface(TCK, TDI, TDO, TMS and TRST). If boundary scan testing is not needed, TCK (JP1 pin 10) and TRST(JP1 pin 2) should be connected to GND (JP1 pins 1, 3, 5, 7 or 9). The remainder of the JTAG signals canbe left unconnected. By default the EVM is configured with 0 Ωoption resistors R40 and R77 that connectTRST and TCK to ground.

If boundary scan testing is needed, TI can provide the appropriate BDSL file upon request.

The XIO2001 EVM has LEDs onboard to indicate availability of power and status of certain control signals.The onboard LEDs are as follows:•LED1: 5 V power indicator•LED2: 3.3 V power indicator•LED4: 12 V power indicator•LED5: –12 V power indicator

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4 FAQ/Troubleshooting

4.1 BIOS Fails to Assign Memory Window to Bridge

4.2 ×16 Slots Only Support INTA

4.3 System Turns On When PCI Card Is Inserted Into EVM Or When EVM Is Plugged Into Slot

4.4 What To Do If EVM Is Not Working

FAQ/Troubleshooting

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To use the EVM•Plug the PCI add-in cards into the EVM, oriented as indicated on the board•Place the EVM into a PCI express add-in slot•Turn the system on

From the operating system perspective, the XIO2001 appears to be a standard PCI-to-PCI bridge (PCIheader type 1) and the OS will configure the bridge and any devices behind the bridge accordingly usinglegacy PCI configuration transactions. Following sections of this chapter describe issues that may impairuse of the bridge in a system.

Microsoft operating systems generally attempt to respect the resource allocations made by system BIOS.The XIO2001 requires a memory window in order to access some registers used by the device. If theMicrosoft OS determines that the BIOS failed to assign a memory window to the XIO2001, it will assumethat one cannot be assigned and that the device is nonfunctional. The OS will then assume the bridge isnot functional and will not enumerate devices behind the bus. Consequently, these devices will never beconfigured or assigned resources.

This failure can be determined by examining device manager in the OS. If failure has occurred, the bridgewill appear “banged out” and if the bridge properties are examined the OS will reveal this device cannotfind enough free resources that it can use. (Code 12) If you want to use this device, you will need todisable one of the other devices on this system.

As the x16 PCI express add-in slots are designed as a graphics expansion port, many only support asingle interrupt (INTA ), as this is the only interrupt that will be required by a graphics card. The XIO2001EVM supports all interrupts and balances interrupt loading by rotating the interrupts to each add-in slot asrequired by the PCI Local Bus Specification. Accordingly, any PCI add-in card behind the bridge thatasserts an interrupt other than INTA will not be serviced as the interrupt is not supported by the chipset.Consequently, the add-in card will fail. Any devices that do not require interrupts or that only assert INTA(as routed to the specific slot they are placed in) will still function normally.

As mentioned previously, PME is routed on the EVM to the various PCI slots through a reserved pin thatmany PCI add-in cards use for this purpose. On occasion, when a PCI card is inserted into the EVM(while the EVM is plugged into a board), the add-in card may be inserted in such a way as to pull the PMEline low on the EVM. When this happens, the XIO2001 sees a PCI device trying to wake the system andwill appropriately assert WAKE , which may cause the system to turn on.

Similarly, when the EVM is inserted into the slot, V

AUX

from the connector may not have had enough timeto pull the PME line high (as the on-board pullup resistors dictate), yet V

AUX

may have powered theXIO2001 which now samples PME as low and again wakes the system. This is a limitation of the inabilityto appropriately power the pullup resistors before the XIO2001 is powered. If this occurs, turn power to thesystem off and reboot to ensure the EVM receives a clean reset from the system.

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4.4.1 Check EVM Power

4.4.2 Check If Bridge Is Link Training

4.4.3 Check If Bridge Has Been Configured

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FAQ/Troubleshooting

Diodes LED1, LED2, LED4 and LED5 show the status of the 5-V, 3.3-V, 12-V, and –12-V rails,respectively. 1.5 V may be probed on the top pad of C44 (directly next to U3), and –12 V may be probedfrom C100. A ground reference is available at J1 pin 11 and JP1 pins 2, 4, 6, 8 and 10. If any of thesevoltages fail, a problem is likely to occur with EVM functionality. The XIO2001 requires 3.3 V and 1.5 V;other voltages are supplied for use by PCI add-in cards, and PCI V

is by default 5 V (which will causethe entire PCI bus to be clamped to 0.7 V if this voltage is not present). If any of these voltages fail, it islikely that the EVM won’t function because:•XIO2001 will not be powered•The add-in card will not be powered•Neither the XIO2001 or the add-in card will be powered

All voltages have resettable fuses to prevent overcurrent conditions, so if a particular power rail fails:•Detach all devices from the EVM•Remove the EVM from the system•Wait for 30 minutes before trying again

If the system does not boot, remove all PCI add-in cards from EVM and try again. If the system hangsbefore the OS loads, then probably the system and the EVM are having difficulty completing link training (probably an issue with signal integrity on the differential pairs). If a PCI Express analyzer is unavailable,then try a different express slot or a different system if possible. Re-check the 1.5-V rail and examine thedifferential clock on an oscilloscope to ensure it is clean.

If link training successfully completes, the system will boot and the XIO2001 will appear in the devicemanager. If the bridge does not appear in the device manager, then the system may not have detectedthe presence of the bridge, perform the previous checks again.

Also, if the PCI add-in cards have enough weight and there is no mechanical support, the EVM may flexand some components may crack or become disconnected. Check the coupling capacitors on the EVMtransmit lines (C102 and C103). These 0.1- µF 0402 components have a tendency to crack if enoughweight is put on the board; they will need to be replaced if they are damaged.

Once the bridge is communicating with the system, the BIOS and/or the OS are expected to configure thebridge for proper operation. As the bridge appears to software to be a standard PCI-to-PCI bridge, mostexisting BIOS and OS software must be capable of configuring the bridge with no special considerationsfor PCI Express. In addition to the memory window the bridge requests for internal resources, thefollowing items are required for bridge operation:•Command register – PCI offset 0 ×4 : The bus master enable (bit 2), memory enable (bit 1), and I/Oenable (bit 0) must be set to enable the bridge to send upstream transactions.•Cache line size register – PCI offset 0 ×C : Must be set to the cache line size for the system. Failure toset this bit will not cause the bridge to fail but will cause the bridge to limit all upstream transactions to1 DWord.

•Primary, secondary, and subordinate bus numbers– PCI offsets 0 ×18, 0 ×19, and 0 ×1A : The bridgemust have the bus numbers configured so that it can determine which transactions are targeting thebridge, which transactions are targeting devices directly attached to the bridge, and which transactionsare farther downstream from the bridge.•I/O base and limit registers and I/O base upper 16 bits and I/O limit upper 16 bits registers –PCI offsets0×1C, 0 ×1D, 0 ×30 and 0 ×32: If any devices downstream from the bridge require I/O resources, thebridge must be programmed with a window that contains the I/O resources of all devices downstream.Failure to program these windows will cause the bridge to respond to I/O transactions with a responseof Unsupported Request. Any transactions initiated on the secondary side of the bus that fall within thisrange will not be claimed by the bridge. The I/O window for the XIO2001 has a minimum size of 4KBytes and is naturally 4K-aligned. Typically, most systems use only 16-bit addressing for I/Otransactions, so the upper base and limit registers remain 0.

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4.4.4 Check Devices Downstream From Bridge

5 Schematics

Schematics

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•Memory base and memory limit registers – PCI offsets 0 ×20 and 0 ×22 : Similar to the I/O base andlimit registers, the bridge must be programmed with a memory address window containing thenonprefetchable memory resources of all downstream PCI devices requiring nonprefetchable memory.Memory windows have a minimum size of 1 MByte and are naturally 1M-aligned. The bridge does notclaim either a memory transaction initiated from upstream that does not fall within its memory windownor memory transactions initiated downstream that do fall within its memory window.•Prefetchable memory base, prefetchable memory limit, prefetchable base upper 32-bit, andprefetchable limit upper 32-bit registers – PCI offsets 0x24, 0x26, 0x28, and 0 ×2C: Identical to thememory base and limit registers but for prefetchable memory resources. The prefetchable base upper32-bit, and prefetchable limit upper 32-bit registers are only used if 64-bit addressing is in use and inmost systems both of these registers will remain all zeroes. If 64-bit addressing is desired and thememory window for devices behind the XIO2001 resides all or in part in 64-bit memory space then theprefetchable base upper 32-bit register will combine with the prefetchable base register and theprefetchable limit upper 32-bit register will combine with the prefetchable limit register to create 64-bitbase and limit registers. All memory addresses between the two addresses will be considered to belocated behind the bridge.•For all base and limit registers any case in which the limit register contains a lower address than thebase register will be considered invalid. In this situation the bridge will react as if all resources of thattype resided upstream of the bridge. The bridge will respond to all downstream transactions of thattype with Unsupported Request and will claim and forward upstream any transactions of that type thatinitiate on the PCI bus.

Depending on desired functionality, other PCI registers on the XIO2001 may have to be configured.Consult the XIO2001 Data Manual for a description of the previous registers or for any other XIO2001registers.

Once the bridge is communicating and is properly configured, check if devices downstream from thebridge have been configured as required. Check the Windows Device Manager to determine if the devicedrivers have been loaded or if other problems exist with the device. Once you have performed thesechecks, you can perform PCI transactions on the bus and examine them with any standard PCI analyzer.

Schematics for the XIO2001 EVM are shown on the following pages.

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