Texas Instruments TPS2121EVM Manuel utilisateur

SLVUBD2A–September 2018–Revised January 2019

TPS212x Evaluation Module

User's Guide

SLVUBD2A–September 2018–Revised January 2019

TPS212x Evaluation Module

This user's guide describes the characteristics, operation, and use of the TPS212xEVM (EVM). This

document contains the EVM schematics, board layout, bill of materials (BOM), and necessary instructions

on how to properly operate the EVM.

Contents

1 Introduction ................................................................................................................... 2

2 General Configurations ..................................................................................................... 3

3 Test Setup and Results..................................................................................................... 6

4 Board Layout ................................................................................................................. 7

5 Schematic..................................................................................................................... 9

6 Bill of Materials ............................................................................................................. 11

List of Figures

1 TPS2121 Setup With Test Equipment ................................................................................... 7

2 TPS2120 Setup With Test Equipment .................................................................................... 8

3 TPS2121 Schematic......................................................................................................... 9

4 TPS2120 Schematic ....................................................................................................... 10

List of Tables

1 TPS212x EVM Comparison Table......................................................................................... 2

2 TPS2121 Input and Output Connector Functionality.................................................................... 3

3 TPS2121 Test Points Description ......................................................................................... 3

4 TPS2121 Jumper Description.............................................................................................. 3

5 TPS2120 Input and Output Connector Functionality.................................................................... 4

6 TPS2120 Test Points Description ......................................................................................... 4

7 TPS2120 Jumper Description.............................................................................................. 5

8 Default Jumper Settings for TPS2121 Evaluation Board............................................................... 6

9 Default Jumper Settings for TPS2120 Evaluation Board............................................................... 6

10 TPS2121EVM-023 Bill of Materials ..................................................................................... 11

11 TPS2120EVM-042 Bill of Materials ..................................................................................... 13

Trademarks

All trademarks are the property of their respective owners.

Introduction

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TPS212x Evaluation Module

1 Introduction

The TPS212x EVM is an evaluation module for TI's TPS212x family of two-input, one-output power

multiplexers. This device automatically detects, selects, and seamlessly transitions between two power

supplies, each operating from 2.7 V to 22 V. The TPS2121 device, the VSON hot-rod package, can deliver

up to 4 A while the TPS2120, WCSP package, can handle up to 3 A. This user's guide contains the EVM

schematics, board layout, list of materials, and necessary instructions on how to properly operate the

EVM.

The EVM has test points for convenient access to all critical voltages and pins, and jumpers to configure

the different modes of operation. There are also jumpers to configure input and output capacitance, output

load resistance, current limit, and the adjustable soft-start time.

1.1 Features

The TPS212x EVM offers many features including:

• Uninterrupted system power with seamless switchover

• Overvoltage protection

• Low RON resistance at both inputs: 50 mΩtypical

• Multiple configurations for different modes of operation

1.2 Applications

The TPS212x power multiplexer can be used in many applications, including:

• Add-on cards (PCIE, RAID, Network)

• ePos

• Video surveillance

• ORing controllers

1.3 Description

The TPS212x EVM power MUX evaluation board enables evaluation of the TPS212x family of Power

MUX devices. Although both variants (TPS2121EVM-042 or TPS2120EVM-023) contain different jumpers

and connectors, they will function almost identically. Both EVMs allow operation at different input voltages,

although the resistors and jumpers are configured for operation at 3.3 V, 5 V, and 12 V. See the TPS212x

data sheet for more information regarding these settings.

The TPS212x EVMs also allow multiple modes of operation. By configuring the jumpers, the EVMs

automatically detect, select, and seamlessly transition between available inputs. The different modes of

operation are explained in Table 1.

Table 1. TPS212x EVM Comparison Table

EVM Modes of Operation: VOUT Range IOUT MAX Package

TPS2121EVM

• VCOMP

• VREF

• XCOMP

• XREF

2.7 V–22 V 4 A VSON, 2.0 mm × 2.5 mm

TPS2120EVM • VCOMP

• VREF 2.7 V–22 V 3 A WCSP, 1.5 mm × 2.0 mm

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General Configurations

SLVUBD2A–September 2018–Revised January 2019

TPS212x Evaluation Module

2 General Configurations

2.1 TPS2121 Configurations

This section provides an overview of the TPS212x evaluation board input and output jumpers. Table 2

describes the input and output connectors on the EVM. Table 3 describes the different test points and

functionality, while Table 4 describes the jumper functionality and configurations.

Table 2. TPS2121 Input and Output Connector Functionality

Input Connector Label Description

VIN1 J21 VIN1 + , GND - Input block header for VIN1

TP8 VIN1 Input test point for VIN1

TP6 VIN1_SNS Input sense connector for VIN1

VIN2 J14 VIN2 + , GND - Input block header for VIN2

TP11 VIN2 Input test point for VIN2

TP6 VIN2_SNS Input sense connector for VIN2

VOUT J15 VOUT +, GND - Output block header for VOUT

TP9 VOUT Output test point for VOUT

TP7 VOUT_SNS Output sense connector for VOUT

GND TP12, TP13, TP14, TP15,

TP16, TP17, TP18, TP19 GND Test point for GND

Table 3. TPS2121 Test Points Description

Input Connector Label Description

VIN1 TP1 OV1 Overvoltage test point for VIN1

TP4 PR1 Priority test point for VIN1

VIN2 TP2 OV2 Overvoltage test point for VIN2

TP3 CP2 Comparator test point for VIN2

VOUT TP5 ST Status test point

Table 4. TPS2121 Jumper Description

Input Connector Label Description

VIN1

J1, J2, J3 PR1 Resistors (3.3 V, 5 V, 12

Sets priority operation based on voltage

J1 sets 3.3 V

J2 sets 5 V

J3 sets 12 V

J4, J5, J6 OV1 Resistors (3.3 V, 5 V, 12

Sets overvoltage protection for VIN1

J4 sets 3.3 V

J5, sets 5 V

J6 sets 12 V

JP1 PR1 Priority operation control

Position 1-2 sets VCOMP (GND)

Position 2-3 sets VREF, XCOMP, XREF

VIN2

J7, J8, J9 CP2 Resistors (3.3 V, 5 V, 12

Sets XCOMP operation based on voltage

J7 sets 3.3 V

J8 sets 5 V

J9 sets 12 V

J10, J11, J12 OV2 Resistors (3.3 V, 5 V, 12

Sets overvoltage protection for VIN2 channel

J10 sets 3.3 V

J11, sets 5 V

J12 sets 12 V

J13 CP2 CP2 enable, disable

General Configurations

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TPS212x Evaluation Module

Table 4. TPS2121 Jumper Description (continued)

Input Connector Label Description

VOUT

J17, J18 100 µF 100-µF output capacitor

J19 100 µF 100-µF output capacitor

J19 220 µF 220-µF output capacitor

J16 - Female header for custom output resistance,

capacitance

J20 10 Ω10-Ωexternal resistor

JP2 ST Sets adjustable hysteresis

Position 1-2 sets ST, 2-3 disables (GND)

J22, J23 SS Soft-start control

JP3 ILIM Current limit control

Position 1-2 position sets 4.5 A maximum

Position 2-3 sets 2 A maximum

No jumper sets 1.5 A maximum

2.2 TPS2120 Configurations

This section provides an overview of the TPS212x evaluation board input and output jumpers. Table 2

describes the input and output connectors on the EVM. Table 3 describes the different test points and

functionality, while Table 4 describes the jumper functionality and configurations.

Table 5. TPS2120 Input and Output Connector Functionality

Input Connector Label Description

VIN1 J10 VIN1 + , GND - Input block header for VIN1

TP7 VIN1 Input test point for VIN1

TP5 VIN1_SNS Input sense connector for VIN1

VIN2 J17 VIN2 + , GND - Input block header for VIN2

TP11 VIN2 Input test point for VIN2

TP10 VIN2_SNS Input sense connector for VIN2

VOUT J11 VOUT +, GND - Output block header for VOUT

TP8 VOUT Output test point for VOUT

TP6 VOUT_SNS Output sense connector for VOUT

GND TP12, TP13, TP14, TP15,

TP16, TP17, TP18, TP19 GND Test point for GND

Table 6. TPS2120 Test Points Description

Input Connector Label Description

VIN1 TP1 OV1 Overvoltage test point for VIN1

TP3 PR1 Priority test point for VIN1

VIN2 TP2 OV2 Overvoltage test point for VIN2

TP9 SEL Select test point

VOUT TP4 ST Status test point

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General Configurations

SLVUBD2A–September 2018–Revised January 2019

TPS212x Evaluation Module

Table 7. TPS2120 Jumper Description

Input Connector Label Description

VIN1

J1, J2, J3 PR1 Resistors (3.3 V, 5 V, 12 V) Sets priority operation based on voltage

J1 sets 3.3 V

J2 sets 5 V

J3 sets 12 V

J4, J5, J6 OV1 Resistors (3.3 V, 5 V, 12 V) Sets overvoltage protection for VIN1 channel

J4 sets 3.3 V

J5, sets 5 V

J6 sets 12 V

JP2 PR1 Priority operation control

Position 1-2 sets VCOMP (GND)

Position 2-3 sets VREF

VIN2

J7, J8, J9 OV2 Resistors (3.3 V, 5 V, 12 V) Sets overvoltage protection for VIN2 channel

J10 sets 3.3 V

J11, sets 5 V

J12 sets 12 V

JP1 SEL Selects between priority control or GND

Position 1-2 disables priority

Position 2-3 enables priority

VOUT

J12 100 µF 100-µF output capacitor

J13 100 µF 100-µF output capacitor

J14 220 µF 220-µF output capacitor

J15 10 Ω10-Ωexternal resistor

J16 - Female header for custom output resistance,

capacitance

JP3 ST Sets adjustable hysteresis

Position 1-2 sets ST

Position 2-3 disables (GND)

J18, J19 SS Soft-start control

JP4 ILIM Current Limit Control

Position 1-2 sets 4.5 A maximum

Position 2-3 sets 2 A

No jumper sets 1.5 A

Test Setup and Results

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TPS212x Evaluation Module

3 Test Setup and Results

This chapter describes the proper setup for the TPS212x power MUX EVM. This section explains the

different configuration modes present on each EVM, and the required jumper positions to enable each

configuration.

3.1 TPS212x EVM Test Equipment

Read the TPS212x data sheet before using the EVM.

The following test equipment is recommended:

• Storage oscilloscope

• Current problem

• Two adjustable power supples, 0 V–22 V at 4 A maximum

• A passive or active load

3.2 Setting up the TPS2121 EVM

Make sure the TPS2121 evaluation board has the default jumper settings as Table 8 shows.

Table 8. Default Jumper Settings for TPS2121 Evaluation Board

Input Connector Label Position

VIN1 J1 PR1 (3.3 V) Install

J4 OV1 (3.3 V) Install

VIN2 J12 OV2 (12 V) Install

J13 CP2 Install

VOUT

J17, J18 100 µF Install

J20 10 ΩInstall

J22 SS (10 nF) Install

JP1 PR1 Jump pins 2 and 3

JP2 ST Jump pins 2 and 3

JP3 ILIM (4.5 A maximum) Jump pins 1 and 2

The default jumper configuration sets the Internal Voltage Reference (VREF) configuration. Since the

voltage on the priority pin is set for 3.3-V operation and CP2 is grounded, priority will be given to VIN1.

Therefore, VIN1 can be set to 3.3 V, and the device will prioritize VIN1 even if VIN2 is at a higher voltage.

See the data sheet for more information regarding the configuration settings.

3.3 Setting up the TPS2120 EVM

Make sure the TPS2120 evaluation board has default jumper settings as Table 9 shows.

Table 9. Default Jumper Settings for TPS2120 Evaluation Board

Input Connector Label Position

J1 PR1 (3.3 V) Install

J4 OV1 (3.3 V) Install

J9 J9 (12 V) Install

J12, J13 100 µF Install

J15 10 ΩInstall

J18 SS (10 nF) Install

JP1 SEL Jump pins 1 and 2

JP2 PR1 Jump pins 2 and 3

JP3 ST Jump pins 2 and 3

JP4 ILIM (4.5 A maximum) Jump pins 2 and 3

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Board Layout

SLVUBD2A–September 2018–Revised January 2019

TPS212x Evaluation Module

The default jumper configuration sets the Internal Voltage Reference (VREF) configuration. Since the

voltage on the priority pin is set for 3.3-V operation and SEL is grounded, the priority is given to VIN1.

Therefore, VIN1 can be set to 3.3 V, and the device will prioritize VIN1 even if VIN2 is at a higher voltage.

See the data sheet for more information regarding the configuration settings.

4 Board Layout

Figure 1 and Figure 2 show the test equipment setup for the TPS2121 and TPS2120, respectively.

Figure 1. TPS2121 Setup With Test Equipment

Board Layout

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Figure 2. TPS2120 Setup With Test Equipment

J14

J15

VIN1

2.7V to 22V

GND

VOUT

4A Max

GND

VOUTVIN1

J21

VIN2

2.7V to 22V

GND

OV1 Resistors

GND

JP1

GND

JP2

GND

PR1 Resistors

VIN1

PR1

VIN2

ST Connector

R13

GND

OV2 Resistors

GND

OV2

CP2

OV2

PR1_TP

ST_TP

OV1_TP OV2_TP

VIN2

GND

GND GND

JP3

GND

Cout Capacitors Rout Resistors Female Header

Vout

J16

XREF/CP2_TP

Recommended input voltages:

3.3V 5V 12V 3.3V 5V 12V

CP2 Resistors

0.1uF

C10

GND

VIN1

GND GND GND GND GND GND GND GND

GND

20V

0.1uF

C11

10.2k

R10

18.2k

R11

13.7k

23.7k

63.4k

5.00k

R14

OV1

13.7k

23.7k

63.4k

5.00k

R17

0.01uF

C12

1uF

C13

TP1

TP4

TP5

TP8

TP11

TP9

TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19

TP3

TP2

TP6

TP10

TP7

5.00k

R15

GND

IN1

7OUT 1

ST 9

ILM 10

SS 11

GND 12

OUT 8

IN2

CP2

OV2

OV1 5

PR1

TPS2121RUXR

OV1

PR1

CP2

20V

GND

100uF

220uF

GND

100uF

GND

0.1uF

GND GND

0.1uF

GND GND

0.1uF

51.1k

R20

21.5k

R21

R18

R19

3.3V, 5V, and 12V @ 4A Imax

J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12

J13

J17 J18 J19 J20

J22 J23

Maximum Output Voltage: 22V

PR1

ILIM

49.9k

R12

10.7k

R16

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Schematic

SLVUBD2A–September 2018–Revised January 2019

TPS212x Evaluation Module

5 Schematic

Figure 3 illustrates the TPS2121 schematic and Figure 4 illustrates the TPS2120 schematic.

Figure 3. TPS2121 Schematic

J10

J11

VIN1

2.7V to 22V

GND

VOUT

4A Max

GND

VOUTVIN1

J17

VIN2

2.7V to 22V

GND

OV1 Resistors

GND

JP2

GND

JP3

GND

PR1 Resistors

VIN1

PR1

VIN2

ST Connector

R10

GND

OV2 Resistors

GND

OV2

PR1_TP

ST_TP

OV1_TP

OV2_TP

VIN2

GND

GND GND

JP4

GND

Cout Capacitors Rout Resistors Female Header

Vout

J16

Recommended input voltages:

3.3V 5V 12V 3.3V 5V 12V

3.3V 5V 12V

0.1uF

C11

GND

VIN1

GND GND GND GND GND GND GND GND

GND

20V

0.1uF

C12

10.2k

18.2k

R8 13.7k

23.7k

63.4k

5.00k

R11

OV1

13.7k

23.7k

63.4k

0.01uF

C13

1uF

C14

TP1

TP3

TP4

TP7

TP11

TP8

TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19

TP2

TP5

TP10

TP6

5.00k

R12

GND

OV1

PR1

20V

GND

100uF

220uF

GND

100uF

GND

0.1uF

GND GND

0.1uF

GND GND

0.1uF

C10

51.1k

R17

21.5k

R18

R15

R16

3.3V, 5V, and 12V @ 3A Imax

IN1

OUT C3

ST E1

ILM E2

SS E3

GND E4

OUT C2

IN2

IN1

OV2

OV1 A2

PR1

IN1

SEL

IN2

OUT D1

OUT D2

OUT D3

OUT D4

TPS2120YFPR

SEL

JP1

0.1uF

C110.0k

R14

GND

SEL

PR1

Select

TP9

Maximum Output Voltage: 22V

J1 J2 J3 J4 J5 J6 J7 J8 J9

J18 J19

J12 J13 J14 J15

PR1

ILIM

49.9k

10.7k

R13

Schematic

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Figure 4. TPS2120 Schematic

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