Texas Instruments FPD23DAEVM Manuel utilisateur

FPD23DAEVM User's Guide

User's Guide

Literature Number: SNLU144

may 2013

Chapter 1

SNLU144–may 2013

Introduction

1.1 FPD23DAEVM

FPD23DAEVM is designed to directly adapt to one of the following types of RGB data and source

HDMI/DVI compatible video output.

• FPD-Link I (Four LVDS data/control streams and one LVDS clock pair)

• Parallel LVCMOS (RGB888) signals and clock.

Hence, it act as a powerful tool to evaluate performance of FPD-Link II/III Serial link Devices.

The adapter has an on board PanelBus Digital Transmitter, TFP410 which is DVI 1.0-compliant solution.

DVI and HDMI have the same electrical specifications for their TMDS and VESA/DDC links, output of

TFP410 is routed to 19-pin HDMI type-A connector. Hence, hooking up this board with one of the

deserializer in FPD-Link II/III family allows evaluation of the serial link through direct observation of the

video data on HDMI/DVI compatible display.

Figure 1-1. FPD-Link II/III Display Adapter

FPD23DAEVM contains FPD-Link II/III Display Adapter board only. (1)

(1) Other components required: 12V DC Supply, an HDMI cable or HDMI to DVI adapter cable, an HDMI or DVI compatible display.

2Introduction SNLU144–may 2013

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FPD23DAEVM Features

1.2 FPD23DAEVM Features

1. PanelBus Digital Transmitter, TFP410 supports flat panel display resolutions up to UXGA and

maximum pixel rate of 165 MHz in 24-bit true color pixel format.

2. It can accept FPD-Link I input or parallel LVCMOS (RGB888) input based on a simple set of hardware

configuration.

3. Although designed to be used with an HDMI cable, it is easy to hook up the output to DVI display using

an HDMI to DVI adapter cable.

4. Once a DC supply of 12V (recommended current limit is 500mA) is connected to FPD23DAEVM, it can

supply 3.3V (400mA) DC to other devices used in the system such as deserializer.

5. Optionally, PCF8582C-2 can be populated, which is connected to on board I2C bus and allows

implementation of EDID.

6. TFP410 allows minimization of the skew between parallel RGB data and clock signal through a control

switch (S1).

7. TPD8S009 and TPD4E001 provide ESD protection at the output for display port.

1.3 Typical Application

Figure 1-2 below illustrates a typical setup for FPD23DAEVM with either FPD-Link I source or parallel

LVCMOS (RGB888) as a source for RGB data and clock signals. These signals are then translated into

TMDS for transmission over HDMI cable.

Figure 1-2. Typical Application/Evaluation Configuration

SNLU144–may 2013 Introduction

Chapter 2

SNLU144–may 2013

Quick Start Guide

This chapter provides minimal steps required to setup FPD23DAEVM in the two hardware configuration

depending upon the type of input signals. Switch and jumper position required for this operation have

been set at the factory.

1. Verify the factory settings for the adapter board as shown in Figure 2-1 and Figure 2-2.

2. Connect either FPD-Link I input to J3 or parallel LVCMOS (RGB888) input to J2. Make sure that board

is configured for corresponding input type, refer to Section 2.1 and Section 2.2.

3. Connect 12V power supply to either J6 or J1 as shown in . LED D1(green) indicates that board is

correctly powered up and 3.3V(200mA) supply is available at J5.

4. Connect an HDMI/DVI compatible display device to J4 using an HDMI cable. Desired results can be

observed on the display. (2)

2.1 Board Setup with FPD-Link input

In this configuration, connect input to J3 and instructions below should be followed,

1. Make sure RN5, RN6, RN7 and RN8 are mounted.

2. To avoid stubs, RN1, RN2, RN3 and RN4 should not be mounted.

3. Verify pin HIGH and PDN to be shorted on JP2 while using FPD-Link I input.

Figure 2-1. FPD23DAEVM with FPD-Link input

(2) MSEN/PO1 signal on TP4 should be high, once the display/receiver connected to J4 is detected properly.

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Board Setup with Parallel LVCMOS input

2.2 Board Setup with Parallel LVCMOS input

In this configuration connect input to J2 and instructions below should be followed,

1. Make sure RN1, RN2, RN3 and RN4 are mounted.

2. RN5, RN6, RN7 and RN8 should not be mounted to avoid stubs.

3. Verify pin VSS and REF to be shorted on JP6 while using RGB888 parallel LVCMOS input.

Figure 2-2. FPD23DAEVM with Parallel LVCMOS input

SNLU144–may 2013 Quick Start Guide

Chapter 3

SNLU144–may 2013

Evaluation Hardware Overview

FPD23DAEVM includes circuits and interfaces facilitating the full control over the devices present on the

board.

3.1 Power

FPD23DAEVM can be powered up by 6V(min) to 12V(max) DC supply as detailed in Figure 2-1 and

Figure 2-2.Apply power to only ONE of these ports: J1 or J6.

Table 3-1. Power

Reference Description and Default settings

12V power port

J1 Do not apply more than 12V and less than 6V DCsupply to this port.

12V power jack

J6 Do not apply more than 12V and less than 6V DCsupply to this port.

3.3V power port

J5 This port can be used to power up the Deserializer board to which the adapter is connected. It can

source up to 400mA of current.

3.2 Video Data Input

As mentioned earlier, there two input options available.

NOTE: To ensure electrical signal compatibility,

1. Board is by default configured for LVCMOS threshold of VIH(min)= 2.31V and

VIL(max)= 0.99V for the PanelBus Transmitter, TFP410. This allows using this

board with deserializer VDDIO = 3.3V.

2. To work with low signal swings (with deserializer VDDIO = 1.8V), change R7 to

40kΩand R8 to 15kΩ. This hardware change corresponds to VIH(min)= 1.1V and

VIL(max)= 0.7V.

3.2.1 FPD-Link Video Data Input

Header J3 (mounted on bottom side) accepts a 20-pin IDC or similar 0.1" spaced male header. Connect

the clock and 4 FPD-Link (LVDS) data pairs to this header as marked on the silk screen. 100Ωdifferential

termination is provided on the board near DS90CF386 (U4) device pins.

Figure 3-1. FPD-Link Input header: J3

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Video Output

3.2.2 Parallel LVCMOS Video Data Input

Header J2 (mounted on bottom side) accepts R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK as inputs. The

even numbered pins are the inputs. The odd numbered pins are connected to REF (pin 2 of JP6). Jumper

JP6 is factory set to select VSS as a reference.

Figure 3-2. Parallel LVCMOS Input header: J2

3.3 Video Output

Connect an HDMI cable between connector J4 and an HDMI display OR

An HDMI to DVI adapter cable can be used to connect to a DVI display.

3.4 Hardware controls

Hardware controls present on the board determines the specific mode or state of operation.

Table 3-2. Description : Control element

Reference Description and Default settings

Allows access to multifunction input (pin 6, 7, 8) of TFP410.

For more details on function of these pin, refer Table 3-3 and device datasheet.

JP1 Default : CTL[3:1] = 100

To pull these pins High or Low, switch S1 can be used.

Connected to PDN pin of DS90CF386.

HIGH: DS90CF386 CMOS output will be switching. (This condition is required while using FPD-Link I

JP2 input)

LOW: DS90CF386 CMOS output will be low.

I2C clock port

JP3 Allows access to SCL pin of TFP410(U1), U3 and DDC_C (1).

I2C serial data port

JP4 Allows access to SDA pin of TFP410(U1), U3 and DDC_D (2).

Address select port for U3

JP5 It allows to select an appropriate address for U3 (PCF8582C-2, not provided) in the range 0x50 to 0x57.

Default : floating

To select appropriate reference for LVCMOS inputs.

JP6 Default : LVCMOS inputs refer to VSS.

It also allows strapping of parallel LVCMOS input connector pins.

Allows shorting schottky diode D3, if required.

JP7 Default : Open

This switch controls the operation of TFP410 PanelBus digital transmitter only and the default settings

are listed below,

S1.10 : CTL3 : HIGH, Default de-skew settings, although de-skew is disabled.

S1.9 : CTL2 : LOW, Default de-skew settings, although de-skew is disabled.

S1.8 : CTL1 : LOW, Default de-skew settings, although de-skew is disabled.

S1.7 : EDGE/HTPLG : LOW, Falling edge of input clock IDCK+ selected for primary latch to occur

S1 S1.6 : ISEL/RST : LOW, I2C disabled

S1.5 : DSEL/SDA : LOW, Single ended input clock mode

S1.4 : BSEL/SCL : HIGH, 24-bit, single edge input mode

S1.3 : DKEN : LOW, De-skew disabled

S1.2 : NONE : LOW, not used

S1.1 : PD : HIGH, TFP410 is in normal operation mode

Refer Table 3-3 for detailed description of TFP410 control associated with this switch.

(1) Pull up is not present for DDC_C pin.

(2) Pull up is not present for DDC_D pin.

SNLU144–may 2013 Evaluation Hardware Overview

Indicators and Test points

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Table 3-3 below describes function of switch S1 in more detail.

Table 3-3. Switch S1 Functions

Description

Switch Control

position I2C Disabled (ISEL/RST= LOW) I2C Enabled (ISEL/RST= HIGH)

When De-skew mode is disabled (DKEN= Acts as 3 LSBs of the 7 bit I2C address of

LOW), CTL2 & CTL1 can be used to send TFP410,

additional information across the DVI link A[3:1]=000 to select 7 bit I2C address as 0x38

during blanking interval (DE= LOW).

S1.10 CTL3 through

S1.9 CTL2 When De-skew mode is enabled (DKEN= A[3:1]=111 for 0x3F.

S1.8 CTL1 HIGH), these 3 inputs become DK[3:1], used Based on read or write operation 1 or 0 is

to adjust the setup and hold times of the appended to form the 8 bit I2C address, refer

pixel data inputs relative to IDCK+. Refer device datasheet for more details.

device datasheet for more details.

HIGH : Primary latch occurs on the rising

edge of IDCK+ Used to monitor the hot plug detect signal.

LOW : Primary latch occurs on the falling Make sure that R4 is mounted, R13 is not

S1.7 EDGE/HTPLG edge of IDCK+ mounted and S1.7 is set HIGH for the

Make sure that R13 is mounted and R4 is operation.

not mounted for the operation.

S1.6 ISEL/RST LOW : I2C disabled HIGH : I2C enabled

Depends upon VREF and BSEL, refer This switch should be positioned high for the

S1.5 DSEL/SDA TFP410 device datasheet. external pull up on SDA line.

HIGH : selects 24-bit input, single ended

input mode. This switch should be positioned high for the

S1.4 BSEL/SCL LOW : selects 12-bit input, dual edge input external pull up on SCL line.

mode.

HIGH : Enables de-skew with the trim

increment selected through S1.10, S1.9, This pin should be tied either to GND or to

S1.3 DKEN S1.8 VDD and avoid floating input. De-skew function

LOW : Disables de-skew and default trim can be accessed through I2C.

setting is used

S1.2 Not used - -

In this mode, PD pin should be tied to GND.

HIGH : Normal operating mode

S1.1 PD Power down state is selected through I2C and

LOW : Power down mode default mode is Power down.

3.5 Indicators and Test points

Table 3-4. Description : Indicators and Test points

Reference Description

D1 3.3V LDO supply indicator : Green LED

Hot plug detect / Edge Select : Red LED

• By default (I2C disabled on TFP410), it will indicate the status of the input clock (IDCK+) edge

selected (though S1.7) for primary latch on TFP410,

D2 HIGH : Rising edge

TP1 LOW : Falling edge (default)

Make sure that R13 is mounted and R4 is not mounted for the operation.

• When I2C enabled, it indicates hot plug detect signal status.

Make sure that R4 is mounted, R13 is not mounted and S1.7 is set high for the operation.

TP2 HDMI CEC pin test point

TP3 Programming time control output of U3

Monitor sense/ programmable output of TFP410

• When I2C is disabled,

HIGH level on this pin indicates a receiver is detected at the differential outputs,

TP4 Low level indicates a power on receiver is not detected

• When I2C is enabled, this output is programmable through I2C interface, refer TFP410 device

datasheet for more details.

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I2C and Device Addressing (3)

3.6 I2C and Device Addressing (1)

FPD23DAEVM provides flexibility to configure I2C bus as per the requirement.

Figure 3-3. I2C and Device Addressing

1. Header J7 is directly connected to U3 as shown in Figure 3-3, which allows implementation of external

EDID (2) (it requires mounting PCF8582C-2 on board). When 12V is supplied to the EVM, SCL and

SDA lines are pulled high to 5V by resistor R19 and R25 on the board.

The SCL and SDA lines are also connected to pin 1 of JP3 and JP4 respectively.

I2C device address of U3 can be configured by connecting the JP5 pins to either VSS or VDD. Refer

PCF8582C-2 device datasheet for more details.

2. Pin2 of JP3 and JP4 are connected to BSEL/SCL and DSEL/SDA pins of U1, TFP410. Note that, to

communicate with TFP410 over I2C proper settings are required on switch S1. Refer Table 3-3.

3. Pin3 of JP3 and JP4 are connected to DDC_C and DDC_D lines from the HDMI connector, J4. This

might be useful while using the actual EDID of the display.

(1) Unless resistor R19 and R25 are removed, do not put jumper across pin 1 and 2 of either JP3 or JP4. This may damage TFP410 on the

board.

(2) EDID (Extended Display Identification Data) is a display's feature of describing its identity and capabilities to the source, e.g.: video

formats, audio formats, colorimetry, lip-sync delays, etc.

SNLU144–may 2013 Evaluation Hardware Overview

Chapter 4

SNLU144–may 2013

Using Internal Test Pattern Generation of 720p FPD-Link

III Devices

This section provides basic steps to use Internal Test Pattern Generator of 720p FPD-Link III devices to

observe the output on HDMI/DVI compatible display through FPD23DAEVM.

ALP provides an interactive GUI to control the internal pattern generator of DS90Ux92x family of devices

as shown below.

Here, a specific example of DS90UH925 & DS90UH926 serial link is considered, however similar

procedure applies to other members of DS90Ux92x family.

1. Connect USB cable to DS90UH925QSEVB and launch ALP. Once DS90UH925 is detected by the

software as shown in Figure 4-1, click on the device name and select Pattern Generator tab.

Figure 4-1. Initial Window

10 Using Internal Test Pattern Generation of 720p FPD-Link III Devices SNLU144–may 2013

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