19.1 PWM Overview ....................................................................................................... 88
19.2 PWM Instances in F 310-G000 ...............................................................................89
19.3 PWM Memory Map .................................................................................................89
19.4 PWM Count Register (pwmcount)............................................................................90
19.5 PWM Configuration Register (pwmcfg).....................................................................91
19.6 Scaled PWM Count Register (pwms).........................................................................92
19.7 PWM Compare Registers (pwmcmp0–pwmcmp3)........................................................92
19.8 Deglitch and Sticky Circuitry.....................................................................................93
19.9 Generating Left- or Right-Aligned PWM Waveforms ...................................................94
19.10 Generating Center-Aligned (Phase-Correct) PWM Waveforms ..................................94
19.11 Generating Arbitrary PWM Waveforms using Ganging ..............................................95
19.12 Generating One-Shot Waveforms ...........................................................................96
19.13 PWM Interrupts..................................................................................................... 96
20 Debug ...................................................................................................................... 97
20.1 Debug CSRs .......................................................................................................... 97
20.1.1 Trace and Debug Register Select (tselect)....................................................97
20.1.2 Trace and Debug Data Registers (tdata1-3)..................................................98
20.1.3 Debug Control and Status Register (dcsr).......................................................99
20.1.4 Debug PC dpc ...............................................................................................99
20.1.5 Debug Scratch dscratch...............................................................................99
20.2 Breakpoints ............................................................................................................ 99
20.2.1 Breakpoint Match Control Register mcontrol ..................................................99
20.2.2 Breakpoint Match Address Register (maddress).............................................101
20.2.3 Breakpoint xecution ....................................................................................101
20.2.4 Sharing Breakpoints Between Debug and Machine Mode ................................102
20.3 Debug Memory Map..............................................................................................102
20.3.1 Component Signal Registers (0x100–0x1FF).................................................102
20.3.2 Debug RAM (0x400–0x43f)........................................................................103
20.3.3 Debug ROM (0x800–0xFFF)........................................................................103
21 Debug Interface................................................................................................ 104
21.1 JTAG TAPC State Machine ....................................................................................104
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