Sensl HRM-TDC Manuel utilisateur

USER MANUAL

HRM-TDC

High Resolution Time-to-Digital Converter Module

Document Overview

This document provides the user with a comprehensive

description of the hardware and software of the HRM-

TDC module, including system description, the various

timing modes, software GUI and DLL drivers. The

document is split up into the following sections:

GETTING STARTED

This section provides instructions for unpacking the HRM-TDC and a brief overview.

SYSTEM DESCRIPTION

This section gives a description of the system hardware, the various ports and communication channels, the internal

processor, and the specic timing features.

SENSL INTEGRATED ENVIRONMENT (SIE)

The SIE is a user interface for setting up and controlling the HRM-TDC module. While the interface provides an

extensive range of operating modes and measurement processes, including graphical presentation, it does not fully

cover all features available in the HRM-TDC module. This section of the User Manual includes instructions for the

installation of the necessary software, and detailed description of each part of the SIE and how to set up and use it.

APPENDIX

The HRM-TDC DLL provides a set of functions that will allow full control of the HRM-TDC for all features. For

complex experiments that require control beyond the scope of the SIE, it is expected that the user will write their own

real-time application utilizing the various functions in this DLL. The Appendix of the User Manual covers Registers,

low level DLL functions, high level DLL functions, DLL error reporting and examples, as well as help and examples

for resolving time-tag values,an explanation of the correlation function used and the Labview drivers provided.

USER MANUAL

HRM-TDC

> Contents > Getting Started

Contents

Document Overview.................................................................................................................................. 1

Glossary..................................................................................................................................................... 5

Getting Started.......................................................................................................................................... 6

Contact & Support................................................................................................................................. 6

Unpacking the System and Preparing for Use........................................................................................ 6

Safety Considerations............................................................................................................................ 6

System Installation Procedures .............................................................................................................. 6

Signal Inputs and Outputs ..................................................................................................................... 8

I/O Port Connector Pin Allocation .......................................................................................................... 8

HRM-TDC System Description................................................................................................................. 9

Block Diagram....................................................................................................................................... 9

Memory ........................................................................................................................................ 9

Time-to-Digital Converter Module ................................................................................................. 9

High Speed USB 2.0 Interface ...................................................................................................... 9

16-Bit General Purpose I/O Port ................................................................................................... 10

System Processor and Controller.................................................................................................. 10

System Processor and Controller Detailed Description........................................................................... 10

Command Interpreter.................................................................................................................... 10

DMA to USB Fast Transfer Interface.............................................................................................. 11

Time-Bin and Time-Tag Controller................................................................................................. 11

Data Router Module...................................................................................................................... 11

Address Router Module ................................................................................................................ 11

Dual Port Memory Arbiter ............................................................................................................. 11

HRM-TDC Specic Feature Overview .................................................................................................... 12

HISTOGRAM ................................................................................................................................ 13

FIFO ............................................................................................................................................. 13

Histogram – Single-stop (“TCSPC” MODE) ............................................................................................ 14

Histogram – Multi-stop (“Multiscaler/Counter”)....................................................................................... 15

USER MANUAL

HRM-TDC

> Contents > Getting Started

FIFO – Single-stop (“TCSPC - with Macro-Time”)................................................................................... 16

FIFO – Multi-stop (“FIFO - Time Tagging”) .............................................................................................. 17

SensL Integrated Environment (SIE) ........................................................................................................ 18

System Requirements............................................................................................................................ 18

Installation ............................................................................................................................................. 18

Using the SensL Integrated Environment (SIE) ....................................................................................... 19

Main Page .................................................................................................................................... 19

Module Information....................................................................................................................... 19

“HISTOGRAM –TCSPC” (Histogram Single-stop).......................................................................... 20

“HISTOGRAM – Multi-scaler” (Histogram Multi-stop) .................................................................... 22

“FIFO – TCSPC with MACRO time” (FIFO Single-stop).................................................................. 23

“FIFO – Time Tagging” (FIFO – Multi-stop)..................................................................................... 26

Correlation .................................................................................................................................... 30

Appendix ................................................................................................................................................... 32

HRM-TDC Registers and Low Level DLL Functions ............................................................................... 32

Initialization Low Level Drivers ....................................................................................................... 32

ARR – Address Route Register ..................................................................................................... 33

DRR – Data Route Register........................................................................................................... 35

LAL, LAH – Load Address LO/HI Register..................................................................................... 36

LFL, LFH – Load Fill Value LO/HI Register..................................................................................... 37

UAL, UAH – Load Address LO/HI Register ................................................................................... 37

MBR – Mode Bits Register............................................................................................................ 38

ESR – Edge Sensitivity Register .................................................................................................... 39

RRR – Routing Reset Register....................................................................................................... 40

MCL, MCH – Memory Count LO/HI Register ................................................................................ 40

FSR – Frequency Select Register .................................................................................................. 41

IDR – I/O Direction Register .......................................................................................................... 41

IVR – I/O Value Register ................................................................................................................ 41

BCL, BCH – Bin Count LO/HI Register ......................................................................................... 42

UCL, UCH – USB Count HI/LO Register ....................................................................................... 42

USER MANUAL

HRM-TDC

> Contents > Getting Started

HRS, HRM-TDC Status Register................................................................................................... 43

PCR – Product Code Register ...................................................................................................... 44

SRR – Software Revision Register................................................................................................. 44

MIR – Module ID 1, 2, 3, 4 Register .............................................................................................. 44

WCH – Write Count HI Register .................................................................................................... 45

WCL – Write Count LO Register.................................................................................................... 45

Non-Register Specic Low Level Drivers....................................................................................... 46

High Level DLL Functions ...................................................................................................................... 48

DLL Error Reporting............................................................................................................................... 56

DLL Application Examples ..................................................................................................................... 57

Resolving Free Running FIFO Time-Tag Values ...................................................................................... 66

Free Running Algorithm Explained................................................................................................. 66

Resync Algorithm Explained.......................................................................................................... 68

Correlation Function Algorithm............................................................................................................... 70

Labview Driver details ............................................................................................................................ 71

HRM-TDC LabView Driver VI List .................................................................................................. 71

Sample LabView Application......................................................................................................... 84

USER MANUAL

HRM-TDC

> Glossary > Getting Started

Glossary

Here are words and phrases used in this user manual in relation to the HRM-TDC module.

SIE - SensL Integrated Environment - the GUI that runs on the SensL DLL and provides an example

program allowing the user to make measurements with the HRM-TDC.

LSB - Least Signicant Bit: The right most bit in a binary integer, and in the case of the HRM-TDC

it determines the minimum timing resolution possible.

Histogram - The use of consecutive memory locations to store counts that represent points on a graph.

Each memory location represents a time range that can be specied via software, down to

the LSB value of the HRM-TDC (27ps).

FIFO - First In, First Out: in the HRM-TDC, timing data can be stored in memory before being

downloaded to the PC. FIFO is analogous to putting the data into a queue in memory,

whereby the rst loaded in, will also be the rst downloaded to the PC.

TCSPC - Time Correlated Single Photon Counting: A technique used to study properties of molecules

by exciting with a laser source and measuring the subsequent relaxation time through the

acquisition of lifetime curves.

Time bin - The time interval covered by one memory location in one of the HRM-TDC’s Histogram

modes.

Time Tag - The timing value recorded between a START of a STOP signal, in one of the HRM-TDC’s

FIFO modes.

Curve - The data resulting from one of the HRM-TDCs histogramming modes.

Micro time - The timing value between a START signal and any given STOP signal in FIFO single-stop

(TCSPC) mode. In the FIFO multi-stop (time-tagging) mode, it refers to the value of the high-

resolution TDC when the event occured.

Macro time - The time elapsed since the experiment began in FIFO single-stop (TCSPC) mode. In FIFO

multi-stop (time-tagging) mode, it refers to the the coarse timer that, used in conjunction with

the micro-time, allows the user to determine the absolute time of the event.

USER MANUAL

HRM-TDC

> Getting Started > Contact & Support

Getting Started

CONTACT & SUPPORT

For all enquiries, please email: [email protected]

Supporting documentation can be found on the SensL website at www.sensl.com/documentation/

Downloadable copies of the SensL HRM-TDC software and release note can be found at

www.sensl.com/support/sw/

UNPACKING THE SYSTEM AND PREPARING FOR USE

Unpack the contents and identify each of the components.

• HRM-TDC Module

• Power Supply, with country specic connector

• USB cable

SAFETY CONSIDERATIONS

1. Only use the power supply supplied with the HRM-TDC module.

2. The power supply should be disconnected from the mains supply when the module is not in use.

3. The module is not intended for outdoor use

4. The power supply should not be opened nor should the module covers be removed at any time as there

are no user adjustable components or settings, except via the SensL Integrated Environment Software.

5. Liquids should not be spilled on or into the module.

SYSTEM INSTALLATION PROCEDURES

For software driver and SensL Integrated Environment installation instructions see the SIE User Guide on page 18

of this document.

Please follow the instructions carefully and ensure you have installed the QuickUSB drivers as instructed.

USER MANUAL

HRM-TDC

> Getting Started > System Installation Procedures

SYSTEM CHARACTERISTICS AND SPECIFICATIONS

Dimensions 164mm (L) x 96mm (W) x 34 mm (H)

Weight 680g

Power +5V @ 0.65 A

Temperature Operating: 0°C to +50°C

Storage: -20°C to +70°C

Specications

Number of channels per module 4

Time channels per curve 1 to 4,194,304

Number of curves in memory 1 to 4,194,304

Input voltage range LVTTL (5V TTL tolerant)

START/STOP channels input impedance 51kW

Minimum input pulse width 6ns

Minimum Time/Channel 27ps

Histogram/channel depth 65,535 or 4,294,967,295 bits (16 or 32 bits)

Dead time 190ns

Saturated count rate 4.5MHz

Usable count rate 9MHz *

Burst rate timing Up to 100MHz (Mode dependent)

Macro Timing resolution Down to 5ns

Memory size 8Mbytes

Memory format Dual ported linear or dual ported FIFO (mode

dependent)

Readout during operation Fully dual-ported memory (no stop start operation

required)

Multi detector operation Up to 4

Multi module operation Number depends on USB capability of PC

I/O control 16 fully programmable I/O ports

Software SensL Integrated Environment (SIE) and DLL

drivers

PC Interface High speed USB 2.0

* Useful count rate is maximum count rate without loss of greater than 50%

USER MANUAL

HRM-TDC

> Getting Started > Signal Inputs And Outputs

SIGNAL INPUTS AND OUTPUTS

Figure 1 HRM-TDC ports and connectors labelled

AChannel 0 Start Input (SMA LVTTL*) BChannel 0 Stop Input (SMA LVTTL*)

CChannel 1 Start Input (SMA LVTTL*) DChannel 1 Stop Input (SMA LVTTL*)

EChannel 2 Start Input (SMA LVTTL*) FChannel 2 Stop Input (SMA LVTTL*)

GChannel 3 Start Input (SMA LVTTL*) HChannel 3 Stop Input (SMA LVTTL*)

I USB connector JLEMO power supply connector (for SensL PSU use only)

K 26-way I/O port connector L Programmable Clock output (SMA LVTTL 50W)

* 5V TTL tolerant

I/O PORT CONNECTOR PIN ALLOCATION

Pins 1 to 16: I/O ports 0 to 15 respectively

Pin 17: Test clock signal ENABLE (LO to disable test clocks)

Pin 18 to 22: Test clock signals (outputs)

Pin 23, 24: +5v

Pin 25, 26: Ground

ABCD

L K

JIEFGH

USER MANUAL

HRM-TDC

> Hrm-tdc System Description > Block Diagram

HRM-TDC System Description

BLOCK DIAGRAM

Data

Control

Start 0

Stop 0

High Speed 2.0

USB Interface

Time to Digital

Converter Module

Time to Digital

Converter Module

Time to Digital

Converter Module

Time to Digital

Converter Module

Memory

(8 MB)

16-bit General

Purpose

I/O Port LVTTL

System Processor

and

Controller (FPGA)

Start 1

Stop 1

Start 2

Stop 2

Start 3

Stop 3

Figure 2 An overview of the HRM-TDC operation

The HRM-TDC system consists of 4 ‘time-to-digital’ modules (each having a START and a STOP input), 16 I/O

ports, a high speed USB interface, memory storage and an FPGA based processor, as depicted in Fig. 2. The

purpose of each element is as follows:

Memory

The memory module is an HRM-TDC format plug-in mezzanine board providing 8 Mbytes of memory.

Time-to-Digital Converter Module

This module is the front end of the system and is responsible for resolving the timing between the START and STOP

inputs of each of up to four channels. Each channel is controlled by the FPGA and can be programmed to start and

stop on either LO-HI or HI-LO transitions.

High Speed USB 2.0 Interface

The USB interface is used to command/congure the HRM-TDC as well as download, in real-time, timing data to the

host computer. This USB interface implements high speed USB 2.0 protocol allowing real time continuous logging

of timing data up to rates of 4.5MHz without data loss.

USER MANUAL

HRM-TDC

> Hrm-tdc System Description > System Processor And Controller Detailed Description

16-Bit General Purpose I/O Port

This general purpose I/O port is used to allow multi-dimensional curve readings. The position of curve data, within

the system memory, can be dened by these ports. These ports can be set directly by outside control lines (inputs)

or by software to drive outside equipment (outputs).

System Processor and Controller

The ‘System Processor/Controller’ is responsible for implementing all the functionality of the HRM-TDC module.

This module decodes commands from the USB and executes the timing function accordingly. All results are saved

in memory as either time-bins for curve measurements or time-tags for continuous recording. In this latter mode

the memory is congured as a large FIFO to allow continuous downloading of time-tag data up to rates of 4.5MHz.

SYSTEM PROCESSOR AND CONTROLLER DETAILED DESCRIPTION

Figure 3 Overview of the system processor and controller

Command Interpreter

This module is responsible for receiving a set of commands from the host computer and controlling the system

accordingly. HRM-TDC is a fully programmable system with a wide range of parameters that can be user dened.

The Command Interpreter is responsible for setting these parameters and starting the execution of a particular task.

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