
iv CM4 User’s Guide—SBS Technologies
Preliminary
3.12 Ethernet I/O Communications ............................................................................3-16
3.13 System Controller vs. Peripheral Operation .......................................................3-16
3.14 Reset Circuitry ....................................................................................................3-17
3.14.1 Hard Resets ..............................................................................................3-17
3.14.2 Soft Resets ...............................................................................................3-20
3.14.3 PCI Resets ................................................................................................3-20
3.14.4 Watchdog Timer ......................................................................................3-21
3.15 Interrupt Circuitry ...............................................................................................3-22
3.15.1 PCI Interrupts ...........................................................................................3-22
3.15.2 On-board Interrupts ..................................................................................3-25
3.16 Clock Circuitry ...................................................................................................3-26
3.16.1 24MHz and 14.318MHz Clocks ..............................................................3-26
3.16.2 Real-Time Clock ......................................................................................3-26
3.16.3 Tsi107 Clock Distribution .......................................................................3-27
3.16.4 PCI 6254 PCI Bridge Clock Operation—Transparent Mode ..................3-29
3.16.5 PCI 6254 PCI Bridge Clock Operation—Non-Transparent Mode ..........3-29
Chapter 4: Components
4.1 Component Location .............................................................................................4-1
4.2 Processors .............................................................................................................4-2
4.3 Tsi107 Host Bridge ...............................................................................................4-3
4.3.1 System Bus Interface .................................................................................4-3
4.3.2 Memory Controller and Bus Interface .......................................................4-3
4.3.3 PCI Bus Interface .......................................................................................4-3
4.3.4 Interrupt Controller ....................................................................................4-3
4.4 PCI 6254 PCI Bridge ............................................................................................4-4
4.5 SDRAM ................................................................................................................4-4
4.6 Flash Memory .......................................................................................................4-4
4.6.1 Boot Flash ..................................................................................................4-4
4.6.2 Extended Flash ...........................................................................................4-4
4.7 Decoder CPLD ......................................................................................................4-5
4.8 82559ER Ethernet Controller ...............................................................................4-5
4.9 ST16C2550 Dual Channel UARTs .......................................................................4-5
4.10 STK14C88 NVSRAM ..........................................................................................4-6
4.11 DS1685 Real-Time Clock .....................................................................................4-6
Chapter 5: CPLD Registers
5.1 Watchdog Control Register ..................................................................................5-1
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