Samsung S5PC110 Manuel utilisateur

Rev. 0.0, Jan.2009

S5PC110

RISC Microprocessor

Revision 1.00

February 2010

Rev. 0.0, Jan.2009

Important Notice

The information in this publication has been carefully

checked and is believed to be entirely accurate at the

time of publication. Samsung assumes no

responsibility, however, for possible errors or

omissions, or for any consequences resulting from the

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products or product specifications with the intent to

improve function or design at any time and without

notice and is not required to update this

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semiconductor devices described herein any license

under the patent rights of Samsung or others.

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product or circuit and specifically disclaims any and all

liability, including without limitation any consequential

or incidental damages.

"Typical" parameters can and do vary in different

applications. All operating parameters, including

"Typicals" must be validated for each customer

application by the customer's technical experts.

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S5PC110 RISC Microprocessor

User's Manual, Revision 1.00

any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior

written consent of Samsung Electronics.

Samsung Electronics Co., Ltd.

San #24 Nongseo-Dong, Giheung-Gu

Yongin-City, Gyeonggi-Do, Korea 446-711

TEL : (82)-(31)-209-0810

FAX : (82)-(31)-209-0837

Home Page: http://www.samsungsemi.com

Printed in the Republic of Korea

Rev. 0.0, Jan.2009

Revision History

Revision No. Date Description Author(s)

0.00 February 27, 2010 - Initial draft S.H Yoon

Section 1

OVERVIEW

Table of Contents

1 Overview of S5PC110.................................................................................1-1

1.1 Architectural Overview ............................................................................................................................. 1-1

1.2 Block Diagram of S5PC110 ..................................................................................................................... 1-2

1.3 Key Features of S5PC110 ....................................................................................................................... 1-3

1.3.1 Microprocessor ................................................................................................................................. 1-4

1.3.2 Memory Subsystem .......................................................................................................................... 1-5

1.3.3 Multimedia ........................................................................................................................................ 1-6

1.3.4 Audio Subsystem.............................................................................................................................. 1-9

1.3.5 Security Subsystem.......................................................................................................................... 1-9

1.3.6 Connectivity .................................................................................................................................... 1-10

1.3.7 System Peripheral .......................................................................................................................... 1-13

1.4 Conventions ........................................................................................................................................... 1-15

1.4.1 Register R/W Conventions ............................................................................................................. 1-15

1.4.2 Register Value Conventions ........................................................................................................... 1-15

2 Memory Map ...............................................................................................2-1

2.1 Memory Address Map.............................................................................................................................. 2-1

2.1.1 Device Specific Address Space........................................................................................................ 2-2

2.1.2 Special Function Register Map......................................................................................................... 2-4

List of Figures

Figure Title Page

Number Number

Figure 1-1 S5PC110 Block Diagram .................................................................................................................. 1-2

Figure 2-1 Address Map..................................................................................................................................... 2-1

Figure 2-2 Internal Memory Address Map.......................................................................................................... 2-3

S5PC110_UM 1 OVERVIEW OF S5PC110

1-1

1 OVERVIEW OF S5PC110

1.1 ARCHITECTURAL OVERVIEW

S5PC110 is a 32-bit RISC cost-effective, low power, and high performance microprocessor solution for mobile

phones and general applications. It integrates the ARM Cortex-A8 core, which implements the ARM architecture

V7-A with supporting peripherals.

To provide optimized Hardware (H/W) performance for the 3G and 3.5G communication services, S5PC110

adopts 64-bit internal bus architecture. This includes many powerful hardware accelerators for tasks such as

motion video processing, display control, and scaling. Integrated Multi Format Codec (MFC) supports encoding

and decoding of MPEG-1/2/4, H.263, and H.264, and decoding of VC1 and Divx. This hardware accelerator

(MFC) supports real-time video conferencing and Analog TV out, HDMI for NTSC, and PAL mode.

S5PC110 has an interface to external memory that is capable of sustaining heavy memory bandwidths required in

high-end communication services. The memory system has Flash/ ROM external memory ports for parallel access

and DRAM port to meet high bandwidths. DRAM controller supports LPDDR1 (mobile DDR), DDR2, or LPDDR2.

Flash/ ROM port supports NAND Flash, NOR-Flash, OneNAND, SRAM, and ROM type external memory.

To reduce the total system cost and enhance the overall functionality, S5PC110 includes many hardware

peripherals such as TFT 24-bit true color LCD controller, Camera Interface, MIPI DSI, CSI-2, System Manager for

power management, ATA interface, four UARTs, 24-channel DMA, four Timers, General I/O Ports, three I2S,

S/PDIF, three IIC-BUS interface, two HS-SPI, USB Host 2.0, USB 2.0 OTG operating at high speed (480Mbps),

four SD Host and high-speed Multimedia Card Interface, and four PLLs for clock generation.

Package on Package (POP) option with MCP is available for small form factor applications.

S5PC110_UM 1 OVERVIEW OF S5PC110

1.2 BLOCK DIAGRAM OF S5PC110

Figure 1-1 shows the complete block diagram of S5PC110.

CPU Core

Memory Interface

Multimedia

Connectivity

System Peripheral

Multi layer AHB / AXI Bus

RTC CortexA8

32KB/32KB I/ D cache

800MHz/1 GHz @1.1V/1.2V

512KB

L 2 cache NEON

96 KB

RAM

64 KB

ROM

Crypto

Engines

12 MP Camera IF/ MIPI CSI-2

1080p 30 fps MFC

Codec H. 263/H. 264/ MPEG4

Decoder MPEG2/ VC-1/ Divx

2 D VG /

3 D Graphics engine

NTSC / PAL TV out

& HDMI

JPEG Codec

SRAM / ROM

PLL x4

Timer with PWM(4ch)

Watchdog Timer

DMA(24ch)

Keypad(14x8)

TS- ADC(12bit/10ch)

Audio IF

IIS x3 / PCM x3

1-2

Power

Management

SPDIF/ AC97

Storage IF

HSMMC/ SD x4

ATA

Connectivity

USB Host 2. 0 / OTG2.0

UART x4

IIC x3

HS- SPI x2

GPIO

Clock gating/

Power gating/

Dynamic Voltage

Frequency Scaling

LPDDR1 / OneDRAM

LPDDR2 / DDR2

SLC / MLC NAND

with 16 bit ECC

Audio

DSP

( Flex) OneNAND

TFT LCD controller

XGA resolution

Modem IF(16KB DPSRAM)

Figure 1-1 S5PC110 Block Diagram

S5PC110_UM 1 OVERVIEW OF S5PC110

1-3

1.3 KEY FEATURES OF S5PC110

The key features of S5PC110 include:

•ARM CortexTM-A8 based CPU Subsystem with NEON

−32/ 32 KB I/D Cache, 512 KB L2 Cache

−Operating frequency up to 800 MHz at 1.1V, 1 GHz at 1.2V

•64-bit Multi-layer bus architecture

−MSYS domain for ARM CortexTM-A8, 3D engine, Multi Format Codec and Interrupt Controller

•Operating frequency up to 200 MHz at 1.1V

−DSYS domain mainly for Display IPs (such as LCD controller, Camera interface, and TVout), and MDMA

•Operating frequency up to 166 MHz at 1.1V

−PSYS domain mainly for other system component such as system peripherals, external memory interface,

peri DMAs, connectivity IPs, and Audio interfaces.

•Operating frequency up to 133 MHz at 1.1V

−Audio domain for low power audio play

•Advanced power management for mobile applications

•64 KB ROM for secure booting and 128 KB RAM for security function

•8-bit ITU 601/656 Camera Interface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for

un-scaled resolution

•Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 720p@30fps and

decoding of MPEG-2/VC1/Divx video up to 720p@30 fps

•JPEG codec supports up to 80 Mpixels/s

•3D Graphics Acceleration with Programmable Shader up to 20M triangles/s and 1000 Mpixels/s

•2D Graphics Acceleration up to 160Mpixels/s

•1/ 2/ 4/ 8 bpp Palletized or 8/ 16/ 24 bpp Non-Palletized Color TFT recommend up to XGA resolution

•TV-out and HDMI interface support for NTSC and PAL mode with image enhancer

•MIPI-DSI and MIPI-CSI interface support

•One AC-97 audio codec interface and 3-channel PCM serial audio interface

•Three 24-bit I2S interface support

•One TX only S/PDIF interface support for digital audio

•Three I2C interface support

•Two SPI support

•Four UART supports three Mbps ports for Bluetooth 2.0

•On-chip USB 2.0 OTG supports high-speed (480 Mbps, on-chip transceiver)

•On-chip USB 2.0 Host support

•Asynchronous Modem Interface support

•Four SD/ SDIO/ HS-MMC interface support

•ATA/ ATAPI-6 standard interface support

S5PC110_UM 1 OVERVIEW OF S5PC110

1-4

•24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA)

•Supports 14x8 key matrix

•10-channel 12-bit multiplexed ADC

•Configurable GPIOs

•Real time clock, PLL, timer with PWM and watch dog timer

•System timer support for accurate tick time in power down mode (except sleep mode)

•Memory Subsystem

−Asynchronous SRAM/ ROM/ NOR Interface with x8 or x16 data bus

−NAND Interface with x8 data bus

−Muxed/ Demuxed OneNAND Interface with x16 data bus

−LPDDR1 Interface with x16 or x32 data bus (266~400 Mbps/ pin DDR)

−DDR2 interface with x16 or x32 data bus (400 Mbps/ pin DDR)

−LPDDR2 interface (400 Mbps/ pin DDR)

1.3.1 MICROPROCESSOR

The key features of this microprocessor include:

•The ARM CortexTM-A8 processor is the first application processor based on ARMv7 architecture.

•With the ability to scale in speed from 600 MHz to 1 GHz (or more), the ARM CortexTM-A8 processor meets

the requirements of power-optimized mobile devices, which require operation in less than 300mW; and

performance-optimized consumer applications require 2000 Dhrystone MIPS.

•Supports first superscalar processor featuring technology from ARM for enhanced code density and

performance, NEONTM technology for multimedia and signal processing, and Jazelle®RCT technology for

ahead-of-time and just-in-time compilation of Java and other byte code languages.

•Other features of ARM CortexTM-A8 include:

−Thumb-2 technology for greater performance, energy efficiency, and code density

−NEONTM signal processing extensions

−Jazelle RCT Java-acceleration technology

−TrustZone technology for secure transactions and DRM

−13-stage main integer pipeline

−10-stage NEONTM media pipeline

−Integrated L2 Cache using standard compiled RAMs

−Optimized L1 caches for performance and power

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