Renesas HD49335HNP Manuel utilisateur

Rev.1.0, Feb.12.2004, page 1 of 29

HD49335NP/HNP

CDS/PGA & 10-bit A/D TG Converter REJ03F0097-0100Z

Rev.1.0

Feb.12.2004

Description

The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera

digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip.

There are address map and timing generator charts besides this specification. May be contacted to our sales department

if examining the details.

Functions

• Correlated double sampling

• PGA

• Serial interface control

• 10-bit ADC

• Timing generator

• Operates using only the 3 V voltage

• Corresponds to switching mode of power dissipation and operating frequency

Power dissipation: 220 mW (Typ), maximum frequency: 36 MHz (HD49335HNP)

Power dissipation: 150 mW (Typ), maximum frequency: 25 MHz (HD49335NP)

• ADC direct input mode

• QFN 64-pin package

Features

• Suppresses low-frequency noise, which output from CCD by the correlated double sampling.

• The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and

registers.

• High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier.

• PGA, pulse timing, standby mode, etc., is achieved via a serial interface.

• High precision is provided by a 10-bit-resolution A/D converter.

• Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization

(wave pattern). It is patented by Renesas.

• Timing generator generates the all of pulse which are needed for CCD driving.

HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 2 of 29

Pin Arrangement

48 47 3946 45 44 43 42 41 40 38 36 35 3437

12 103 4 5 6 7 8 9 11 12 13 14 15

(Top view)

BLKC

CDS_in

BLKFB

BLKSH

Test2

Test1

DLL_C

MON

41cont

SDATA

SCK

XV3

XV2

XV1

1/4clk_o

H2A

1/2clk_o

H1A

Reset

VD_in

VRM

VRT

VRB

BIAS

ADC_in

STROB

SUB_PD

SUB_SW

XSUB

CH4

CH3

CH2

CH1

XV4

1,2

CLK_in

HD_in

Pin Description

Pin No.

Symbol

Description

I/O Analog(A) or

Digital(D)

Remarks

1 ID Odd/even number line detecting pulse output pin O D 2 mA/10 pF

2 DVSS1,2 CDS Digital ground + ADC output buffer ground (0 V) — D

3 to 12 D0 to D9 Digital output (D0; LSB, D9; MSB) O D 2 mA/10 pF

13 DVDD2 ADC output buffer power supply (3 V) — D

14 DVSS3 General ground for TG (0 V) — D

15 CLK_in CLK input (max 72 MHz) I D

16 HD_in HD input I/O D

17 VD_in VD input I/O D

18 Reset Hardware reset (for DLL reset) I D Schmitt trigger

19 RG Reset gate pulse output O D 3 mA/10 pF

20 DVDD3 General power supply for TG (3 V) — D

21 DVDD4 H1 buffer power supply (3 V) — D

22 H1A H.CCD transfer pulse output-1A O D 30 mA/165 pF

23 1/2clk_o CLK_in 2 divided output. 3 divided output at 3 divided mode O D 2 mA/10 pF

24 DVSS4 H1 buffer ground (0 V) — D

25 DVSS4 H1 buffer ground (0 V) — D

26 H2A H.CCD transfer pulse output-2A O D 30 mA/165 pF

27 1/4clk_o CLK_in 4 divided output. 6 divided output at 3 divided mode O D 2 mA/10 pF

28 DVDD4 H2 buffer power supply (3 V) — D

29 DVDD3 General power supply for TG (3 V) — D

HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 3 of 29

Pin Description (cont.)

Pin No.

Symbol

Description

I/O Analog(A) or

Digital(D)

Remarks

30 XV1 V.CCD transfer pulse output-1 O D 2 mA/10 pF

31 XV2 V.CCD transfer pulse output-2 O D 2 mA/10 pF

32 XV3 V.CCD transfer pulse output-3 O D 2 mA/10 pF

33 XV4 V.CCD transfer pulse output-4 O D 2 mA/10 pF

34 CH1 Read out pulse output-1 O D 2 mA/10 pF

35 CH2 Read out pulse output-2 O D 2 mA/10 pF

36 CH3 Read out pulse output-3 O D 2 mA/10 pF

37 CH4 Read out pulse output-4/XV6 at stripe mode O D 2 mA/10 pF

38 XSUB Pulse output for electronic shutter O D 2 mA/10 pF

39 SUB_SW SUB voltage control output-1. ADCK input I/O D 2 mA/10 pF

40 SUB_PD SUB voltage control output-2/ XV5 at stripe mode O D 2 mA/10 pF

41 STROB Flash control output. Input Vgate at Hi of pin 61 I/O D 2 mA/10 pF

42 DVSS3 General ground for TG (0 V) — D

43 AVSS Analog ground (0 V) — A

44 ADC_in AD converter input pin I A

45 BIAS Bias standard resistance — A

46 VRB ADC bottom standard voltage (0.1 µF for GND) — A

47 VRT ADC top standard voltage (0.1 µF for GND) — A

48 VRM ADC middle standard voltage (0.1 µF for GND) — A

49 AVDD Analog power supply (3 V) — A

50 BLKC Black level C pin (1000 pF for GND) — A

51 CDS_in CDS input pin I A

52 AVDD Analog power supply (3 V) — A

53 BLKFB Black level FB pin (1 µF between BLKFB and BLKSH) I A

54 BLKSH Black level S/H pin O A

55 AVSS Analog ground (0 V) — A

56 Test2

H: Normal operation, L: CDS single operation mode

Input 36; PBLK at testing, Input 37; OBP, Input 38; CPDM,

Input 39; ADCK, Input 40; SP2, Input 41; SP1

I D

57 Test1 L: Slave mode, H: Master mode I D

58 DLL_C Analog delay DLL external C pin (100 pF for GND) O A

59 DVDD1 Digital power supply (3 V) CDS, PAG, ADC part — D

60 MON Pulse monitor (SP1, SP2, ADCK, OBP, CPDM, PBLK input) O D 2 mA/10 pF

61 41cont

Input STROB = pin 41, Input SUB_SW = pin 39 at Low

Input Vgate = pin 41, Input ADCK = pin 39 at Hi I D

62 CS Serial data CS at CDS part I D

63 SDATA Input serial data I D

64 SCK Input serial clock I D

HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 4 of 29

Input/Output Equivalent Circuit

Pin Name Equivalent Circuit

D0 to D9, HD_in, VD_in,

H1A, H2A, 1/2clk_o,

1/4clk_o, 41cont,

SUB_SW, SUB_PD

DIN

ENABLE

Digital

output

Digital output

ID, RG, MON, XV1 to XV4,

CH1 to CH4, XSUB

DIN

Digital

output

Digital input CLK_in, HD_in, VD_in,

ADCLK, OBP, SPBLK,

SPSIG, CS, SCK, SDATA,

PBLK, OEB, Reset, Test1,

Test2, SUB_SW, STROB

Digital

input

DVDD

Note: Only OEB is pulled down to about 70 kΩ.

CDS_in

AVDD

Internally

connected

to VRT

ADC_in

DC_in

Internally

connected

to VRT

BLKSH, BLKFB, BLKC

BLKFB

AVDD

BLKSH

BLKC

−

VRT, VRM, VRB

−

VRT

VRM

VRB AV

−

Analog

BIAS

HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 5 of 29

Block Diagram

10bit

ADC

AVSS

VRB

VRM

VRT

CDS_in CDS

BLKSH

BLKC

ADC_in

SUB_SW

SUB_PD

STROB

Reset

DVSS1 to 4

BLKFB

SDATA

SCK

DLL_C

MON

BIAS

Timing

generator

VD_in

HD_in

CLK_in

XSUB

CH4

CH3

CH2

CH1

XV4

XV3

PBLK

CPDM

OBP

ADCLK

SP2

SP1

XV2

XV1

1/4clk_o

H2A

1/2clk_o

H1A

AVDD

DVDD1 to 4

PGA

DLL

Output latch circuit

DC offset

compensation

circuit

Serial

interface

Bias

generator

HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 6 of 29

Internal Functions

Functional Description

• CDS input

 CCD low-frequency noise is suppressed by CDS (correlated double sampling).

 The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *1

 Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *2

• ADC input

 The center level of the input signal is clamped at 512 LSB (Typ).

 Gain can be adjusted using 8 bits of register (0.01784 times steps, register settings) within the range from 0.57

times (–4.86 dB) to 5.14 times (14.22 dB). *2

• Automatic offset calibration of PGA and ADC

• DC offset compensation feedback for CCD and CDS

• Pre-blanking

 Digital output is fixed at clamp level

• Digital outputs enable function

Note: 1. It is not covered by warranty when 14LSB settings

2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

Operating Description

Figure 1 shows CDS/PGA + ADC function block.

DAC

CDS

AMP

CDS_in

BLKFB BLKSH

AMP

VRT

SP1 SP1

SP2 10bit

ADC

D0 to D9

BLKC

OBP

ADC_in

Offset

calibration

logic

DC offset

feedback

logic

Gain setting

(register) Clamp data

(register)

Current

DAC

Figure 1 CDS/PGA Functional Block Diagram

1. CDS (Correlated Double Sampling) Circuit

The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The

black level is directly sampled at C1 by using the SP1 pulse, buffered by the SHAMP, then provided to the

CDSAMP.

The signal level is directly sampled at C2 by using the SP2 pulse, and then provided to CDSAMP (see figure 1).

The difference between these two signal levels is extracted by the CDSAMP, which also operates as a

programmable gain amplifier at the previous stage. The CDS input is biased with VRT (2 V). During the PBLK

period, the above sampling and bias operation are paused.

2. PGA Circuit

The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain

using 8 bits of register.

The equation below shows how the gain changes when register value N is from 0 to 255.

In CDSIN mode: Gain = (–2.36 dB + 0.033 dB) ×N (LOG linear).

In ADCIN mode: Gain = (0.57 times + 0.001784 times) ×N (linear).

Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 7 of 29

3. Automatic Offset Calibration Function and Black-Level Clamp Data Settings

The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration.

The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data

(14 LSB to 76 LSB) set by register are added and input to the DAC.

The automatic offset calibration starts automatically after the RESET mode set by register is cancelled and

terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).

4. DC Offset Compensation Feedback Function

Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets

(including the CCD offset and the CDSAMP offset) are compensated for.

The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged

by the current DAC (see figure 1).

The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is

the one cycle of the OBP.

∆Gain/∆H = 0.078/(fclk ×C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)

Example:When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039

When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop

gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 2 times, 4 times, 8

times, or 16 times by changing the register settings (see table 1). Note that the open-loop differential gain

(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.

The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be

selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 16 LSB, the high-speed lead-in operation continues,

and when the offset error is 16 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4

H, or 8 H depending on the register settings. (Refer to table 2.)

Table 1 Loop Gain Multiplication Factor during

High-Speed Lead-In Operation

Table 2 High-Speed Lead-In Operation

Cancellation Time

HGain-Nsel

(register settings) Multiplication

Factor N

HGstop-Hsel

(register settings) Cancellation

Time

[0]

[1]

[0]

[1]

1 H

8 H

4 H

2 H

5. Pre-Blanking Function

During the PBLK input period, the CSD input operation is separated and protected from the large input signal. The

ADC digital output is fixed to clamp data (14 to 76 LSB).

HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 8 of 29

6. ADC Digital Output Control Function

The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5

show the output functions and the codes.

Table 3 ADC Digital Output Functions

STBY

TEST0

D0D1D2D3D4D5D6D7D8

PBLK

MINV

TEST1

LINV

Hi-Z

Same as in table 4.

D9 is inverted in table 4.

D8 to D0 are inverted in table 4.

D9 to D0 are inverted in table 4.

Output code is set up to Clamp Level.

Same as in table 5.

D9 is inverted in table 5.

D8 to D0 are inverted in table 5.

D9 to D0 are inverted in table 5.

Output code is set up to Clamp Level.

Low-power wait state

Normal operation

Pre-blanking

Normal operation

Pre-blanking

Test mode

Operating Mode

ADC Digital Output

Note: 1. STBY, TEST, LINV, and MINV are set by register.

Table 4 ADC Output Code (Binary)

511

512

1020

1021

1022

1023

Output Pin

Output

codes

Steps

Table 5 ADC Output Code (Gray)

511

512

1020

1021

1022

1023

Output Pin

Output

codes

Steps

HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 9 of 29

7. Adjustment of Black-Level S/H Response Frequency Characteristics

The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the

Table 6 SHSW CR Time Constant Setting

BLKC

Recommendation value of C is 1000 pF

The SHAMP frequency characteristics can be adjusted by changing the register settings

and the C4 value of the external pin.

The settings are shown in table 7.

Values other than those shown in the table 7 cannot be used.

2.20 nsec

(72 MHz)

2.30 nsec

(69 MHz)

2.51 nsec

(63 MHz)

2.64 nsec

(60 MHz)

2.93 nsec

(54 MHz)

3.11 nsec

(51 MHz)

3.52 nsec

(45 MHz)

3.77 nsec

(42 MHz)

[3]

[0]

4.40 nsec

(36 MHz)

4.80 nsec

(33 MHz)

[1]

[2]

5.87 nsec

(27 MHz)

6.60 nsec

(24 MHz)

8.80 nsec

(18 MHz)

10.6 nsec

(15 MHz)

17.6 nsec

(9 MHz)

26.4 nsec

(6 MHz)

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

SHSW-fsel (Register setting)

CR Time Constant (Typ)

(cutoff frequency conversion)

CR Time Constant (Typ)

(cutoff frequency conversion)

Table 7 SHAMP Frequency Characteristics Setting

230 MHz

6800 pF

(240 pF)

56 MHz

18000 pF

(360 pF)

116 MHz

10000 pF

(270 pF)

100 MHz

10000 pF

(560 pF)

"Lo"

"Hi" 24 MHz

27000 pF

(820 pF)

75 MHz

13000 pF

(300 pF)

32 MHz

22000 pF

(750 pF)

49 MHz

15000 pF

(620 pF)

[0]

[1]

[0]

[1]

[0]

[1]

SHA-fsel (Register setting)

LoPwr

(Register setting)

Note: Upper line

Middle line

Lower line

: SHAMP cutoff frequency (Typ)

: Standard value of C4 (maximum value is not defined)

: Minimum value of C4 (do not set below this value)

HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 10 of 29

Timing Chart

Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.

012 91011

N+1 N+2 N+9 N+10 N+11N

CDS_in

SP1

SP2

ADCLK

D0 to D9

N+2

N+8 N+9

N+10 N+11

N−8N−9N−1

ADC_in

ADCLK

D0 to D9

NN+1

N−9N−8N−1 NN−10

•When CDS_in input mode is used

•When ADC_in input mode is used

Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used

• The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes.

• Pipe-line delay is ten clock cycles when CDSIN is used and nine when ADCIN is used.

• In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.

Ce manuel convient aux modèles suivants

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