PSI DRS4 Manuel utilisateur

DRS4 Evaluation Board User’s Manual

Please check for possible updates of this manual under http://www.psi.ch/drs/documentation

DRS4 Evaluation Board

User’s Manual

Board Revision 5

as of January 2014

Last revised: April 27, 2016

Stefan Ritt

Paul Scherrer Institute

CH-5232 Villigen PSI

Switzerland

Email: [email protected]

Phone: +41 56 310 3728

DRS4 Evaluation Board User’s Manual

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Revision History

Date

Modification

2 March 09

Initial Revision

27 April 09

Mention input range, added timing calibration description

3 Aug. 09

Added LED description

12 July 10

Updated documentation for evaluation board V3

12 Sept. 10

Added maximum input voltage

16. Feb. 12

Added info for external connectors

5. Dec. 12

Changed LED description, added OSX part

11. Jan 13

Changed binary format for multi-board functionality

18. Dec. 13

Updated documentation for evaluation board V5

28. Feb. 14

Added note on clock distribution

6. Mar. 14

Added formulas for inter-channel time alignment

26. Sept. 14

Added range in binary format

DRS4 Evaluation Board User’s Manual

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Table of Contents

Revision History......................................................................................................................... 2!

Table of Contents ....................................................................................................................... 3!

1.!Introduction ......................................................................................................................... 4!

1.1.!Board description ......................................................................................................... 4!

1.2.!LEDs............................................................................................................................. 6!

1.3.!Firmware Description................................................................................................... 7!

2.!Installation........................................................................................................................... 9!

2.1.!Windows XP ................................................................................................................ 9!

2.2.!Windows 7.................................................................................................................. 12!

2.3.!Linux .......................................................................................................................... 14!

2.4.!Macintosh OSX .......................................................................................................... 16!

3.!Running the Board ............................................................................................................ 17!

3.1.!Command line Interface “drscl”................................................................................. 17!

3.2.!Oscilloscope application “DRSOsc”.......................................................................... 18!

3.3.!Multi-board configuration .......................................................................................... 26!

4.!Development Hints............................................................................................................ 27!

4.1.!Power Supply ............................................................................................................. 27!

4.2.!Analog Input............................................................................................................... 28!

4.3.!Control Voltages ........................................................................................................ 29!

4.4.!ADC Clock................................................................................................................. 29!

4.5.!Calibration.................................................................................................................. 29!

5.!DRS4 Evaluation Board V5 Schematics........................................................................... 30!

6.!DRS4 Evaluation Board V5 Bill of Materials................................................................... 37!

DRS4 Evaluation Board User’s Manual

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1. Introduction

The DRS4 chip, which has been designed at the Paul Scherrer Institute, Switzerland by Stefan

Ritt and Roberto Dinapoli is a Switched Capacitor Array (SCA) capable of digitizing eight

channels at sampling speeds up to 5 GSPS and 1024 sampling points. This chip is available

through the PSI technology transfer program for other institutes and organizations. In order to

simplify the design process to integrate the DRS4 chip into custom electronics, an evaluation

board has been designed, which demonstrates the basic operation of the chip. It has SMA

connectors for four input channels CH1 to CH4, an USB 2.0 connector and MMCX

connectors for triggering and clock synchronization (Figure 1). The board is powered through

the USB port and contains an on-board trigger logic. It comes with MS Windows®, Linux and

Mac OSX drivers and two application programs. It is basically equivalent to a four channel 5

GSPS digital oscilloscope.

This manual describes the software installation, the usage of the application programs, and

gives hints for developers seeking to build new electronics around the DRS4 chip.

1.1. Board description

Since the DRS4 chip has differential inputs, the board uses four active buffers (THS4508

from Texas Instruments ®) to convert the 50-Ohm terminated single ended inputs into

differential signals. Analog switches in front of the buffers (ADG901 form Analog Devices®)

are used to de-couple the inputs during calibration. Two reference voltages are generated by

the on-board 16-bit DAC to measure the offset and gain of all DRS4 storage cells for

calibration. The four analog inputs are AC coupled and have a input range of 1 V peak-to-

peak. The DRS4 is read out with a 14-bit ADC (AD9245 from Analog Devices®) and a FPGA

(Xilinx®Spartan 3). The USB connection is implemented with a micro controller (Cypress®

CY2C68013A). The high speed modus of the USB 2.0 bus allows for data transfer rates of

more than 20 MB/sec.

Figure 1: Picture of the DRS4 Evaluation Board V5 with different components

DRS4 Evaluation Board User’s Manual

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For trigger purposes and inter-board synchronization, four MCX connectors are available,

which can be seen on the right side of Figure 1. The Trigger IN works as an external trigger

much like the one of an oscilloscope. The electrical standard is 5V TTL. Although a 50 Ω

termination is possible, the resistor is not soldered by default. This allows using weaker

sources, which cannot drive 5V into a 50 Ωload. Reflections on this line usually do not

matter, since the first leading edge of the trigger is used. To connect a SMA cable to the

trigger input, a commercial adapter can be used like the one shown in.

Figure 2: MCX-SMA adapter which can be obtained for example form

www.digikey.com (part number ACX1348-ND)

The Trigger OUT signal sends a 150 ns wide pulse when ever the board triggers via the

internal hardware trigger. It does not output a trigger when the board is triggered via software

(for example in the “AUTO” trigger mode of the DRSOsc program). The signal standard is

5V TTL. When terminated with 50 Ω, the signal amplitude will only reach about 2V. As

written above, in most cases the termination should not be necessary.

The Clock IN/OUT signals will be supported in a future firmware version to allow a better

synchronization between different boards for multi-board DAQ systems.

Four on-board discriminators with programmable level allows for self triggering on any of the

four input channels, or a combination of channels supporting coincidences for example. A 1

MBit EEPROM (25LC1025 from Microchip®) is used to store the board serial number and

calibration information. Two 14-pin headers carry all important logical signals which allow

easy debugging with a logic analyzer or oscilloscope. A JTAG adapter can be used to update

the FPGA firmware through a Xilinx®Platform Cable Adapter.

The specifications of the board inputs is summarized in following table:

Analog inputs

Termination

Input range

Maximum allowed input voltage

Long pulse (<2µs)

Short pulse (<200ns)

50 Ω

1 V p-p

±10V

±20V

±30V

AC coupled

Trigger input/Clock input

Termination

Maximum allowed input voltage

High Level Input Voltage

high impedance,

optionally 50 Ω

-0.5 V to +5.5 V

2.5 V (min)

5 V TTL compatible

Trigger output/Clock output

Level

5V TTL

DRS4 Evaluation Board User’s Manual

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1.2. LEDs

The DRS4 evaluation board is equipped with three LEDs. They are operated by the micro

controller and the FPGA and have following meaning:

LED

Meaning

Blue

This LED becomes green when the on-board micro-controller booted

successfully. If this LED stays dark, there is either no power or the micro-

controller lost its program, which requires a re-programming of the EEPROM.

Green

When the on-board FPGA boots correctly this LED becomes lit. If it stays dark,

it might be that the FPGA program was lost and requires re-programming. After

booting, this LED indicates the board status. If lit, the DRS4 chip is active and

sampling data. If stopped by software or a trigger, this LED turns off. A special

pulse stretcher ensures that even in high trigger rate environments this LED

does not flash with more than ~10Hz so the blinking can still be seen by eye.

Yellow

When lit, this LED indicates a error condition

DRS4 Evaluation Board User’s Manual

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1.3. Firmware Description

Both the Windows and the Linux distribution contain a subdirectory “firmware” which

contains the FPGA and Microcontroller firmware for the DRS4 Evaluation Board. The FPGA

firmware is written in pure VHDL, thus making it easy to port it to other FPGA devices such

as Altera®or Lattice®. Only a few Xilinx®basic components such as clock managers and I/O

blocks have been instantiated and must be adapted when another FPGA manufacturer than

Xilinx®is chosen. The FPGA source code is contained in several files with following

contents:

src/drs4_eval1.vhd

Top level entity. Routing of clock signals, global reset signal,

LEDs and LEMO input

src/drs4_eval1_app.vhd

Main file containing state machines for DRS4 readout, serial

interface to DAC, EEPROM and temperature sensor, trigger

logic and reference clock generation

src/usb_dpram.vhd

Instantiates block ram for waveform storage

src/usb_racc.vhd

Interface to CY2C68013A microcontroller in slave FIFO mode.

Implements a set of status and control registers through which

the main application can be controlled

src/usr_clocks.vhd

Generates 66 MHz, 132 MHz, 264 MHz and a phase shifted 66

MHz clock out of the 33 MHz quartz input frequency via the

Xilinx®Digital Clock Managers (DCM)

ucf/drs4_eval1.ucf

Constraint file. Assigns package pins and defines clock

constraints

3s400/drs4_eval1.ise

Xilinx®ISE 9.2i project file

3s400/drs4_eval1.bit

Compiled firmware image directly for Spartan 3s400 FPGA

3s400/drs4_eval1.mcs

Compiled firmware image for FPGA EEPROM XCF02S

3s400/drs4_eval1.ipf

Xilinx®Impact project file to program FPGA via download

cable

The firmware for the USB microcontroller from Cypress®is written in C and must be

compiled with the Keil®8051 C compiler. It contains the standard include and library files

from the Cypress EZ-USB®development kit plus some DRS specific files:

CY7C68013A/drs_eval.c

Main micro controller firmware file

CY7C68013A/dscr.a51

USB descriptor tables

CY7C68013A/drs_eval.hex

Compiled firmware file (Intel HEX format)

CY7C68013A/drs_eval1.iic

Compiled firmware file (For Cypress EZ-USB Console

download)

CY7C68014A/*

Remaining files are standard files from EZ-USB development

kit

DRS4 Evaluation Board User’s Manual

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The FPGA firmware implements a set of control and status registers, through which the DRS4

can be controlled and read out. The mapping of the control registers is as follows:

Ofs.

Bit

Name

Comment

0x00

start_trig

Write a "1" to start the domino wave

0x00

reinit_trig

Write a "1" to stop & reset the DRS chip

0x00

soft_trig

Write a "1" to stop the DRS chip & read the data to RAM

0x00

eeprom_write_trig

Write contents of RAM into EEPROM (32kB page)

0x00

eeprom_read_trig

Read contents of EEPROM into RAM (32kB page)

0x02

led

1=on, 0=blinks once at beginning of DRS chip readout

0x02

tcal_en

Switch on (1) / off (0) 100 MHz calib. sig. for DRS chips

0x02

transp_mode

1=send DRS inputs to outputs ("transparent mode")

0x02

enable_trigger1

Write a "1" to enable external trigger (LEMO)

0x02

readout_mode

0:start from first bin, 1:start from domino stop

0x02

neg_trigger

1=trigger on high to low transition

0x02

acalib

Write "1" to enable amplitude calibration

0x02

refclk_source

0: FPGA, 1: external MCX CLKIN reference clock

0x02

dactive

0:stop domino wave during readout, 1:keep it running

0x02

standby

1: put chip in standby mode

0x04

31..16

DAC0

Set DAC 0 (=A, ROFS)

0x06

15..0

DAC1

Set DAC 1 (=B, CMOFS)

0x08

31..16

DAC2

Set DAC 2 (=C, CAL-)

0x0A

15..0

DAC3

Set DAC 3 (=D, CAL+)

0x0C

31..16

DAC4

Set DAC 4 (=E, BIAS)

0x0E

15..0

DAC5

Set DAC 5 (=F, TLEVEL)

0x10

31..16

DAC6

Set DAC 6 (=G, O-OFS)

0x12

15..0

DAC7

Set DAC 7 (=H, -)

0x14

31..24

configuration

Bit0: DMODE, Bit1: PLLEN, Bit2: WSRLOOP

0x14

23..16

channel_config

1=1x8k,0x11=2x4k,0x33=4x2k,0xFF=8x1k

0x16

15..8

adcclk_phase

ADC clock phase

0x16

7..0

0x18

31..16

trigger_delay

Trigger delay in ticks of roughly 2.3 ns

0x1A

15..0

sampling_freq

Sampling frequency in ticks (=1024/fsamp*0.120-2)

0x1E

31..16

trigger_config

Trigger configuration

0x1E

15..0

eeprom_page

Page number for EEPROM communication

While the mapping of the status registers is like this:

Ofs.

Bits

Name

Comment

0x00

31..16

board_magic

0xC0DE, Magic number for DRS board identification

0x02

15..8

board_type

7: Eval. Board V3, 8: Eval. Board V4, 9: Eval Board V5

0x02

7..0

drs_type

4 for DRS4

0x04

running

"1" while domino wave running or readout in progress

0x08

31..16

stop_cell

position of cell where sampling stopped at last trigger

0x20

31..16

temperature

temperature in 0.0625 deg. C units

0x24

31..16

serial_cmc

Board serial number

0x26

15..0

version_fw

firmware version (SVN revision)

0x28

31..16

scaler_1hi

Scaler for input #1

0x2A

15..0

scaler_1lo

0x2C

31..16

scaler_2hi

Scaler for input #2

DRS4 Evaluation Board User’s Manual

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0x2E

15..0

scaler_2lo

0x30

31..16

scaler_1hi

Scaler for input #3

0x32

15..0

scaler_1lo

0x34

31..16

scaler_1hi

Scaler for input #4

0x36

15..0

scaler_1lo

0x38

31..16

scaler_1hi

Scaler for trigger

0x3a

15..0

scaler_1lo

All registers are implemented as 32-bit registers, so they can be mapped easily into some

VME address space for example if one decides to build a VME board containing the DRS4.

2. Installation

2.1. Windows XP

Under MS Windows®it is important to install the necessary driver before connection the

DRS4 Evaluation Board with the PC. The current distribution can be downloaded from

http://www.psi.ch/drs/download . The Windows version contains a single program drs-

xx.exe (where xx is the version) which can be executed to install the driver, applications,

documentation and source code. Executing this file starts the installer:

You can select which components to be installed:

DRS4 Evaluation Board User’s Manual

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Then you can select the installation directory:

After the installer has finished, you can connect the DRS4 Evaluation Board to the Computer:

Now you will see the “Found New Hardware” dialog:

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