PLX Technology PEX 8614AA Guide rapide de l'utilisateur

PEX 8614AA Base Board RDK

Hardware Reference Manual

Version 1.0

October 2008

Website: www.plxtech.com

Technical Support: www.plxtech.com/support

October 16, 2008

PEX 8614AA Base Board RDK Hardware Reference Manual – Version 1.0

PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor

variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or

PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.

Other brands and names are the property of their respective owners.

Document Number: PEX8614AA-Base Board RDK-HRM-1.0

October 16, 2008

PEX 8614AA Base Board RDK Hardware Reference Manual – Version 1.0

PREFACE

NOTICE

This document contains PLX Confidential and Proprietary information. The contents of this document may not be

copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.

PLX provides the information and data included in this document for your benefit, but it is not possible to entirely

verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured

products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this

information. The information in this document is subject to change without notice. Although every effort has been

made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential

damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes

no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which

may arise through the use of the RDK, or for any damage or loss caused by deletion of data as a result of

malfunction or repair.

ABOUT THIS MANUAL

This document describes the PLX PEX 8614AA-Base Board RDK, a Rapid Development Kit, from a hardware

perspective. It contains a description of all major functional circuit blocks on the board and also is a reference for

the creation of software for this product. This manual also includes complete schematics and bill of materials.

REVISION HISTORY

Date Version Comments

October

2008 1.0 Initial Release

PEX 8614AA Base Board RDK Hardware Reference Manual – Version 1.0

CONTENTS

1. General Information...........................................................................................................................................1

1.1 PEX 8614 Features.................................................................................................................................. 1

1.2 PEX 8614AA-BB RDK Features .............................................................................................................. 3

2. System Architecture...........................................................................................................................................4

3. Hardware Architecture.......................................................................................................................................4

3.1 PEX 8614................................................................................................................................................. 4

3.2 PCI Express Interfaces ............................................................................................................................ 5

3.2.1 RDK Configuration Modules and Their Receptacles........................................................................... 5

3.2.2 PCI Express Lane 0 to Lane 3............................................................................................................. 5

3.2.3 PCI Express Lane 4 to Lane 7............................................................................................................. 6

3.2.4 PCI Express Lane 8 to Lane 11........................................................................................................... 7

3.3 Reference Clock Circuits.......................................................................................................................... 8

3.4 Reset Circuits........................................................................................................................................... 8

3.5 Serial Hot-Plug (SHP) Controller Circuits................................................................................................. 9

3.6 Serial EEPROM...................................................................................................................................... 10

3.7 I2C Interface............................................................................................................................................ 10

3.8 Power Distribution Circuits..................................................................................................................... 11

3.9 FPGA Interface....................................................................................................................................... 12

3.10 LED and 7-Segment Displays................................................................................................................ 13

3.10.1 LED Indicators............................................................................................................................... 13

3.10.2 7-Segment Displays ...................................................................................................................... 14

3.11 GPIO Pins .............................................................................................................................................. 15

3.12 Reserved Pins........................................................................................................................................ 15

4. On-Board Connectors, Switches, and Jumpers...............................................................................................16

4.1 DIP Switches.......................................................................................................................................... 16

4.1.1 Dip Switch Group 1............................................................................................................................ 16

4.1.2 Dip Switch Group 2............................................................................................................................ 17

4.1.3 Dip Switch Group 3............................................................................................................................ 19

4.2 Push-Button Switches............................................................................................................................ 20

4.2.1 Manual Reset# (S1)........................................................................................................................... 20

4.2.2 FPGA Manual Reset# (S2)................................................................................................................ 20

4.2.3 Serial Hot-Plug Controller Attention Button (S3) ............................................................................... 21

4.3 Connectors and Headers ....................................................................................................................... 21

4.3.1 ATX Peripheral Power Connectors (J1-J4 & J7-J8) .......................................................................... 21

4.3.2 x4 PCI Express External Cable Connectors (J5 & J6) ...................................................................... 21

4.3.3 ATX Main Power Connector (J9)....................................................................................................... 22

4.3.4 ATX +12V Power Connector(J10) ..................................................................................................... 22

4.3.5 Xilinx JTAG Connector (J12) ............................................................................................................. 22

4.3.6 Xilinx Mode Setting Header (J13)...................................................................................................... 23

4.3.7 PEX 8614 JTAG Header (JP3).......................................................................................................... 23

4.3.8 SMBus Header (JP5)......................................................................................................................... 23

4.3.9 PCI Express x8 Midbus Probe Footprint (JP6).................................................................................. 23

4.3.10 PEX 8614 I2C Port (JP8) ............................................................................................................... 24

4.3.11 Debug Signal Header (JP9 & JP11).............................................................................................. 24

4.3.12 Debug Input Header (JP10)........................................................................................................... 26

4.3.13 Reference Clock Header (JP100) ................................................................................................. 26

5. RDK Port Configurations..................................................................................................................................27

6. Bill of Materials/ Schematics............................................................................................................................30

PEX 8614AA Base Board RDK Hardware Reference Manual – Version 1.0

FIGURES

Figure 1. PEX 8614AA Base Board RDK Front View................................................................................................ 2

Figure 2. Connecting The RDK to a PC with x1 or x4 link......................................................................................... 4

Figure 3. Lanes 0-3 Hardware Connections on the RDK.......................................................................................... 6

Figure 4. Lanes 4-7 Hardware Connections on the RDK.......................................................................................... 7

Figure 5. Lanes 8-11 Hardware Connections on the RDK........................................................................................ 7

Figure 6. RDK Reference Clock Circuits................................................................................................................... 8

Figure 7. RDK Reset Circuits .................................................................................................................................... 9

Figure 8. SERIAL HOT-PLUG Circuits.................................................................................................................... 10

Figure 9. RDK ATX Power Connectors................................................................................................................... 11

Figure 10. RDK Power Distribution Circuits ............................................................................................................ 12

Figure 11. FPGA Interface on RDK......................................................................................................................... 13

Figure 12. RDK Dip Switch Groups......................................................................................................................... 16

Figure 13. Group1 of Switches................................................................................................................................ 16

Figure 14. Group 2 of Dipswitches.......................................................................................................................... 17

Figure 15. Group 3 of Dip Switches......................................................................................................................... 19

Figure 16. x1 upstream and 11x1 downstream (PCFG=0000) ............................................................................... 27

Figure 17. x4 upstream 8x1 downstream (PCFG=0001) ........................................................................................ 28

Figure 18. x4 upstream, 1x4 and 4x1 downstream (PCFG=0010).......................................................................... 29

TABLES

Table 1. Port Configurations Supported by the RDK................................................................................................. 5

Table 2. RDK LED Indicator descriptions................................................................................................................ 13

Table 3. RDK 7-Segment Display Functions........................................................................................................... 14

Table 4. Strap_Reserved Pin Connections ............................................................................................................. 15

Table 5. Functional Description of Group 1 Dip Switches....................................................................................... 16

Table 6. Functional Description of Group 2 Dip Switches....................................................................................... 18

Table 7. Port Configurations use Dipswitch SW2.................................................................................................... 19

Table 8. Functional Descriptions of SW3, SW6, SW13-SW14 ............................................................................... 20

Table 9. Signal Names of J1-J4 & J7-J8................................................................................................................. 21

Table 10. Signal Names of J5 and J6...................................................................................................................... 21

Table 11. Signal Names of J9 ................................................................................................................................. 22

Table 12. Signal Names of J10 ............................................................................................................................... 22

Table 13. Signal Names of J12 ............................................................................................................................... 22

Table 14. Signal Names of J13 ............................................................................................................................... 23

Table 15. Pin assignment of JP3............................................................................................................................. 23

Table 16. Signal Names of JP5............................................................................................................................... 23

Table 17. Signal Names of JP6............................................................................................................................... 23

Table 18. Pin assignment of JP8............................................................................................................................. 24

Table 19. Pin assignment of JP9 & JP11................................................................................................................ 24

Table 20. Pin assignment of JP10........................................................................................................................... 26

Table 21. Pin assignment of JP100......................................................................................................................... 26

PEX 8614AA Base Board RDK Hardware Reference Manual – Version 1.0

1. General Information

The PLX PEX 8614AA Base Board RDK is a Rapid Development Kit based on the PEX 8614, a 12-lane, 12-port

PCI Express switch based in the PCI Express Specification rev 2.0 with SerDes capable of running at 5 GT/s. The

PEX 8614AA Base Board RDK provides a complete hardware and software development platform that facilitates

getting designs up and running quickly, lowering risk and reducing time-to-market. This RDK consists a base

board containing three hardware configuration Modules, a PCI Express cable adapter board that plugs into the

host system, and up to two x4 PCI Express cables that used to connect the RDK to the cable adapter. This

manual primarily focuses on the PEX 8614AA Base Board RDK, and its use with other parts to demonstrate the

various functions of PEX 8614 chip. Figure 1 provides a top view (component side) of the PEX 8614AA Base

Board RDK.

1.1 PEX 8614 Features

•12-lane, 12-port PCI Express Gen 2 switch with integrated on-chip SerDes

•120 GT/s aggregate bandwidth (5.0GT/s/Lane x 16 Lanes x 2 (full duplex))

•19mm2324-ball Plastic Ball Grid Array (PBGA) package

•Typical Power – 1.7W

•Cut-Thru packet latency of less than 160ns

•Low power SerDes (under 90mW per lane)

•Fully non-blocking switch architecture

•Flexible port configuration

o12 flexible and configurable ports (x1, or x4 ), x2 is also supported

•Flexible device configuration

oConfigurable via serial EEPROM, I2C, hardware strapping, or by the host

•Maximum packet payload size of 2,048 bytes

•Designate any Port as the Upstream Port (Port 0 is recommended)

•Dynamic Buffer Pool Architecture

•Read Pacing (allows user to throttle Read requests from Downstream Ports to allow for more efficient

performance)

•Dual-Cast (enhances performance by sending date from one ingress port to two egress ports)

•Dynamic speed (2.5 GT/s or 5.0 GT/s) negotiation

•Dynamic link-width negotiation (automatically negotiates down to optimal link-width based on traffic

density)

•Lane and polarity reversal

•Non-Transparent Bridging support

oEnables Dual-Host, Host-Failover applications

•Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready, and L3 (with

Vaux not supported)

•Conventional PCI-compatible Device Power Management states – D0 and D3hot

•Active State Power Management

•Spread-Spectrum Clock Isolation

oDual-clock Domain

•Quality of Service (QoS)

oTwo Virtual Channels (VC0 and VC1) and Eight Traffic classes (TC)

oWeighted Round-Robin Port and Virtual Channel arbitration

•Reliability, Availability, Serviceability (RAS) features

oAll ports are Hot-Plug capable through I2C (Serial Hot-Plug Controller on every port)

oAdvanced Error Reporting capability

oPerformance Monitoring

Per-Port Payload and Header Counters

Per-traffic type (write, Read, Completion) Counters

oJTAG AC/DC boundary scan

o12 Lane status balls (PEX_LANE_GOOD[11:0]#)

o32 GPIO balls (GPIO[31:0]

PEX 8614AA Base Board RDK Hardware Reference Manual – Version 1.0

Figure 1. PEX 8614AA Base Board RDK Front View

PEX 8614AA Base Board RDK Hardware Reference Manual – Version 1.0

•INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) ball

support

•Compliant to the following specifications:

oPCI Local Bus Specification, Revision 3.0 (PCI r3.0)

oPCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2)

oPCI to PCI Bridge Architecture Specification, Revision 1.2 (PCI-to-PCI Bridge r1.2)

oPCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1)

oPCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0)

oIEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture,

1990 (IEEE Standard 1149.1-1990)

oIEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture

oIEEE Standard 1149.1-1994, Specifications for Vendor-Specific Extensions

oIEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture

Extensions (IEEE Standard 1149.6-2003)

oThe I2C-Bus Specification, Version 2.1 (I2C Bus v2.1)

1.2 PEX 8614AA-BB RDK Features

•PLX PEX 8614 PCI Express switch in a 324-ball Plastic BGA package

•Based on PCI Express Card Electromechanical (CEM) Specification 2.0 and PCI Express External

Cabling Specification 1.0

•Supports up to 3 different port configurations with 4x PCI Express cable connection(s) to the upstream

•Non-Transparent Bridging support

•One x8 Gen 2 Midbus probe footprint for upper 4 lanes of PCI Express signal probing for the chip

•PCI Express RefClk Circuits supports Spread-Spectrum Clock Isolation

•Serial Hot-Plug circuits on one PCI Express card edge connector

•In system programmable Serial EEPROM (2.5V)

•A standard 2x2 header provides the I2C interface to an I2C master

•DIP switches for port configuration, upstream port or NT port select and I2C address settings

•Manual push-button PERST# capability

•Up to sixteen dual color LEDs for visual inspection of link speed and status

•7-Segment displays for port numbers and link width

•Up to 3-digit display for junction temperature of PEX 8614

•Voltage level monitoring circuit for 1.0V and 2.5V power to the PEX 8614

PEX 8614AA Base Board RDK Hardware Reference Manual – Version 1.0

2. System Architecture

The PEX 8614AA-Base Board RDK is a 21” x 10” bench top board for silicon evaluation and design reference for

the PEX 8614 PCI Express Gen 2 switch. This RDK consists of three main hardware components: the base

board, the PCI Express External Cable Adapter and PCI Express Cable assembly. Figure 1 represents the

placement of major component blocks on the RDK base board. Figure 2 and Figure 3 provide diagrams of the

RDK being used in a PC. The RDK provides up to 11 PCI Express slots for add-in cards and visual indicators for

port, link status and speed information. The RDK is designed to be powered up with an ATX power supply.

Figure 2. Connecting The RDK to a PC with x1 or x4 link

3. Hardware Architecture

The PEX 8614AA Base Board RDK is designed around the PEX 8614, a 12-port, 12-lane Gen 2 switch, and

based on the PCI Express CEM 2.0 Specification. The RDK offers PCI Express interfaces to 11 PCI Express

Edge Card Connectors, two x4 PCI Express External cable connectors, and three configuration modules. The

RDK is designed to support 3 different port configurations (see Table 1 for details) and to connect to its upstream

PC through its PCI Express Cable Connectors. The RDK relies on the PC connected to its PCI Express Cable

Connector J5 to obtain it primary PCI Express reference clock and reset to support the RDK normal functions.

Also, the RDK provides visual indications for power, link speed, port status, port number, and link width.

3.1 PEX 8614

The PEX 8614 is a 12-lane, 12-port PCI Express Gen 2 (5.0GT/s) switch. It is in 19mmx19mm package. It

supports 4 different types of port configurations with any port can be upstream or NT port. It supports Spread-

Spectrum Clocking Isolation function. It also provides 12 lane status drivers and 32 GPIOs.

PEX 8614AA Base Board RDK Hardware Reference Manual – Version 1.0

3.2 PCI Express Interfaces

The RDK provides 11 PCI Express connectors and one x4 PCI Express External Cable Connectors for PCI

Express connections of PEX 8614. The RDK supports 3 different port configurations of PEX 8614. With the

correct port configuration STRAP pin settings and the right Configuration Modules are installed, the RDK can

demonstrate up to 12 ports and a up to x4 link upstream connection PCI Express Gen 2 switch. Table 1 shows all

port configurations supported by the RDK while sections 3.2.1 to 3.2.5 describe the Configuration Modules and

hardware configurations of grouped of each four PCI Express lanes in details.

Table 1. Port Configurations Supported by the RDK

Strap pin Settings

STRAP_PORTCFG[3:0] Port Configurations Configuration Modules Used*

0000 x1x1x1x1x1x1x1x1x1x1x1x1 0108 at U74;0108 at U75; and 0108 at U76

0001 x4x1x1x1x1x1x1x1x1 0107 at U74;0108 at U75; and 0108 at U76

0010 x4x4x1x1x1x1 0107 at U74;0108 at U75; and 0107 at U76

Note: * Three Configuration Modules may use for the RDK. They are “configuration Module 0107-0109”; U74, U75

and U76 are receptacles on the RDK for Configuration Modules to be installed

3.2.1 RDK Configuration Modules and Their Receptacles

Each Configuration Module is a plug of a 200-pin board-to-board Mezzanine Connector assembled on a PCB. For

the RDK, it is used to connect x4 link of PCI Express signals from PEX 8614 to one particular hardware

connections. Only three Configuration Modules may be used on the PEX 8614AA base board RDK. These

modules are labeled on their PCB silk screen as:

•Configuration Module 0107

•Configuration Module 0108

•Configuration Module 0109

On the RDK side, three receptacles of same Mezzanine Connectors are placed at U74, U75 and U76 where the

Configuration Modules can be manually plugged in to complete the RDK PCI Express hardware configurations.

3.2.2 PCI Express Lane 0 to Lane 3

PCI Express lanes 0 - 3 of PEX 8614 are routed to the receptacle U74 as shown in Figure 4. When Configuration

Module 0108 is plugged into U74 at Case (a), lanes 0-3 will be separately connected with a single line going to

the following: PCI Express cable connector J5, PCI Express SLOT 1, PCI Express SLOT 2 and PCI Express

SLOT 3. This results in x1 links to form port 0, 4, 6, and 8. When Configuration Module 0107 is plugged into U74

at Case (b), all four lanes will be connected to x4 PCI Express cable connector J5 to form a x4 link at port 0. Note

that the PCIe signals to PCIe Cable Connector J5 can be an independent x4 port or the lower lanes of a x8 port.

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