Phytec PhyCORE-i.MX 6 Manuel utilisateur

A product of a PHYTEC Technology Holding company

phyCORE®-i.MX 6

Hardware Manual

Document No.: L-808e_2

SOM Prod. No.: PCM-058

SOM PCB. No.: 1429.3

Edition: August 2016

phyCORE®-i.MX 6 [PCM-058]

©PHYTEC Messtechnik GmbH 2016 L-808e_2

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and copyright (©) symbols does not imply that a product is not protected. Additionally, registered

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The information in this document has been carefully checked and is considered to be entirely reliable.

However, PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies. PHYTEC Messtechnik

GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages

resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the

right to alter the information contained herein without prior notification and accepts no responsibility for

any damages that might result.

Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising

from the improper usage or improper installation of the hardware or software. PHYTEC Messtechnik GmbH

further reserves the right to alter the layout and/or design of the hardware without prior notification and

accepts no liability for doing so.

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Address: PHYTEC Messtechnik GmbH

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Information:

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Support:

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Web Site: http://www.phytec.in http://www.phytec.cn

2nd Edition August 2016

Contents

©PHYTEC Messtechnik GmbH 2016 L-808e_2 i

List of Figures........................................................................................................... iii

List of Tables ............................................................................................................ iv

Conventions, Abbreviations and Acronyms ..................................................................... v

Preface .................................................................................................................. viii

1Introduction ...................................................................................................... 1

1.1 Features of the phyCORE-i.MX 6 ....................................................................... 1

1.2 Block Diagram.............................................................................................. 3

1.3 phyCORE-i.MX 6 Component Placement ............................................................. 4

1.4 Minimum Requirements to operate the phyCORE-i.MX 6 ........................................ 6

2Pin Description................................................................................................... 7

3Jumpers .......................................................................................................... 18

4Power.............................................................................................................. 22

4.1 Primary System Power (VDD_3V3) ...................................................................22

4.2 Power Management IC (PMIC) (U16) ................................................................22

4.2.1 Power Domains.................................................................................23

4.3 Supply Voltage for external Logic ....................................................................25

4.4 Backup Power (PMIC_VBAT/VDD_MX6_SNVS) ....................................................25

5Reset............................................................................................................... 26

6System Configuration and Booting....................................................................... 27

6.1 Boot Mode Selection ....................................................................................27

6.2 Boot Device Selection and Configuration ..........................................................28

7System Memory................................................................................................. 30

7.1 DDR3-SDRAM (U4-U7) ..................................................................................30

7.2 NAND Flash Memory (U12).............................................................................31

7.3 eMMC Flash Memory (U14).............................................................................31

7.4 I²C EEPROM (U11) ........................................................................................31

7.4.1 EEPROM Write Protection Control (J4)...................................................32

7.5 SPI Flash Memory (U9) )................................................................................32

8SD / MM Card Interfaces ..................................................................................... 33

9Serial Interfaces ............................................................................................... 34

9.1 Universal Asynchronous Interface ...................................................................34

9.2 USB OTG Interface........................................................................................35

9.3 USB Host Interface.......................................................................................35

9.4 Ethernet Interface .......................................................................................36

9.4.1 Ethernet PHY (U2).............................................................................36

9.4.2 Software Reset of the Ethernet Controller ..............................................37

9.4.3 MAC Address ....................................................................................37

9.4.4 RMII Interface..................................................................................38

9.5 SPI Interface...............................................................................................39

9.6 I2C Interface ...............................................................................................40

9.7 I2S Audio Interface (SSI))..............................................................................40

9.8 CAN Interface..............................................................................................41

9.9 SATA Interface ............................................................................................41

9.10 PCI Express Interface ....................................................................................42

phyCORE®-i.MX 6 [PCM-058]

ii ©PHYTEC Messtechnik GmbH 2016 L-808e_2

10 General Purpose I/Os ......................................................................................... 43

11 User LED .......................................................................................................... 44

12 Debug Interface ................................................................................................ 45

13 Display Interfaces ............................................................................................. 46

13.1 Parallel Display Interface.............................................................................. 46

13.2 LVDS Display Interface ................................................................................. 47

13.3 Supplementary Signals................................................................................. 47

High-Definition MultimediaInterface

(HDMI)......................................................... 48

15 Camera Interfaces ............................................................................................. 49

15.1 Parallel 0 Camera Interface (CSI0 of IPU#1)...................................................... 51

15.2 Parallel 1 Camera Interface (CSI1 of IPU#2)...................................................... 52

15.3 MIPI/CSI-2 Camera Interface......................................................................... 53

15.4 Utilizing the Camera Interfaces on a Carrier Board ............................................. 54

16 Tamper Detection .............................................................................................. 55

17 Technical Specifications ..................................................................................... 56

17.1 Product Temperature Grades ......................................................................... 58

17.2 Connectors on the phyCORE-i.MX 6: ................................................................ 59

18 Hints for Integrating and Handling the phyCORE-i.MX 6.......................................... 60

18.1 Integrating the phyCORE-i.MX 6..................................................................... 60

18.2 Handling the phyCORE-i.MX 6 ........................................................................ 62

19 Revision History................................................................................................ 63

Index...................................................................................................................... 65

Contents

©PHYTEC Messtechnik GmbH 2016 L-808e_2 iii

List of Figures

Figure 1: Block Diagram of the phyCORE-i.MX 6.............................................................. 3

Figure 2: phyCORE-i.MX 6 Component Placement (top view) ............................................. 4

Figure 3: phyCORE-i.MX 6 Component Placement (bottom view)........................................ 5

Figure 4: Pinout of the phyCORE-Connector (top view) .................................................... 8

Figure 5: Typical Jumper Pad Numbering Scheme ..........................................................18

Figure 6: Jumper Locations (top view) ........................................................................19

Figure 7: Jumper Locations (bottom view)...................................................................20

Figure 8: Powering Scheme of the phyCORE- i.MX 6........................................................24

Figure 9: User LED Location (top view)........................................................................44

Figure 10: Camera Connectivity of the i.MX 6 (Solo/DualLite)............................................49

Figure 11: Camera Connectivity of the i.MX 6 (Dual Core/Quad Core)...................................49

Figure 12: Camera Interfaces at the phyCORE-Connector (Parallel 0(CSI0 of IPU#1),

Parallel 1(CSI1 of IPU#2), and MIPI/CSI-2) .....................................................50

Figure 13: Use of Parallel 0 (CSI0 of IPU#1) and Parallel 1 (CSI1 of IPU#2) as

phyCAM-P interface ....................................................................................54

Figure 14: Use of Parallel 0 (CSI0 of IPU#1) and Parallel 1 (CSI1 of IPU#2) as

phyCAM-S+ interface ..................................................................................54

Figure 15: Physical Dimensions (top view).....................................................................56

Figure 16: Footprint of the phyCORE-i.MX 6 ...................................................................61

phyCORE®-i.MX 6 [PCM-058]

iv ©PHYTEC Messtechnik GmbH 2016 L-808e_2

List of Tables

Table 1: Signal Types used in this Manual ................................................................... vi

Table 2: Abbreviations and Acronyms used in this Manual..............................................vii

Table 3: Pinout of the phyCORE-Connector X1, Row A ................................................... 10

Table 4: Pinout of the phyCORE-Connector X1, Row B................................................... 12

Table 5: Pinout of the phyCORE-Connector X1, Row C ................................................... 14

Table 6: Pinout of the phyCORE-Connector X1, Row D................................................... 16

Table 7: Jumper Settings ....................................................................................... 21

Table 8: Boot Modes of the phyCORE-i.MX 6 ............................................................... 27

Table 9: Boot Configuration Pins at the phyCORE-Connector.......................................... 29

Table 10: EEPROM write protection states via J4 ........................................................... 32

Table 11: Location of the SD / MM Card Interface Signals................................................ 33

Table 12: Location of the UART Signals ....................................................................... 34

Table 13: Location of the USB OTG Signals................................................................... 35

Table 14: Location of the USB Host Signals.................................................................. 35

Table 15: Location of the Ethernet Signals .................................................................. 36

Table 16: Location of the RMII Interface Signals........................................................... 38

Table 17: SPI Interface Signal Location....................................................................... 39

Table 18: I2C Interface Signal Location ....................................................................... 40

Table 19: I2S Interface Signal Location ....................................................................... 40

Table 20: CAN Interface Signal Location...................................................................... 41

Table 21: SATA Interface Signal Location .................................................................... 41

Table 22: PCIe Interface Signal Location ..................................................................... 42

Table 23: Location of GPIO Pins................................................................................. 43

Table 24: Debug Interface Signal Location at phyCORE-Connector X1................................ 45

Table 25: Parallel Display Interface Signal Location....................................................... 46

Table 26: LVDS Display Interface Signal Location.......................................................... 47

Table 27: Supplementary Signals to support the Display Connectivity ............................... 47

Table 28: HDMI Interface Signal Location.................................................................... 48

Table 29: Camera Interface Parallel 0 (IPU1_CSI0) Signal Location................................... 51

Table 30: Camera Interface Parallel 1 (IPU2_CSI1) Signal Location................................... 52

Table 31: Camera Interface MIPI/CSI-2 Signal Location.................................................. 53

Table 32: Technical Specifications ............................................................................. 57

Table 33: Product Temperature Grades........................................................................ 58

Conventions, Abbreviations and Acronyms

©PHYTEC Messtechnik GmbH 2016 L-808e_2 v

Conventions, Abbreviations and Acronyms

This hardware manual describes the PCM-058 System on Module in the following referred

to as phyCORE®-i.MX 6. The manual specifies the phyCORE®-i.MX 6's design and function.

Precise specifications for the NXP® Semiconductor i.MX 6 microcontrollers can be found in

the enclosed microcontroller Data Sheet/User's Manual.

Note: We refrain from providing detailed part specific information within this manual,

which can be subject to continuous changes, due to part maintenance for our products.

Please read the paragraph "Product Change Management and information in this

manual on parts populated on the SOM" within the Preface.

Note: The BSP delivered with the phyCORE®-i.MX 6 usually includes drivers and/or software

for controlling all components such as interfaces, memory, etc. Therefore programming

close to hardware at register level is not necessary in most cases. For this reason, this

manual contains no detailed description of the controller's registers, or information

relevant for software development. Please refer to the i.MX 6 Reference Manual, if such

information is needed to connect customer designed applications.

Conventions

The conventions used in this manual are as follows:

Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or

that have a dash on top of the signal name (e.g.: RD) are designated as active low

signals. That is, their active state is when they are driven low, or are driving low.

A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or

high-level signal.

The hex-numbers given for addresses of I2C devices always represent the 7 MSB of the

address byte. The correct value of the LSB which depends on the desired command

(read (1), or write (0)) must be added to get the complete address byte. E.g. given

address in this manual 0x41 => complete address byte = 0x83 to read from the device

and 0x82 to write to the device

Tables which describe jumper settings show the default position in bold, blue text.

Text in blue italic indicates a hyperlink within, or external to the document. Click these

links to quickly jump to the applicable URL, part, chapter, table, or figure.

References made to the phyCORE-Connector always refer to the high density Samtec

connector on the undersides of the phyCORE-i.MX 6 System on Module.

phyCORE®-i.MX 6 [PCM-058]

vi ©PHYTEC Messtechnik GmbH 2016 L-808e_2

Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table

lists the abbreviations used to specify the type of a signal.

Signal Type Description Abbr.

Power Supply voltage input PWR_I

Ref-Voltage Reference voltage output REF_O

Input Digital input I

Output Digital output O

IO Bidirectional input/output I/O

OC-Bidir PU Open collector input/output with pull up OC-BI

OC-Output Open collector output without pull up, requires an external

pull up

5V Input PD 5 V tolerant input with pull down 5V_PD

LVDS Input Differential line pairs 100 Ohm LVDS level input LVDS_I

LVDS Output Differential line pairs 100 Ohm LVDS level output LVDS_O

TMDS Output Differential line pairs 100 Ohm TMDS level output TMDS_O

USB IO Differential line pairs 90 Ohm USB level bidirectional

input/output

USB_I/O

ETHERNET

Input

Differential line pairs 100 Ohm Ethernet level input ETH_I

ETHERNET

Output

Differential line pairs 100 Ohm Ethernet level output ETH_O

ETHERNET IO Differential line pairs 100 Ohm Ethernet level bidirectional

input/output

ETH_I/O

PCIe Input Differential line pairs 100 Ohm PCIe level input PCIe_I

PCIe Output Differential line pairs 100 Ohm PCIe level output PCIe_O

MIPI CSI-2

Input

Differential line pairs 100 Ohm MIPI CSI-2 level input CSI-2_I

Table 1: Signal Types used in this Manual

Conventions, Abbreviations and Acronyms

©PHYTEC Messtechnik GmbH 2016 L-808e_2 vii

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the table below to

navigate unfamiliar terms used in this document.

Abbreviation Definition

BSP Board Support Package (Software delivered with the Development Kit

including an operating system (Windows, or Linux) preinstalled on the

module and Development Tools).

CB Carrier Board; used in reference to the phyCORE Development Kit Carrier

Board.

DFF D flip-flop.

EMB External memory bus.

EMI Electromagnetic Interference.

GPI General purpose input.

GPIO General purpose input and output.

GPO General purpose output.

IRAM Internal RAM; the internal static RAM on the NXP® Semiconductor i.MX 6

microcontroller.

J Solder jumper; these types of jumpers require solder equipment to

remove and place.

JP Solderless jumper; these types of jumpers can be removed and placed by

hand with no special tools.

PCB Printed circuit board.

PDI PHYTEC Display Interface; defined to connect PHYTEC display adapter

boards, or custom adapters

PEB PHYTEC Extension Board

PMIC Power management IC

PoE Power over Ethernet

POR Power-on reset

RTC Real-time clock.

SMT Surface mount technology.

SOM System on Module; used in reference to the PCM-058 /phyCORE®-i.MX 6

module

Sx User button Sx (e.g. S1, S2, etc.) used in reference to the available user

buttons, or DIP-Switches on the carrier board.

Sx_y Switch y of DIP-Switch Sx; used in reference to the DIP-Switch on the

carrier board.

Table 2: Abbreviations and Acronyms used in this Manual

phyCORE®-i.MX 6 [PCM-058]

viii ©PHYTEC Messtechnik GmbH 2016 L-808e_2

Preface

As a member of PHYTEC's phyCORE®product family the phyCORE-i.MX 6 is one of a series of

PHYTEC System on Modules (SOMs) that can be populated with different controllers and,

hence, offers various functions and configurations. PHYTEC supports a variety of 8-/16-

and 32-bit controllers in two ways:

(1) as the basis for Rapid Development Kits which serve as a reference and evaluation

platform

(2) as insert-ready, fully functional phyCORE®OEM modules, which can be embedded

directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design

allows you to focus on hardware peripherals and firmware without expending resources to

"re-invent" microcontroller circuitry. Furthermore, much of the value of the phyCORE®

module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware

will further reduce your development time and risk and allow you to focus on your product

expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce

development costs, and avoid substantial design issues and risks. With this new innovative

full system solution you will be able to bring your new ideas to market in the most timely

and cost-efficient manner.

For more information go to:

http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html or

http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

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