Pentek 71620 Manuel utilisateur

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Pentek Model 71620 Operating Manual Page 1

Manual Part No: 800.71620 Rev: 2.14 − December 27, 2017

Pentek, Inc.

One Park Way

Upper Saddle River, NJ 07458

(201) 818−5900

http://www.pentek.com

OPERATING MANUAL

MODEL 71620

3−Channel 200 MHz A/D, 2−Channel 800 MHz D/A

Cobalt Family XMC Module

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Page 2 Pentek Model 71620 Operating Manual

Warranty

Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are free from defects in mate−

rials and workmanship for a period of one year from the date of delivery when used under normal operating conditions and within the

service conditions for which they were furnished. The obligation of Pentek arising from a warranty claim shall be limited to repairing or

at its option, replacing without charge, any product that in Pentek’s sole opinion proves to be defective within the scope of the warranty.

Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected product returned to Pentek

within thirty days after discovery of such defect or nonconformity. Buyer shall prepay shipping charges, taxes, duties and insurance for

products returned to Pentek for warranty service. Pentek shall pay for the return of products to buyer except for products returned from

another country.

Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized modification, misuse, neglect,

inadequate maintenance, or accident, or for any product that has been repaired or altered by anyone other than Pentek or its authorized

representatives.

The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written or oral, is expressed or

implied. Pentek specifically disclaims fitness for a particular purpose. Under no circumstances shall Pentek be liable for any direct, indi−

rect, special, incidental, or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or any

other legal theory.

Copyrights

reproduced in any form without written permission.

Trademarks

Pentek, Cobalt, GateFlow, and ReadyFlow are registered trademarks or trademarks of Pentek, Inc.

Linux is a registered trademark of Linus B. Torvaids. PowerPC is a registered trademark of International Business Machines Corporation.

Microsoft and Windows are registered trademarks of Microsoft Corporation. PCI, PCI Express, PCIe, and PCI−SIG are trademarks or reg−

istered trademarks of PCI−SIG. VxWorks is a registered trademark of Wind River Systems, Inc. Xilinx and Virtex are registered trade−

marks or trademarks of Xilinx, Inc.

Manual Revision History

Date Revision Comments

6/10 − 5/11 Preliminary Contact Factory for manual revision history.

6/21/11 A Sect 5.14, corrected description of BUSY bit in CDC Control/Status Register, per KBCase 1382.

Release manual Revision A.

7/21/11 A.1 Sect 5.33, added note to NUM BYTES, bits 3−0, for accessing board ID EEPROM.

8/18/11 A.2 Sect 2.7.1, corrected external CLK maximum input to +12 dBm.

10/25/11 A.3 Sect 7.17, corrected RAM Capture Count Register address to 0x30044 in Table 7−17.

11/4/11 A.4 Sect 3.5.3, Sect 5.14, & Sect 5.21, corrected description of CDC reset per KBCase 1391.

12/13/11 A.5 Sect 2.2.2, updated switch SW2 descriptions.

Sect 2.7.2, removed incorrect reference to Option 002.

12/22/11 A.6 Sect 5.34.1, added new EEPROM format for boards shipped in November 2011 or later.

Sect 2.5 & Sect 2.7.4, added Note of input limits for PMC P14 and front panel Sync Bus connectors.

1/16/12 2.0 Version number change only. (Starting January 2012 Pentek upgraded document Version numbering.)

4/20/12 2.1 Sect 1.14 & Sect 2.7.1, corrected external clock input voltage limit to +10 dBm.

5/10/12 2.2 Sect 1.14, deleted Output IF specification for Digital to Analog Upconverter.

11/20/12 2.3 Sect 2.5.1, add XMC P16 connector pin definition table.

4/22/13 2.4 Updated several graphics’ fonts.

5/28/13 2.5 Sect 1.14 & Sect 2.7.1, corrected external clock input frequency maximum to 800 MHz.

8/2/13 2.6 Table 3−20, corrected Min VCCINT address to 0x08094.

9/6/13 2.7 Verified & updated cross−reference links in manual.

2/19/14 2.8 Sect 3.2.2, increased minimum number of clock cycles to 5 for DELAY in ADC Input Linked List.

3/21/14 2.9 Sect 2.2.2, changed switch SW2−5 to OFF, factory use only.

4/21/14 2.10 Sect 1.14, spec update: removed environmental Option 700 − Option 701 is now default.

6/12/14 2.11 Sect 1.14 & Sect 3.5, changed external Sync unit needed to Pentek Model 7893.

9/18/14 2.12 Sect 5.30, changed Timestamp Start Time Register to Write Only.

6/25/15 2.13 Sect 2.7.4, provided Pentek Model numbers for available mating connectors.

12/27/17 2.14 Sect 2.5.2 & Table 2−8, removed references to VMEbus from P14 connector.

Printed in the United States of America.

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Pentek Model 71620 Operating Manual Page 3

Page

Table of Contents

Rev.: 2.14

Chapter 1: Introduction

1.1 General Description............................................................................................................................17

1.2 Features ................................................................................................................................................17

1.3 Block Diagram.....................................................................................................................................18

Figure 1−1: Model 71620 Block Diagram.......................................................................................18

1.4 Principle of Operation........................................................................................................................19

1.5 Analog to Digital Input Conversion ................................................................................................20

1.6 Digital to Analog Output Conversion .............................................................................................20

1.7 FPGA Digital Interfaces .....................................................................................................................20

1.8 FPGA Configurations.........................................................................................................................20

1.9 Memory................................................................................................................................................21

1.10 Timing and Synchronization.............................................................................................................21

1.11 XMC Baseboard Interfaces ................................................................................................................21

1.12 Board Support Software ....................................................................................................................22

1.13 Supporting Documentation...............................................................................................................22

1.14 Specifications.......................................................................................................................................23

Chapter 2: Installation and Connections

2.1 Inspection.............................................................................................................................................29

Figure 2−1: Model 71620 PCB Assembly Drawing, Connector Side .......................................29

2.2 DIP Switch Settings ............................................................................................................................30

Figure 2−2: Model 71620 Main PCB Assembly Drawing, Solder Side....................................30

2.2.1 Switch SW1 − FPGA MGT Clock Operation ................................................................31

Table 2−1: SW1 − FPGA MGT Clock Operation........................................................31

Table 2−2: Aux MGT Clock Frequency − Switches SW1−3:4 ..................................31

Figure 2−3: Model 71620 FPGA MGT Clock Logic ....................................................32

2.2.2 Switch SW2 − FPGA Configuration ...............................................................................33

Table 2−3: SW2 − FPGA Configuration .......................................................................33

Table 2−4: FPGA Configuration Select − Switches SW2−3:4...................................33

2.3 PCB Jumpers........................................................................................................................................34

Figure 2−4: Model 71620 PCB Jumpers, Connector Side............................................................34

Table 2−5: Virtex−6 Program eFUSE Enable − Jumper Block J28 ............................................34

2.4 PCB LEDs.............................................................................................................................................35

Figure 2−5: Model 71620 PCB LEDs, Solder Side........................................................................35

Table 2−6: PCB LED Use ..................................................................................................................35

2.5 Baseboard Connectors........................................................................................................................36

2.5.1 XMC Connectors ...............................................................................................................36

Table 2−7: Option 105 XMC P16 FPGA Pin Connections.........................................36

2.5.2 PMC FPGA Connections (Option 104) ..........................................................................37

Table 2−8: Option 104 PMC P14 FPGA Pin Connections .........................................37

2.6 Installing the Model 71620 on an XMC Baseboard........................................................................38

Figure 2−6: Typical XMC Baseboard − Connectors & Mounting Hardware ........38

Figure 2−7: Baseboard PMC/XMC Connections.........................................................39

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Page 4 Pentek Model 71620 Operating Manual

Page

Table of Contents

Rev.: 2.14

Chapter 2: Installation and Connections (continued)

2.7 Front Panel Connections ................................................................................................................... 40

Figure 2−8: Model 71620 Front Panel............................................................................................40

2.7.1 Clock Input Connector .................................................................................................... 40

2.7.2 Analog Output Connectors ............................................................................................. 41

2.7.3 Analog Input Connectors ................................................................................................ 41

2.7.4 Sync Bus Connector ......................................................................................................... 42

Table 2−9: SYNC/GATE Connector Pins..................................................................... 42

2.8 Front Panel LEDs................................................................................................................................ 43

2.8.1 Link LED ............................................................................................................................ 43

2.8.2 User LED ........................................................................................................................... 43

2.8.3 Master LED ....................................................................................................................... 43

2.8.4 PPS LED ............................................................................................................................. 43

2.8.5 Over Temperature LED ................................................................................................... 43

2.8.6 Clock LED .......................................................................................................................... 43

2.8.7 DAC Underrun LED ........................................................................................................ 43

2.8.8 ADC Overload LEDs ....................................................................................................... 43

Chapter 3: Model 71620 Resource Operation

3.1 Overview ............................................................................................................................................. 45

Figure 3−1: Model 71620 Data Flow...............................................................................................45

3.2 Analog to Digital Input ..................................................................................................................... 46

Figure 3−2: Analog to Digital Input Channel Data Flow .......................................................... 46

3.2.1 ADC Data Packing Formats ............................................................................................ 47

3.2.1.1 Real−only Packed ......................................................................................... 48

Table 3−1: ADC PACK FIFO − Real−only Packed Format................... 48

3.2.1.2 Real−only Unpacked .................................................................................... 48

Table 3−2: ADC PACK FIFO − Real−only Unpacked Format ............. 48

3.2.1.3 I/Q Packed .................................................................................................... 49

Table 3−3: ADC PACK FIFO − I/Q Packed Data Format...................... 49

3.2.1.4 I/Q Unpacked ............................................................................................... 49

Table 3−4: ADC PACK FIFO − I/Q Unpacked Data Format ................ 49

3.2.2 ADC Input Linked List Operation ................................................................................. 50

Table 3−5: ADC Trigger Controller Linked List RAM ............................................. 50

Table 3−6: ADC1 Trigger Controller Linked List RAM ........................................... 52

Table 3−7: ADC1 Trigger Controller Linked List RAM ........................................... 53

3.2.3 ADC DMA Operation ...................................................................................................... 54

Table 3−8: ADC DMA Meta Data Format ................................................................... 54

3.2.4 ADC DMA Linked Lists .................................................................................................. 57

Table 3−9: ADC DMA Linked List RAM.................................................................... 57

Table 3−10: ADC Link Control Word Format............................................................. 58

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Pentek Model 71620 Operating Manual Page 5

Page

Table of Contents

Rev.: 2.14

Chapter 3: Model 71620 Resource Operation (continued)

3.3 Digital To Analog Output .................................................................................................................60

Figure 3−3: Digital to Analog Output Data Flow ........................................................................60

3.3.1 DAC DMA Linked Lists ..................................................................................................61

Table 3−11: DAC DMA Linked List RAM...................................................................61

Table 3−12: DAC Link Control Word Format .............................................................62

3.3.2 DAC Output Linked List Operation ..............................................................................64

Table 3−13: DAC Output Controller Linked List RAM............................................64

Table 3−14: DAC Output Controller Linked List RAM............................................68

Table 3−15: DAC Output Controller Linked List RAM............................................69

Table 3−16: QDRII+ Waveform Storage RAM ...........................................................70

3.3.3 DAC Data Routing and Formats ....................................................................................71

3.3.3.1 Dual Bus Mode − Channel−Packed FIFO .................................................71

Table 3−17: DAC FIFO, Channel−Packed Data Format ........................71

3.3.3.2 Half Rate Bus Mode − Time−Packed FIFO ...............................................72

Table 3−18: DAC FIFO, Time Packed Data Format................................72

3.4 RAM Memory Operation ..................................................................................................................73

Figure 3−4: RAM Memory Module Interfaces.............................................................................73

3.5 Timing and Synchronization.............................................................................................................74

3.5.1 Gates ...................................................................................................................................74

Figure 3−5: Gate Logic Diagram ....................................................................................75

3.5.2 Syncs ...................................................................................................................................76

Figure 3−6: Sync Logic Diagram ....................................................................................76

3.5.3 Clocks .................................................................................................................................77

Figure 3−7: Clock Logic Diagram ..................................................................................77

3.6 Interrupt Operation............................................................................................................................78

Figure 3−8: Interrupt Signal Logic Diagram.................................................................................78

3.6.1 PCIe Interrupts ..................................................................................................................79

3.6.2 Global Interrupts ..............................................................................................................80

3.6.3 ADC Interrupts .................................................................................................................81

3.6.4 DAC Interrupts .................................................................................................................82

3.7 FPGA Resources Operation...............................................................................................................83

3.7.1 FPGA System Monitor .....................................................................................................83

Table 3−19: System Monitor Measurement Ports ......................................................83

Table 3−20: System Monitor Status Register Addresses...........................................84

Table 3−21: System Monitor Control Register Addresses........................................85

3.7.2 I2C Bus Controllers ..........................................................................................................86

3.8 FLASH Memory Operation...............................................................................................................87

Table 3−22: FLASH Memory Map..................................................................................................87

3.9 User Register Address Space ............................................................................................................87

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Page 6 Pentek Model 71620 Operating Manual

Page

Table of Contents

Rev.: 2.14

Chapter 4: Model 71620 Memory Maps

4.1 Overview ............................................................................................................................................. 89

Table 4−1: Model 71620 PCI Memory Map.................................................................................. 89

4.2 Default FPGA Memory Map ............................................................................................................ 90

Table 4−2: Default FPGA Memory Map....................................................................................... 90

Chapter 5: Global Registers

5.1 Overview ............................................................................................................................................. 97

5.2 Link Status Register ........................................................................................................................... 98

Table 5−1: Link Status Register...................................................................................................... 98

5.2.1 MSI ENABLED ................................................................................................................. 99

5.2.2 MAX RD RQST ................................................................................................................. 99

5.2.3 MAX PAYLOAD .............................................................................................................. 99

5.2.4 SEL LINK WIDTH ......................................................................................................... 100

5.2.5 CORE NOM WIDTH ..................................................................................................... 100

5.2.6 SEL LINK RATE ............................................................................................................. 100

5.2.7 CORE NOM SPEED ....................................................................................................... 100

5.2.8 LINK UPCFG CAP ......................................................................................................... 100

5.2.9 PARTNER GEN2 SPRT ................................................................................................. 100

5.2.10 LINK GEN2 CAP ........................................................................................................... 101

5.2.11 LANE RVRSL MODE .................................................................................................... 101

5.2.12 INITIAL LINK WIDTH ................................................................................................. 101

5.3 Interrupt Flag Register .................................................................................................................... 102

Table 5−2: Interrupt Flag Register ............................................................................................... 102

Table 5−3: Interrupt Register Bits................................................................................................ 103

5.4 Interrupt Enable Register ................................................................................................................ 104

Table 5−4: Interrupt Enable Register .......................................................................................... 104

5.5 Byte Swap Register........................................................................................................................... 105

Table 5−5: Byte Swap Register ..................................................................................................... 105

5.6 Interrupt Control Register............................................................................................................... 106

Table 5−6: Interrupt Control Register ......................................................................................... 106

5.7 Global Register Reset Register........................................................................................................ 107

Table 5−7: Global Register Reset Register................................................................................. 107

5.8 Board Identification Register.......................................................................................................... 108

Table 5−8: Board Identification Register.................................................................................... 108

5.9 Daughter Board ID Register ........................................................................................................... 109

Table 5−9: Daughter Board ID Register...................................................................................... 109

5.9.1 FPGA TYPE ..................................................................................................................... 109

5.9.2 FPIO TYPE ....................................................................................................................... 109

5.9.3 MEM CD TYPE ............................................................................................................... 110

5.9.4 MEM AB TYPE ............................................................................................................... 110

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Pentek Model 71620 Operating Manual Page 7

Page

Table of Contents

Rev.: 2.14

Chapter 5: Global Registers (continued)

5.10 FPGA Code Type Register...............................................................................................................111

Table 5−10: FPGA Code Type Register .......................................................................................111

5.10.1 FPGA CODE EXPL .........................................................................................................111

5.10.2 MEM CD CODE ..............................................................................................................111

5.10.3 MEM AB CODE ..............................................................................................................112

5.10.4 FPGA CODE ID ..............................................................................................................112

5.10.5 CODE TYPE .....................................................................................................................112

5.11 FPGA Code Revision Register ........................................................................................................113

Table 5−11: FPGA Code Revision Register ................................................................................113

5.12 FPGA Date Code Register ...............................................................................................................114

Table 5−12: FPGA Date Code Register........................................................................................114

5.13 ICAP Register....................................................................................................................................115

Table 5−13: ICAP Register .............................................................................................................115

5.14 CDC Control/Status Register .........................................................................................................116

Table 5−14: CDC Control/Status Register...................................................................................116

5.14.1 BUSY .................................................................................................................................116

5.14.2 PRGM ...............................................................................................................................117

5.14.3 RESET ...............................................................................................................................117

5.14.4 RST EN .............................................................................................................................118

5.14.5 VCXO STAT ....................................................................................................................118

5.14.6 REF STAT .........................................................................................................................118

5.14.7 LOCK ................................................................................................................................118

5.15 CDC Data Register............................................................................................................................119

Table 5−15: CDC Data Register ....................................................................................................119

5.15.1 CDC Word 0 Register .....................................................................................................120

Table 5−16: CDC Word 0 Register...............................................................................120

5.15.2 CDC Word 1 Register .....................................................................................................121

Table 5−17: CDC Word 1 Register...............................................................................121

5.15.3 CDC Word 2 Register .....................................................................................................122

Table 5−18: CDC Word 2 Register...............................................................................122

5.16 Clock Control/Status Register........................................................................................................123

Table 5−19: Clock Control/Status Register.................................................................................123

5.16.1 CDC RDY .........................................................................................................................123

5.16.2 CDC CLKB/CLKA LOCKED .......................................................................................123

5.16.3 CDC CLKB/CLKA DET ................................................................................................124

5.16.4 FPGA CLKB/CLKA SRC SEL ......................................................................................124

Figure 5−1: CDC/FPGA Clock Logic...........................................................................124

5.16.5 FPGA CLKB/CLKA PWR DWN .................................................................................124

5.17 Sync Bus Control Register 1 ............................................................................................................125

Table 5−20: Sync Bus Control Register 1 ....................................................................................125

5.17.1 SBUS SYNCB DRV INV .................................................................................................126

5.17.2 SBUS GATEB DRV INV .................................................................................................126

5.17.3 SBUS SYNCA DRV INV ................................................................................................126

5.17.4 SBUS GATEA DRV INV ................................................................................................126

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Page 8 Pentek Model 71620 Operating Manual

Page

Table of Contents

Rev.: 2.14

Chapter 5: Global Registers (continued)

5.17 Sync Bus Control Register 1 (continued)

5.17.5 SBUS SYNCB DRV SRC ................................................................................................ 126

5.17.6 SBUS GATEB DRV SRC ................................................................................................ 126

5.17.7 SBUS SYNCA DRV SRC ................................................................................................ 126

5.17.8 SBUS GATEA DRV SRC ................................................................................................ 127

5.17.9 CLK SEL ........................................................................................................................... 127

5.17.10 VCXO OUT DISABLE ................................................................................................... 127

5.17.11 GATEB/SYNCB MSTR ................................................................................................. 127

5.17.12 GATEA/SYNCA MSTR ................................................................................................ 128

5.17.13 CLK MASTER EN .......................................................................................................... 128

5.18 Sync Bus Control Register 2............................................................................................................ 129

Table 5−21: Sync Bus Control Register 2.................................................................................... 129

5.18.1 PPS/SYNC/GATE A/B EDGE .................................................................................... 129

5.18.2 PPS/SYNC/GATE A/B POL ....................................................................................... 130

5.18.3 PPS B RCV SRC .............................................................................................................. 130

5.18.4 SYNC B RCV SRC .......................................................................................................... 130

5.18.5 GATE B RCV SRC .......................................................................................................... 130

5.18.6 PPS A RCV SRC .............................................................................................................. 131

5.18.7 SYNC A RCV SRC .......................................................................................................... 131

5.18.8 GATE A RCV SRC ..........................................................................................................131

5.19 Sync Bus Input Delay Tap Control Register................................................................................. 132

Table 5−22: Sync Bus Input Delay Tap Control Register........................................................ 132

5.19.1 IODELAY CNTRL RDY ................................................................................................ 132

5.19.2 SBUS SYNC B/A IN DLY ............................................................................................. 133

5.19.3 SBUS GATE B/A IN DLY ............................................................................................. 133

5.20 Sync Bus Input Delay Control Register......................................................................................... 134

Table 5−23: Sync Bus Input Delay Control Register................................................................ 134

5.20.1 SBUS SYNC B/A IN DLY ............................................................................................. 134

5.20.2 SBUS GATE B/A IN DLY ............................................................................................. 134

5.21 User LED Register............................................................................................................................ 135

Table 5−24: User LED Register ..................................................................................................... 135

5.22 LED Control Register....................................................................................................................... 136

Table 5−25: LED Control Register................................................................................................ 136

5.22.1 CLK DET LED CTRL ..................................................................................................... 136

5.22.2 ALMn/OT LED DISABLE ............................................................................................137

5.22.3 PPS LED SRC .................................................................................................................. 137

5.22.4 PPS LED DISABLE .........................................................................................................137

5.22.5 USER LED SRC ............................................................................................................... 137

5.22.6 xxx MSTR LED DISABLE .............................................................................................. 138

5.23 Gate A Generate Register................................................................................................................ 139

Table 5−26: Gate A Generate Register ........................................................................................ 139

5.24 Gate B Generate Register................................................................................................................. 139

Table 5−27: Gate B Generate Register......................................................................................... 139

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Pentek Model 71620 Operating Manual Page 9

Page

Table of Contents

Rev.: 2.14

Chapter 5: Global Registers (continued)

5.25 Sync A Generate Register ................................................................................................................140

Table 5−28: Sync A Generate Register.........................................................................................140

5.26 Sync B Generate Register.................................................................................................................141

Table 5−29: Sync B Generate Register.........................................................................................141

5.27 Test Signal and Timestamp Control Register...............................................................................142

Table 5−30: Test Signal and Timestamp Control Register ......................................................142

5.27.1 TS START TIME LOAD .................................................................................................142

5.27.2 TS PPS SIG EN ................................................................................................................142

5.27.3 TS SYNCA RST EN .........................................................................................................143

5.27.4 TS MODULE RST ...........................................................................................................143

5.27.5 SYS MON RST .................................................................................................................143

5.27.6 TEST SIG SYNCB RST EN .............................................................................................143

5.27.7 TEST SIG SYNCA RST EN ............................................................................................143

5.27.8 TEST SIG RST ..................................................................................................................143

5.28 Test Sine A Frequency Control Register........................................................................................144

Table 5−31: Test Sine A Frequency Control Register ...............................................................144

5.29 Test Sine B Frequency Control Register ........................................................................................144

Table 5−32: Test Sine B Frequency Control Register ...............................................................144

5.30 Timestamp Start Time Register ......................................................................................................145

Table 5−33: Timestamp Start Time Register ..............................................................................145

5.31 TWSI Port 1 Control/Status Register.............................................................................................146

Table 5−34: TWSI Port 1 Control/Status Register .....................................................................146

5.31.1 RX FIFO CNT[4:0] ...........................................................................................................147

5.31.2 RX FIFO FULL .................................................................................................................147

5.31.3 RX FIFO EMPTY .............................................................................................................147

5.31.4 TX FIFO FULL .................................................................................................................147

5.31.5 TX FIFO EMPTY .............................................................................................................147

5.31.6 TRNSFR BUSY ................................................................................................................147

5.31.7 TWSI ADDR[6:0] .............................................................................................................148

Table 5−35: TWSI Port 1 Bus Addresses ....................................................................148

5.31.8 START TRNSFR ..............................................................................................................148

5.31.9 DATA DIR .......................................................................................................................148

5.31.10 PORT ENABLE ...............................................................................................................148

5.31.11 NUM BYTES[3:0] ............................................................................................................148

5.32 TWSI Port 1 Data Register...............................................................................................................150

Table 5−36: TWSI Port 1 Data Register .......................................................................................150

5.32.1 Main PCB LM83 Temperature Sensor .........................................................................151

Table 5−37: Main PCB LM83 Programmable Sensors.............................................151

5.32.2 Front Panel Module LM83 Temperature Sensor ........................................................151

Table 5−38: Front Panel PCB LM83 Programmable Sensors..................................151

5.32.3 Memory Module LM73 Temperature Sensors ...........................................................152

5.32.4 Si571 Programmable VCXO ..........................................................................................152

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