Panasonic CF-2700 Manuel utilisateur

ORDER

NO.

IED84113035C2

Service

Manual

MSX

Personal

Computer

CF-2700

Specifications

Microprocessor

Z-80A

Memory

ROM

bytes

(MSX-BASIC)

Main

RAM

64K.bytes

Video

RAM

16K

bytes

Video

system

Controller

Number

displayable

characters

Number

displayable

dots

Output

signals

Sound

system

Controller

Functions

Keyboard

Cassette

tape

interface

System

Transfer

rate

I/O

ports

Slot

Printer

port

General

port

Sound

output

Dimensions

and

Weight

(Main

unit)

Power

requirements

Voltage

Power

consumption

TMS

9929A

characters

lines

(H)

(W)

dots/character

mode

characters

lines

(H)

(W)

dots/character

mode

256

(H)

192

(V)

dots

Video

output,

output

AY-3-8910A

octave,

chord

output

keys

FSK

1200/2400

baud

(comforms

MSX

specifications)

14-pin

9-pin

each

436

(W)

245

(D)

(H)

approx.

3.6

220

(Only

for

240

Hz)

Design

and

Specifications

are

subject

change

without

notice.

Panasonic

Matsushita

Electric

Trading

Co.,

Ltd.

P.O.

Box

288,

Central

Osaka

Japan

CONTENTS

Location

Controls

and

Components

Memory

Map

I/O

Map

General

for

Peripheral

Circuit

Display

Screen,

Character

Codes

Self

Test

Block

Diagram

Disassembly

Instructions

Adjustment

Connector

Connection

Wiring

Connection

Diagram

Schematic

Diagram

(Main

Board)

Printed

Circuit

Board

(Main

Board)

Schematic

Diagram

Printed

Circuit

Board

(Power

Source)

Schematic

Diagram

(Video

Board)

Printed

Circuit

Board

(Video

Board)

Printed

Circuit

Board

(Keyboard)

Block

Diagram

Parts

Location

Parts

Location

(Keyboard)

Packing

Instruction

Replacement

Parts

List

Matsushita

Electric

Industrial

Co.,

Ltd.

1984

The

EE3

system

realizes

software

compatibility

between

personal

computers.

trademark

Microsoft

Corporation.

IMPORTANT

(FOR

U.K.)

The

wires

the

mains

lead

are

coloured

accordance

with

the

following

codes:

Blue:

Neutral

Brown:

Live

the

colours

the

wires

the

mains

lead

this

apparatus

may

not

correspond

with

the

coloured

markings

identifying

the

terminals

your

plug,

proceed

follows:

•The

wire

which

coloured

blue

must

connected

the

terminal

which

marked

with

the

letter

coloured

black.

•The

wire

which

coloured

brown.

must

connected

the

terminal

which

marked

with

the

letter

coloured

red.

Notes:

•Disconnect

the

mains

plug

from

the

supply

socket

when

not

use.

•Do

not

remove

cover.

Live

parts

inside.

(located

the

left

side)

fctr-i

POWER

OFF

(T^Function

keys

Key

used

for

easy

inputs

pre¬

defined

character

strings.

(

)Power

indicator

Lights

when

the

power

switch

turned

and

goes

out

when

the

power

turned

off.

(14)

Sound

output

jack

Audio

(sound)

signal

Connects

the

terminal.

output

audio

jack.

input

(l5)

Video

output

jack

Video

signal

output

jack.

Connects

the

video

input

terminal.

(3)

pecial

keys

Keys

used

select,

correct,

and

edit

input

characters,

and

control

program

execution.

(16)

output

jack

signal

output

jack,

the

antenna

terminal.

Connects

(

)Space

bar

Bar

used

input

space

between

characters.

(3)

Character

keys

Keys

used

input

characters.

(17)

Channel

adjust

trimmer

After

connecting

the

and

computer,

turn

the

power

switch.

Set

the

UHF

channels

35-37.

Insert

the

adjustment

screwdriver

into

the

channel

adjust

trimmer

and

adjust

for

clear

picture.

(6)Cursor

keys

Keys

used

move

the

cursor.

(7)

(¥)

General

port

General

port

Connectors

used

connect

joysticks,

tablets,

etc.

(18)

Power

switch

Power

turns

when

set

"ON"

and

the

power

indicator

lights

up.

Power

turns

off

when

set

"OFF".

9;(10)

Slot

Slots

for

MSX

cartridges.

(ll)Printer

connector

Connector

used

connect

printer,

plotter,

etc.

(l2)

assette

Input/Output

Connector

used

connect

cassette

tape

recorder.

(13)

ower

cord

Memory

Map

(when

using

BASIC)

Address

hexadecimal

0000

ROM

area

8000

User

area

RAM

area

F380

FFFF

MSX

BASIC

ROM

Program

area

(text

area)

Variable

area

Array

variable

area

Free

area

Stack

area

Character

string

area

File

control

block

(User

reserve

area)

Work

area

(system

area)

I/O

Map

Area

storing

the

program

which

line

numbers

have

been

added.

Area

for

variables.

For

character

variables,

this

area

stores

the

pointer

which

points

the

character

string

(string

descriptor).

Area

for

array

variables.

the

array

variables

are

the

character

type,

this

area

stores

the

pointer

which

points

the

string

the

string

area.

This

area

allocated

when

the

DIM

statement

executed

and

array

with

subscript

less

used.

The

free

area

unused

area.

The

size

the

free

area

the

size

the

user

area

minus

the

sizes

the

character

area,

stack

area,

variable

area,

and

program

area.

The

size

the

free

area

can

obtained

the

FRE

function.

Stack

area

storing

the

return

address

for

BASIC

when

the

FOR-NEXT

statement

GOSUB

statement

executed.

Area

storing

the

strings

contained

the

character

variables

and

array

variables.

The

size

the

string

area

specified

the

CLEAR

statement.

size

specified

the

CLEAR

statement,

area

200

bytes

allocated.

Area

used

during

the

input

and

output

files.

This

area

allocated

according

the

number

specified

the

MAXFILES

statement.

The

high

limit

address

can

set

the

CLEAR

statement

F380

below

that

area

(such

for

machine

language

subroutines)

can

allocated

until

the

work

area

for

free

use

the

user.

Work

area

used

BASIC.

Port

Bit

I/O

Signal

Name

Description

ffH

Specifies

the

slot

number

for

addresses

&H0-&H3FF

Specifies

the

slot

number

for

addresses

&H4000-&H7FFF

■

Specifies

the

slot

number

for

addresses

&H8000-&H8FFF

Specifies

the

slot

number

for

addresses

'If

•

&HC000-&HFFFF

Keyboard

return

signal

KB0,

KB1

KB2,

KB3

Keyboard

scan

signal

Cassette

control

(ON

when

Cassette

write

signal

CAPS

lamp

signal

(lights

when

SOUND

Software

controlled

sound

output

I/O

Address

Assignment

I/O

address

(hexadecimal)

■

RS-232C

Printer

VDP

(9929A)

PSG

(AY-3-8910A)

PP1

(8255)

I/O

address

R/W

Contents

Remarks

&H98

Data

write

the

video

RAM

Data

read

from

the

video

RAM

&H99

Command,

address

set

Status

read

&HA0

Address

latch

&HA1

Data

write

&HA2

Data

read

&HA8

Port

data

write

Port

data

read

&HA9

Port

data

write

Port

data

read

&HAA

Port

data

write

Port

data

read

&HAB

Mode

set

&H90

Strobe

output

(bO)

Latch

output

Status

input

(bl)

"l”

when

busy

&H91

data

Latch

output

•The

I/O

address

with

the

■

mark

are

provided

optional

equipment.

•For

details

the

VDP,

PSG,

and

PPI,

see

their

respective

manuals.

•Addresses

&H40-&HFF

represent

the

system

reserve

area.

PSG

Bit

Assignment

Port

Bit

I/O

Bit

Port

Connector

Number

Input

Low

level

High

level

Port

Low

level

High

level

Port

Low

level

High

level

Port

Low

level

High

level

Port

Low

level

High

level

Port

Low

level

High

level

Port

Keymatrix

assignment

input

(low

level)

CSAR

(Read

signal

the

cassette

tape)

Output

Port

►

Note

Port

Input

select

port

Note

Either

port

selected

the

output

level

bit

port

Writing

"1"

bit

port

■

high

level

output

port

selected.

Writing

"0"

bit

port

low

level

output

port

selected.

Note

sure

output

high

level

these

pins

portB

used

for

input.

General

for

Peripheral

Circuit

CPU

(Central

Processing

Unit)

Peripheral

Circuit

CPU

Peripheral

Circuit

consists

CPU,

Clock

Generator

Circuit

and

Reset

Circuit.

Z80A

(pPD780C-l,

IC8)

used

CPU.

interruption

system

maskable

inter¬

rupt,

not

non-maskable.

AND

signals

VDP's

INT

and

external

interrupt

are

fed

INT

terminal.

cycle,

WAIT

inserted,

and

external

WAIT

ac¬

cepted

asynchronously

with

CLOCK

signal.

BUSRQ

and

BUSAK

are

not

used,

neither

DMA

function.

Fig.

CPU

Peripheral

Circuit

The

CLOCK

Generator

Circuit—Serial

Os¬

cillation

Circuit

74HC04

(IC43)--

oscillates

10.6781522

MHz

generate

VDP

CLOCK

and,

the

same

time,

gener¬

ates

CPU

CLOCK

the

circuit

74LS74

(IC42)

and

74LS107

(IC47)

which

divides

VDP

CLOCK

get

3.559384

MHz.

Moreover,

CLOCK

Generator

Circuit

di¬

vides

CPU

CLOCK

into

halves

get

1.779462

MHz

74LS74

(IC39)

and

gen¬

erates

PSG

CLOCK.

CPU

CLOCK

3.55938MH!

IIC8.PIN6I

PSG

CLOCK

1.77946

MHz

I1C

39.

Fig.

CLOCK

Waveform

The

Reset

Circuit

utilizes

the

charge

Circuit

(C13

and

R26),

but

takes

too

much

time

raise

RESET

signal

only

the

CR.

the

circuit

compul¬

sively

raised

Q10,

when

each

end

becomes

about

1.5

Therefore,

RESET

signal

changes

"L"

into

"H"

after

power

source

ON.

POWER

SOURCE

RESET

i—i—i—i—i—i—i—i-

100

(ms)

Fig.

RESET

Signal

IROM

~~|

This

system

uses

bits

MASK

ROM

(IC32,

MN23257)

which

builds

the

MSX

BASIC.

connected

SLTO,

and

A15.

Access

time

available

Main

Memory

Peripheral

Circuit

Main

Memory

Peripheral

Circuit

consists

Main

Memory

and

Memory

Access

Cir¬

cuit.

The

Main

Memory

has

memory

space

using

eight

8-bit

DRAMs.

Re¬

fresh

performed

RAS-ONLY

REFRESH.

Because

RAS

pre-charge

time

refresh¬

ing

cycle

ensured

100

Timing

Chart,

the

access

time

RAM

must

150

ns.

the

Memory

Access

Circ

uit,

RAS

generated

MERQ

RESH

and

CLOCK.

The

switchover

the

row

address

the

column

address

done

the

multiplexer

74LS157

and

CAS

generated

being

staggered

the

time,

with

the

condenser

C35,

when

the

column

address

outputted.

C35

ensures

that

the

CAS

will

"L",

considering

differences

the

output

timing

74LS157,

after

the

switchover

the

row

address

the

column

address.

gen

erated

BWR,

and

BRD.

RAS,

CAS,

and

protect

from

the

undershoot

being

inserted

resist¬

ance

for

the

damping.

All

Input/Output

with

external

equipment

are

done

through

I/O

ports

this

system,

and

access

signal

each

port

generated

this

circuit.

I/O

Select

Peripheral

Circuit

consists

I/O

Select

Generator

Circuit,

Chip

Access

Signal

Generator

Circuit

and

Short

Write

Generating

Circuit.

Fig.

I/O

Select

Peripheral

Circuit

I/O

Select

Peripheral

Circuit

I/O

Select

Generator

Circuit

generates

I/O

Select

signal

according

the

I/O

map.

This

signal

generated

through

high-order

five

bits

low-order

byte

Address

Bus

and

through

BIORQ

and

Multiplexer

74LS138

(IC25).

order

ensure

data

stabilizing

time

when

PSG

engaged

WRITE,

and

considered

that

the

output

delay

time

350

when

PPI

WRITE,

WRITE

signal

raised

faster

Short

Write

Generator

Circuit.

Chip

Access

Generator

Circuit

nerates

CSW/CSR

(VDP

Access

signals),

IWR/

PPIRD

(PPI

Access

signals)

and

BCl/BDIR

(PSG

Access_signa

ls)

from

I/O

Select

signal

and

BWR/BRD/SWR.

Automatic

refreshing

function

VRAM

Composite

video

output,

PAL

system

Interruptible

every

frame

Automatic

processing

the

sprite

screen.

This

system

uses

TMS9929A

CRTC.

This

LSI’s

features

are

follows.

256

192

pixels

resolution

Used

4,8

and

VRAM

(16

used

MSX.)

Table

Screen

Mode

VDP.

VDP's

operation

depends

values

READ

and

WRITE,

VDP

resistor

VRAM.

registers

VDP

and

table

VRAM.

"L",

VRAM

the

candidate.

con-

VDP

has

three

control

signals

which

are

nected

MODE

terminal.

CSR

gener-

CSW,

CSR

and

MODE.

MODE

signal

distin-

ated

Inverted

AND

CSVDP

and

RD,

guishes

which

should

candidate

for

and

CSW

CSVDP

and

WR.

Fig.

VDP

Peripheral

Circuit

Diagram

PSG

(Programmable

Sound

Generator)

Peripheral

Circuit

PSG

Block

consists

PSG

and

General

Port

Circuit.

This

system

uses

GI's

AY-3-8910A

PSG,

which

makes

enable

produce

octaves,

triple

chords

and

noise-sound

effects.

This

LSI

builds

tone

generator,

noise

generator,

envelope

generator

and

registers

whose

each

value

decides

the

frequency

and

the

volume

the

sound

software.

This

LSI

has

also

two

I/O

ports

which

are

available

for

Input/Output

with

General

Port,

Keyboard

Control

and

input

cassette

tape

recorder.

this

occasion,

each

bit

port

A/B

assigned

the

following

table.

'-'1

I/O

Function

Input

PORT

1-1

PORT

2-1

PORT

1-2

PORT

2-2

PORT

1-3

PORT

2-3

PORT

1-4

PORT

2-4

PORT

1-6

PORT

2-6

PORT

1-7

PORT

2-7

Input

specifying

the

layout

Keyboard

Read

signal

input

from

cassette

tape

recorder

Output

P0RT1

PORT1

P0RT2

P0RT1

PORT2

Selecting

input

PORT

"L"=P0RT

"H"=P0RT

Table

Bit-Assignment

PSG

Port

PSG

has

three

control

lines—BDIR,

BC1

Input/Output

are

shown

the

following

and

BC2—,

whose

control

signals

table.

BDIR

BC1

BC2

State

Not

Selected

Readout

from

PSG

Writing

PSG

Address

latch

Table

PSG

Control

Signal

Table des matières

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