NXP Semiconductors MPC560xP Mode d’emploi

1 Introduction

The MPC560xP microcontrollers are members of the 32-bit

Qorivva microcontroller family built on the Power

Architecture® technology. The devices are targeted at the

chassis and safety market segment, especially the Electrical

Hydraulic Power Steering, low end Electrical Power Steering

and Airbag applications.

The purpose of this document is to describe hardware design

considerations when developing hardware for the MPC560xP

family of microcontrollers: 5604P, 5603P, 5602P, 5601P. It

will cover topics such as clock generation, decoupling,

Voltage regulator and power considerations. Detailed

reference design schematics and descriptions of the main

components are also contained within this document. Some

general hardware recommendations are also provided.

2 Power Supply

The MPC5604P has a single main/input voltage supply which

can be either 5 V or 3.3 V with a specified tolerance of ±10%

this is converted using the internal VREG to 1.2V ±10% for

the core logic. The user is not permitted to supply the core

logic via an external 1.2 V supply, they must always use the

on-chip voltage regulator (VREG).

Freescale Semiconductor Document Number: MPC560xPQRUG

Design Guide Rev. 0, 2012

Hardware Design Guide

MPC560xP devices

Contents

1 Introduction................................................................1

2 Power Supply............................................................1

3Clock Circuity...........................................................7

4Analogue to Digital Convertor (ADC)......................9

5Recommended debug connectors and

connector pin out definitions..................................11

6 MPC56xx high-speed parallel trace

connector.................................................................12

7 Minimum external circuitry....................................14

8 Example communication peripheral

connections..............................................................15

9 Pin Overview...........................................................21

The internal regulator has 3 different domains:

• Low Voltage Domain for 1.2 V output to the core

• High Voltage Domain for 5 V supply

• High Voltage Domain for 3.3 V supply

MPC5604P has 6 different pin supply voltages:

Symbol Description

VDD_HV_REG Voltage regulator supply voltage

VDD_LV_COR 1.2v Core supply

VDD_HV_IO Input/Output supply voltage

VDD_HV_ADC ADC supply and high voltage reference

VDD_HV_OSC Crystal oscillator amplifier supply voltage

VDD_HV_FL Code and data flash supply voltage

HV: High Voltage external power supply for voltage regulator module. These pins must be connected to the power supply

(3.3 V or 5 V).

LV: Low Voltage (1.2 V) internal power supply for the Core, PLL. This voltage is generated by the internal voltage regulator

with external connections available for stability decoupling capacitors. It is further split into three main domains to ensure

noise isolation between critical LV modules within the device: Core, Flash , PLL

HV_ADC dedicated to the Analog to Digital Converter functions.

2.1 Voltage Regulator

The voltage regulator on the MPC560xP converts the main input supply 3.3 V or 5.0 V ±10% to 1.2 V core logic level. The

internal voltage regulator requires an external capacitance to be connected to the device in order to provide a stable 1.2 V low

voltage digital supply to the device.

2.2 Ballast Transistor

The internal VREG requires an external NPN ballast transistor (BCP56, BCP68, BCX68 or BC817) to be connected as given

in Figure 1. The NPN provides a stable low voltage digital supply to the device and serves as the main current source for the

device.

Power Supply

Hardware Design Guide, Rev. 0, 2012

2 Freescale Semiconductor, Inc.

Table 2. Recommended Ballast Transistors

Part Manufacturer Recommended derivative

BCP68 ON semi BCP68

Infineon BCP68-10

NXP BCP68-10; BCP68-25

Fairchild BCP68-10; BCP68-25

BCX68 Infineon BCX68-10;BCX68-16; BCX68-25

Fairchild BCX68

BC817 Infineon BC817-16; BC817-25; BC817SU

NXP BC817-16; BC817-25

Fairchild BC817-16;BC817-25; BC817-40

BCP56 ON semi BCP56-10

Infineon BCP56-10; BCP56-16

NXP BCP56-10; BCP56-16

Fairchild BCP56

ST BCP56-16

The ballast transistor provides regulator stability. Stability refers to the way which the regulator reacts to changes in the load.

An unstable circuit may enter a state of continuous oscillation.

Figure 1 represents a typical example of the ballast transistor circuitry.

Power Supply

Hardware Design Guide, Rev. 0, 2012

Freescale Semiconductor, Inc. 3

BCTRL

VDD_LV_COR

CDEC3

CDEC2 CDEC1

VDD_HV_REG

BCP56,

BCP68,

BCX68,

BC817

MPC5604P

Figure 1. Configuration without base resistor

BCTRL - (Voltage Regulator external NPN Ballast base control pin) controls the current on the base of the transistor. The

current is increased to raise the voltage on the VDD and decreases to lower the voltage. The gain of the transistor controls the

maximum current available on the supply pin. The gain should be high enough to allow for startup and low enough to prevent

the regulator becoming unstable.

Symbol Parameter Conditions Min Typ Max Unit

VDD_LV_REGCOR Output voltage

under maximum

load run supply

current

configuration

Post-trimming 1.15 - 1.32 V

CDEC1 External

decoupling/

stability ceramic

capacitor

4 capacitances 40 56 - µF

RREG Resulting ESR

of all four CDEC1

Absolute

maximum value

between 100

kHz and 10

MHz

- - 45 mΩ

Table continues on the next page...

Power Supply

Hardware Design Guide, Rev. 0, 2012

4 Freescale Semiconductor, Inc.

CDEC2 External

decoupling/

stability ceramic

capacitor

4 capacitances

of 100 nF each

400 - - nF

CDEC3 External

decoupling/

stability ceramic

capacitor on

VDD_HV_REG

- 40 - - µF

2.3 Capacitors

The ballast transistor requires capacitors to be added for decoupling and stability. The number of capacitors is not important

— only the overall capacitance value and the overall ESR value are important.

• C1 – The capacitance on VDD_LV is determined by the stability requirement of the regulator. It is recommended that the

40µF value is split between the VDD_LV_COR / VSS_LV_COR pair pins, 4x10µF capacitors placed as close as possibly to

the MCU pins.

• C2 – The 4 x100nF decoupling capacitors are required to filter high frequency noise and smooth the 5 V input signal,

again these should be placed as close as possible to the MCU pins.

• C3 – The 40µF capacitance value is required to meet the voltage drop on the collector and transient requirements,

especially during power-up. It is recommended to place the 40µF capacitor as close as possible to the ballast transistor

collector pin.

47 µF cap can be added to the VDD 5V as a bulk capacitance to reduce ripple from the input supply (optional).

The bypass capacitors serve two purposes:

• To provide (normally dominant) pole to ensure loop stability

• Used as a charge tank for load demand changes. This means if for example load suddenly drops, the cap on the collector

will consume the current until the regulator has adapted to the new situation (and vice versa)

NOTE

Required capacitor values listed in the table include a de-rating factor of 40%, covering tolerance, temperature, and aging

effects. These factors are taken into account to assure proper operation under worst case conditions. X7R type materials are

recommended for all capacitors, based on ESR characteristics.

2.4 Additional design option

The output stage for the power transistor is a class A stage, PMOS power device, loaded with a bit current towards ground.

Thus only the current source towards ground can remove charge in the base of the power transistor, so the turn off delay is

not acceptable. Adding an external resistor base to ground improves the situation and decreases the max available base

current. Using this approach it is possible to reduce load capacitance from 40μF to 20μF as shown in Figure 2. This is

achieved through the addition of an external 20 kresistor added to the base of the transistor. Addition of this pull-down

resistor reduces the response rate of the regulation loop, and therefore reduces the amount of reserve required to respond to

changes in the load. This option may reduce component cost.

Power Supply

Hardware Design Guide, Rev. 0, 2012

Freescale Semiconductor, Inc. 5

BCTRL

VDD_LV_COR

CDEC3

CDEC2 CDEC1

VDD_HV_REG

BCP68,

BCX68,

BC817SU

MPC5604P

Figure 2. Configuration with base resistor

Note: For 5601P and 5602P the 20k base resistor has been integrated into the MCU and additional component is not required.

Symbol Parameter Conditions Min Typ Max Unit

VDD_LV_REG

COR

Output voltage

under maximum

load run supply

current

configuration

Post-trimming 1.15 ˉ 1.32 V

RBExternal

resistance on

bipolar junction

transistor (BJT)

base

Bipolar BCP68

or BCX68 or

BC817. Three

capacitance s of

10µF

19.5 30 ˉ µF

RREG Resulting ESR

of either one or

all three CDEC1

Absolute

maximum value

between 100

kHz and 10

MHz

ˉ ˉ 45 m

CDEC1 External

decoupling/

stability ceramic

capacitor

Bipolar BCP68

or BCX68 or

BC817SU

Three

capacitances of

10 μF

19.5 30 ˉ µF

Bipolar BC817

One

capacitance of

22 μF

14.3 22 ˉ

Table continues on the next page...

Power Supply

Hardware Design Guide, Rev. 0, 2012

6 Freescale Semiconductor, Inc.

Symbol Parameter Conditions Min Typ Max Unit

CDEC2 External

decoupling/

stability ceramic

capacitor

Four

capacitances of

440 nF each

1200 1760 ˉ nF

CDEC3 External

decoupling/

stability ceramic

capacitor on

VDD_HV_REG

Two

capacitances of

10 μF each

2 x 10µF ˉ ˉ µF

3 Clock Circuity

The MPC5604P has 4 clock sources.

• IRC— internal RC oscillator

• XOSC — external oscillator clock

• FMPLL_0 - 64 Mhz PLL (max) for System clock

• FMPLL_1 - 120 Mhz PLL (max) for Motor control peripherals

The IRC is internal and does not have to be considered from a hardware design perspective. The FMPLL is described in

Section 3.1.

The XOSC external crystal oscillator works in a range from 4 MHz to 40 MHz. The crystal oscillator circuit includes an

internal oscillator driver and an external crystal circuitry. It provides an output clock that can be provided to PLL or used as a

reference clock to specific modules depending on system requirements.

Referring to the schematic of the on-chip oscillator (Figure 3: Reference oscillator circuit), the key items are described in the

following section. The oscillator circuit provides a reference clock signal to the on-chip PLL. The oscillator circuit consists

of:

• the crystal

• two capacitors

• The external bias resistor (R1) is not required as there is an internal bias resistor within the recommended crystals.

However, it is recommended to leave space for one on the PCB to accommodate different crystal configurations in the

future.

Clock Circuity

Hardware Design Guide, Rev. 0, 2012

Freescale Semiconductor, Inc. 7

Figure 3. External crystal circuit

The load capacitors are dependent on the specifications of the crystal and on the board capacitance. It is recommended to

have the crystal manufacturer evaluate the crystal on the evaluation board / PCB.

3.1 Frequency Modulated PLL (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4MHz to 40MHz input clock. Futhermore, the

FMPLL supports programmable frequency modulation of the system clock. The PLL has the following major features:

• Input clock frequency from an 4MHz to 40MHz

• Voltage controlled oscillator (VCO) range from 256MHz to 512MHz

• Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to re-lock

• Frequency modulated PLL

• Modulation enabled/disabled through software

• Triangle wave modulation

• Programmable modulation depth (±0.25% to ±4% deviation from center frequency)

• Programmable modulation frequency dependent on reference frequency

• Self-clocked mode (SCM) operation

• Input supply : same as core supply : 1.2V

The MPC56xx devices can use either the on-chip oscillator with an external crystal or an external reference clock as the

reference clock to the device. This reference is qualified in multiple manners before the PLL will begin lock operation. The

“pre” FMPLL circuitry consists of an automatic level-controlled amplifier, a comparator, a loss of clock detector, and a

predivider.

Clock Circuity

Hardware Design Guide, Rev. 0, 2012

8 Freescale Semiconductor, Inc.

3.2 Approved crystals

Following is a list of crystals that have been tested and approved by Freescale. If you wish to use a crystal not on this list

please work with the crystal manufacturer to ensure compatibility.

Table 5. Approved crystals

Nominal

frequency

Crystal info Crystal

equivalent

series

resistance ESR

Crystal motional

capacitance

(CI) fF

Crystal motional

inductance (LI)

Load on xtalin/

xtalout

C1=C2(pF)

Shunt

capacitance b/w

xtalout and

xtalin C0(pF)

4.0 NX8045GB 300 2.68 591.0 21.0 2.93

8.0 NX5032GA 300 2.46 160.7 17.0 3.01

10.0 NX5032GA 150 2.93 86.6 15.0 2.91

12.0 NX5032GA 120 3.11 56.5 15.0 2.93

16.0 NX5032GA 120 3.90 25.3 10.0 3.00

40.0 NX5032GA 50 6.18 2.56 8.0 3.49

the CERALOCK resonators listed below have also been approved for use on all MPC560xP devices based on the e200z0

core.

Table 6. Approved resonators

Part

number

vibratio

Fr[kHz[ Fa[kHz] Fa-

Fr(dF)

[kHz]

Ra[ohm

]

R1[ohm

]

L1[mH] C1[pF] Co[pF] Qm CL1(No

minal)p

CL2(no

minal)p

CSTCR

4M00G

53-R0

Funda

mental

3929.5

4163.2

233.75 372.41 12.78 0.8444

1.9426

15.857

1630.9

15 15

CSTCR

4M00G

55-R0

Funda

mental

3898.0

4123.0

225.00 465.03 11.38 0.8824

1.8891

15.905

1899.7

39 39

4 Analogue to Digital Convertor (ADC)

The ADC module has an independent A/D converter supply and reference voltage which allows for an isolated analog

voltage supply input pin VDD_HV_ADC, resulting in a low noise voltage source. The VDD_HV_ADC must be at the same

voltage as the digital voltage supply VDD_HV, in addition to the VSS_HV_ADC analog ground in for further supply

isolation.

Analog signals should not run parallel to clock or any noisy signals such as XTAL and EXTAL and should cross at right

angles if necessary.

Symbol Description

VDD_HV_AD0 ADC0 supply and high reference voltage

VSS_HV_AD0 ADC0 ground and low reference voltage

VDD_HV_AD1 ADC1 supply and high reference voltage

VSS_HV_AD1 ADC1 ground and low reference voltage

Analogue to Digital Convertor (ADC)

Hardware Design Guide, Rev. 0, 2012

Freescale Semiconductor, Inc. 9

1uF 10nF

VDD_HV_ADC0

VSS_HV_ADC0

C1 C2

Figure 4. ADC voltage supply connection

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a

capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as

large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it

sources charge during the sampling phase, when the analog signal source is a high-impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC

filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to

be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal

(bandwidth) and the equivalent input impedance of the ADC itself. For more information read MPC560xP datasheet.

Figure 5. Input equivalent circuit

Analogue to Digital Convertor (ADC)

Hardware Design Guide, Rev. 0, 2012

10 Freescale Semiconductor, Inc.

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