NXP Semiconductors PCA9665 Manuel d'exploitation

1. General description

The PCA9665 serves as an interface between most standard parallel-bus

microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus

system to communicate bidirectionally with the I2C-bus. The PCA9665 can operate as a

master or a slave and can be a transmitter or receiver. Communication with the I2C-bus is

carried out on a Byte or Buffered mode using interrupt or polled handshake. The

PCA9665 controls all the I2C-bus speciﬁc sequences, protocol, arbitration and timing with

no external timing element required.

The PCA9665 has the same footprint as the PCA9564 with additional features:

•1 MHz transmission speeds

•Up to 25 mA drive capability on SCL/SDA

•68-byte buffer

•I2C-bus General Call

•Software reset on the parallel bus

2. Features

nParallel-bus to I2C-bus protocol converter and interface

nBoth master and slave functions

nMulti-master capability

nInternal oscillator trimmed to 15 % accuracy reduces external components

n1 Mbit/s and up to 25 mA SCL/SDA IOL (Fast-mode Plus (Fm+)) capability

nI2C-bus General Call capability

nSoftware reset on parallel bus

n68-byte data buffer

nOperating supply voltage: 2.3 V to 3.6 V

n5 V tolerant I/Os

nStandard-mode and Fast-mode I2C-bus capable and compatible with SMBus

nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

nPackages offered: DIP20, SO20, TSSOP20, HVQFN20

PCA9665

Fm+ parallel bus to I2C-bus controller

Rev. 02 — 7 December 2006 Product data sheet

Product data sheet Rev. 02 — 7 December 2006 2 of 91

NXP Semiconductors PCA9665

Fm+ parallel bus to I2C-bus controller

3. Applications

nAdd I2C-bus port to controllers/processors that do not have one

nAdd additional I2C-bus ports to controllers/processors that need multiple I2C-bus ports

nConverts 8 bits of parallel data to serial data stream to prevent having to run a large

number of traces across the entire printed-circuit board

4. Ordering information

Table 1. Ordering information

amb

−

C to +85

Type number Topside

mark Package

Name Description Version

PCA9665BS 9665 HVQFN20 plastic thermal enhanced very thin quad ﬂat package;

no leads; 20 terminals; body 5 ×5×0.85 mm SOT662-1

PCA9665D PCA9665D SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

PCA9665N PCA9665N DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

PCA9665PW PCA9665 TSSOP20 plastic thin shrink small outline package; 20 leads;

body width 4.4 mm SOT360-1

Product data sheet Rev. 02 — 7 December 2006 3 of 91

NXP Semiconductors PCA9665

Fm+ parallel bus to I2C-bus controller

5. Block diagram

Fig 1. Block diagram of PCA9665

SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

I2CDAT – data register – read/write

BUS BUFFER

SDA CONTROL

AA ENSIO STA STO SI

SCL CONTROL

ENSIO STA STO SI

FILTER

PCA9665

SDA

SCL

– – – – – IP2 IP1 IP0

INDPTR – indirect address pointer – write only

ST5 ST4 ST3 ST2 ST1 ST0 0 0

I2CSTA – status register – read only

AA ENSIO STA STO SI MODE

I2CCON – control register – read/write

CLOCK SELECTOR

OSCILLATOR

CONTROL BLOCK

CE WR RD INT RESET A1 A0 VDD

A1 A0

INTERRUPT CONTROL POWER-ON

RESET

D7 D6 D5 D4 D3 D2 D1 D0

data

FILTER

control signals

002aab023

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

INDIRECT – indirect register access – read/write 10

direct registers

AD7 AD6 AD5 AD4 AD3 AD2 AD1 GC

I2CADR – own address – read/write

L7 L6 L5 L4 L3 L2 L1 L0

I2CSCLL – SCL LOW period – read/write

H7 H6 H5 H4 H3 H2 H1 H0

I2CSCLH – SCL HIGH period – read/write

TE BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

I2CTO – TIMEOUT register – read/write

indirect registers

00h

01h

02h

03h

INDPTR

LB BC6 BC5 BC2 BC1 BC0

I2CCOUNT – byte count – read/write

BC4 BC3

IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0

I2CPRESET – software reset register – write only

04h

05h

– –

–AC0

I2CMODE – I2C-bus mode register – read/write

–––––AC1 06h

68-BYTE

BUFFER

Product data sheet Rev. 02 — 7 December 2006 4 of 91

NXP Semiconductors PCA9665

Fm+ parallel bus to I2C-bus controller

6. Pinning information

6.1 Pinning

Fig 2. Pin conﬁguration of SO20 Fig 3. Pin conﬁguration of TSSOP20

Fig 4. Pin conﬁguration of DIP20 Fig 5. Pin conﬁguration of HVQFN20

PCA9665D

VSS

002aab020

i.c.

19 VDD

SDA

SCL

RESET

INT

PCA9665PW

002aab021

VSS

i.c.

VDD

SDA

SCL

RESET

INT

PCA9665N

D0 VDD

D1 SDA

D2 SCL

D3 RESET

D4 INT

D5 A1

D6 A0

D7 CE

i.c. RD

VSS WR

002aab019

002aab022

PCA9665BS

Transparent top view

D5 INT

D4 RESET

D3 SCL

i.c.

VSS

VDD

SDA

5 11

4 12

3 13

2 14

1 15

terminal 1

index area

Product data sheet Rev. 02 — 7 December 2006 5 of 91

NXP Semiconductors PCA9665

Fm+ parallel bus to I2C-bus controller

6.2 Pin description

[1] HVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS

pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and

board-level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board, and for proper heat conduction through the board thermal vias need to be

incorporated in the PCB in the thermal pad region.

Table 2. Pin description

Symbol Pin Type Description

DIP20,

SO20,

TSSOP20

HVQFN20

D0 1 18 I/O Data bus: Bidirectional 3-state data bus used to

transfer commands, data and status between the bus

controller and the CPU. D0 is the least signiﬁcant bit.

D1 2 19 I/O

D2 3 20 I/O

D3 4 1 I/O

D4 5 2 I/O

D5 6 3 I/O

D6 7 4 I/O

D7 8 5 I/O

i.c. 9 6 - internally connected: must be left ﬂoating (pulled

LOW internally)

VSS 10 7[1] power Supply ground

WR 11 8 I Write strobe: When LOW and CE is also LOW, the

content of the data bus is loaded into the addressed

WR or CE.

RD 12 9 I Read strobe: When LOW and CE is also LOW,

causes the contents of the addressed register to be

presented on the data bus. The read cycle begins on

the falling edge of RD.

CE 13 10 I Chip Enable: Active LOW input signal. When LOW,

data transfers between the CPU and the bus

controller are enabled on D0 to D7 as controlled by

the WR, RD and A0 to A1 inputs. When HIGH,

places the D0 to D7 lines in the 3-state condition.

Data are written into the addressed register on rising

edge of either CE or WR.

A0 14 11 I Address inputs: Selects the bus controller’s internal

registers and ports for read/write operations.

A1 15 12 I

INT 16 13 O Interrupt request: Active LOW, open-drain, output.

This pin requires a pull-up device.

RESET 17 14 I Reset: Active LOW input. A LOW level clears internal

registers and resets the I2C-bus state machine.

SCL 18 15 I/O I2C-bus serial clock input/output (open-drain).

This pin requires a pull-up device.

SDA 19 16 I/O I2C-bus serial data input/output (open-drain). This pin

requires a pull-up device.

VDD 20 17 power Power supply: 2.3 V to 3.6 V

Product data sheet Rev. 02 — 7 December 2006 6 of 91

NXP Semiconductors PCA9665

Fm+ parallel bus to I2C-bus controller

7. Functional description

7.1 General

The PCA9665 acts as an interface device between standard high-speed parallel buses

and the serial I2C-bus. On the I2C-bus, it can act either as a master or slave. Bidirectional

data transfer between the I2C-bus and the parallel-bus microcontroller is carried out on a

byte or buffered basis, using either an interrupt or polled handshake.

7.2 Internal oscillator

The PCA9665 contains an internal 28.5 MHz oscillator which is used for all I2C-bus timing.

The oscillator requires up to 550 µs to start-up after ENSIO bit is set to ‘1’.

7.3 Registers

The PCA9665 contains eleven registers which are used to conﬁgure the operation of the

device as well as to send and receive serial data. There are four registers that can be

accessed directly and seven registers that are accessed indirectly by setting a register

pointer.

The four direct registers are selected by setting pins A0 and A1 to the appropriate logic

levels before a read or write operation is executed on the parallel bus.

The seven indirect registers require that the INDPTR (indirect register pointer, one of the

four direct registers described above) is initially loaded with the address of the register in

the indirect address space before a read or write is performed to the INDIRECT data ﬁeld.

For example, in order to write to the indirectly addressed I2CSCLL register, the INDPTR

(A1 = 0, A0 = 0). Then the I2CSCLL register can be programmed by writing to the

INDIRECT data ﬁeld (A1 = 1, A0 = 0) in the direct address space. Register mapping is

described in Table 3,Table 4 and Figure 6.

Remark: Do not write to any I2C-bus registers while the I2C-bus is busy and the PCA9665

is in master or addressed slave mode.

[1] See Section 8.10 “Power-on reset” for more detail.

Table 3. Direct register selection by setting A0 and A1

I2CSTA status 0 0 R F8h

INDPTR indirect register pointer 0 0 W 00h

I2CDAT data 0 1 R/W 00h

I2CCON control 1 1 R/W 00h[1]

INDIRECT indirect data ﬁeld

access 1 0 R/W 00h

Product data sheet Rev. 02 — 7 December 2006 7 of 91

NXP Semiconductors PCA9665

Fm+ parallel bus to I2C-bus controller

Table 4. Indirect register selection by setting A1 = 1 and A0 = 0

I2CCOUNT byte count 00h R/W 01h

I2CADR own address 01h R/W E0h

I2CSCLL SCL LOW period 02h R/W 9Dh

I2CSCLH SCL HIGH period 03h R/W 86h

I2CTO time-out 04h R/W FFh

I2CPRESET parallel software reset 05h W 00h

I2CMODE I2C-bus mode 06h R/W 00h

Fig 6. Register mapping ﬂowchart

002aab459

I2CSTA REGISTER

A1 A0 = 00

read? yes

INDPTR REGISTER

A1 A0 = 00

write? yes

A1 A0 = 10

read/write? yes

INDPTR = 00h

yes I2CCOUNT REGISTER

A1 A0 = 01

read/write?

INDPTR = 01h

yes I2CADR REGISTER

I2CDAT REGISTER

yes

A1 A0 = 11

read/write?

INDPTR = 02h

yes I2CSCLL REGISTER

I2CCON REGISTER

yes

INDPTR = 03h

yes I2CSCLH REGISTER

INDPTR = 04h

yes I2CTO REGISTER

INDPTR = 05h

yes I2CPRESET REGISTER

INDPTR = 06h

yes I2CMODE REGISTER

RESERVED

(write only)

Product data sheet Rev. 02 — 7 December 2006 8 of 91

NXP Semiconductors PCA9665

Fm+ parallel bus to I2C-bus controller

7.3.1 Direct registers

7.3.1.1 The Status register, I2CSTA (A1 = 0, A0 = 0)

I2CSTA is an 8-bit read-only register. The two least signiﬁcant bits are always zero. The

six most signiﬁcant bits contain the status code. There are 30 possible status codes.

When I2CSTA contains F8h, it indicates the idle state and therefore no serial interrupt is

requested. All other I2CSTA values correspond to deﬁned states. When each of these

states is entered, a serial interrupt is requested (SI = 1 and INT asserted LOW).

Remark: Data in I2CSTA is valid only when a serial interrupt occurs (SI = 1 and INT

asserted LOW). Reading the register when SI = 0 and INT is HIGH may cause wrong

values to be read.

7.3.1.2 The Indirect Pointer register, INDPTR (A1 = 0, A0 = 0)

INDPTR is an 8-bit write-only register. It contains a pointer to a register in the indirect

address space (IP[2:0]). The value in the register will determine what indirect register will

be accessed when the INDIRECT register is read or written, as deﬁned in Table 4.

7.3.1.3 The I2C-bus Data register, I2CDAT (A1 = 0, A0 = 1)

I2CDAT is an 8-bit read/write register. It contains a byte of serial data to be transmitted or

a byte which has just been received. In master mode, this includes the slave address that

the master wants to send out on the I2C-bus, with the most signiﬁcant bit of the slave

address in the SD7 bit position and the Read/Write bit in the SD0 bit position. The CPU

can read from and write to this 8-bit register while the PCA9665 is not in the process of

shifting a byte. This occurs when PCA9665 is in a deﬁned state and the serial interrupt

ﬂag is set. Data in I2CDAT remains stable as long as SI is set. Whenever the PCA9665

generates an interrupt, the I2CDAT register contains the data byte that was just

transferred on the I2C-bus.

Table 5. I2CSTA - Status register (A1 = 0, A0 = 0) bit allocation

7 6 5 4 3 2 1 0

ST5 ST4 ST3 ST2 ST1 ST0 0 0

Table 6. I2CSTA - Status register (A1 = 0, A0 = 0) bit description

Bit Symbol Description

7:2 ST[5:0] status code corresponding to the different I2C-bus states

1:0 - always at zero

Table 7. INDPTR - Indirect Register Pointer (A1 = 0, A0 = 0) bit allocation

7 6 5 4 3 2 1 0

- - - - - IP2 IP1 IP0

Table 8. INDPTR - Indirect Pointer register (A1 = 0, A0 = 0) bit description

Bit Symbol Description

7:3 - reserved; must be written with zeroes

2:0 IP2 to IP0 address of the indirect register

Product data sheet Rev. 02 — 7 December 2006 9 of 91

NXP Semiconductors PCA9665

Fm+ parallel bus to I2C-bus controller

In Byte mode, the CPU can read or write a single byte at a time. In Buffered mode, the

CPU can read or write up to 68 bytes at a time. See Section 8.1 “Conﬁguration modes” for

more detail.

Remark: The I2CDAT register will capture the serial address as data when addressed via

the serial bus.

Remark: In Byte mode only, the data register will capture data from the serial bus during

38h (arbitration lost in slave address + R/W or data bytes causing this data in I2CDAT to

be changed), so the I2CDAT register will need to be reloaded when the bus becomes free.

In Buffered mode, the data is not written in the data register when arbitration is lost, which

keeps the buffer intact.

7.3.1.4 The Control register, I2CCON (A1 = 1, A0 = 1)

I2CCON is an 8-bit read/write register. Two bits are affected by the bus controller

hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared

when a STOP condition is present on the I2C-bus. A Write to the I2CCON register via the

parallel interface automatically clears the SI bit, which causes the Serial Interrupt line to

be de-asserted and the next clock pulse on the SCL line to be generated.

Remark: Since none of the registers should be written to via the parallel interface once

the Serial Interrupt line has been de-asserted, all the other registers that need to be

modiﬁed should be written to before the content of the I2CCON register is modiﬁed.

Table 9. I2CDAT - Data register (A1 = 0, A0 = 1) bit allocation

7 6 5 4 3 2 1 0

SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

Table 10. I2CDAT - Data register (A1 = 0, A0 = 1) bit description

Bit Symbol Description

7:0 SD[7:0] Eight bits to be transmitted or just received. A logic 1 in I2CDAT corresponds to

a HIGH level on the I2C-bus. A logic 0 corresponds to a LOW level on the bus.

Table 11. I2CCON - Control register (A1 = 1, A0 = 1) bit allocation

7 6 5 4 3 2 1 0

AA ENSIO STA STO SI - - MODE

Product data sheet Rev. 02 — 7 December 2006 10 of 91

NXP Semiconductors PCA9665

Fm+ parallel bus to I2C-bus controller

Table 12. I2CCON - Control register (A1 = 1, A0 = 1) bit description

Bit Symbol Description

7 AA The Assert Acknowledge ﬂag.

AA = 1: If the AA ﬂag is set, an acknowledge (LOW level on SDA) will be returned

during the acknowledge clock pulse on the SCL line when:

•‘Own slave address’ has been received (as deﬁned in I2CADR register).

•A data byte has been received while the bus controller is in the Master

Receiver mode.

•A data byte has been received while the bus controller is in the addressed

Slave Receiver mode.

AA = 0: if the AA ﬂag is reset, a not acknowledge (HIGH level on SDA) will be

returned during the acknowledge clock pulse on SCL when:

•‘Own slave address’ has been received (as deﬁned in I2CADR register).

•A data byte has been received while the PCA9665 is in the Master Receiver

mode.

•A data byte has been received while the PCA9665 is in the addressed Slave

Receiver mode.

When the bus controller is in the addressed Slave Transmitter mode, state C8h

will be entered after the last data byte is transmitted and an ACK is received from

the Master Receiver (see Figure 10 and Figure 14). When SI is cleared, the

PCA9665 enters the not addressed Slave Receiver mode, and the SDA line

remains at a HIGH level. In state C8h, the AA ﬂag can be set again for future

address recognition.

When the PCA9665 is in the not addressed slave mode, its own slave address is

ignored. Consequently, no acknowledge is returned, and a serial interrupt is not

requested. Thus, the bus controller can be temporarily released from the I2C-bus

while the bus status is monitored. While the bus controller is released from the

bus, START and STOP conditions are detected, and serial data is shifted in.

Address recognition can be resumed at any time by setting the AA ﬂag.

6 ENSIO The bus controller enable bit.

ENSIO = 0: When ENSIO is ‘0’, the SDA and SCL outputs are in a

high-impedance state. SDA and SCL input signals are ignored, the PCA9665 is in

the ‘not addressed’ slave state. Internal oscillator is off.

ENSIO = 1: When ENSIO is ‘1’, the PCA9665 is enabled.

After the ENSIO bit is set to ‘1’, it takes 550 µs enable time for the internal

oscillator to start up and the serial interface to initialize. The PCA9665 will enter

either the master or the slave mode after this time. ENSIO should not be used to

temporarily release the PCA9665 from the I2C-bus since, when ENSIO is reset,

the I2C-bus status is lost. The AA ﬂag should be used instead (see description of

the AA ﬂag above).

In the following text, it is assumed that ENSIO = ‘1’ for Normal mode operation.

For power-up behavior, please refer to Section 8.10 “Power-on reset”.

Table des matières

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