Nexys A7 Manuel utilisateur
12/25/2018 Nexys A7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual 1/30
The Nexys A7 board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable
Gate Array (FPGA) from Xilinx®. With its large, high-capacity FPGA, generous external memories, and collection of USB, Ethernet, and
other ports, the Nexys A7 can host designs ranging from introductory combinational circuits to powerful embedded processors. Several
built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, a speaker amplifier, and several I/O devices
allow the Nexys A7 to be used for a wide range of designs without needing any other components.
(https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-a7/nexys-a7-obl-600.png)
Nexys A7 Reference Manual
12/25/2018 Nexys A7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual 2/30
12/25/2018 Nexys A7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual 3/30
Artix-7 FPGA
15,850 Programmable logic slices, each with four 6-input LUTs and 8 flip-flops (*8,150 slices)
Features
12/25/2018 Nexys A7 Reference Manual [Reference.Digilentinc]
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1,188 Kbits of fast block RAM () (*600 Kbits)
Six clock management tiles, each with phase-locked loop (PLL)
240 DSP slices (*120 DSPs)
Internal clock speeds exceeding 450 MHz ()
Dual-channel, 1 MSPS internal analog-digital converter (XADC)
Memory
128MiB DDR2
Serial Flash
microSD card slot
Power
Powered from USB or any 4.5V-5.5V external power source
USB and Ethernet
10/100 Ethernet PHY
USB-JTAG programming circuitry
USB-UART bridge
USB HID Host for mice, keyboards and memory sticks
Simple User Input/Output
16 Switches
16 LEDs
Two RGB LEDs
Two 4-digit 7-segment displays
Audio and Video
12-bit VGA output
PWM audio output
PDM microphone
Additional Sensors
3-axis accelerometer
Temperature sensor
Expansion Connectors
Pmod connector for XADC signals
Four Pmod connectors providing 32 total FPGA I/O
The Nexys A7 is compatible with Xilinx’s Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. Xilinx
offers free WebPACK™ versions of these toolsets, so designs can be implemented at no additional cost. The Nexys A7 is not supported by
the Digilent Adept Utility.
12/25/2018 Nexys A7 Reference Manual [Reference.Digilentinc]
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(https://reference.digilentinc.com/_detail/reference/programmable-logic/nexys-a7/nexys-a7-callout.png?id=reference%3Aprogrammable-
logic%3Anexys-a7%3Areference-manual)
Figure 1. Nexys A7 Feature Callout
Callout Component Description Callout Component Description
1Power jack 16 JTAG port for (optional) external cable
2Power switch 17 Tri-color (RGB) LEDs
3USB host connector 18 Slide switches (16)
4PIC24 programming port (factory use) 19 LEDs (16)
5Ethernet connector 20 Power supply test point(s)
6FPGA programming done LED () 21 Eight digit 7-seg display
7VGA connector 22 Microphone
8Audio connector 23 External configuration jumper (SD / USB)
9Programming mode jumper 24 MicroSD card slot
10 Analog signal Pmod port (XADC) 25 Shared UART/ JTAG USB port
11 FPGA configuration reset button 26 Power select jumper and battery header
12 CPU reset button (for soft cores) 27 Power-good LED ()
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13 Five pushbuttons 28 Xilinx Artix-7 FPGA
14 Pmod port(s) 29 DDR2 memory
15 Temperature sensor
The Nexys A7 can be purchased with either a XC7A100T or XC7A50T FPGA loaded. These two Nexys A7 product variants are referred to
as the Nexys A7-100T and Nexys A7-50T, respectively. When Digilent documentation describes functionality that is common to both of
these variants, they are referred to collectively as the “Nexys A7”. When describing something that is only common to a specific variant, the
variant will be explicitly called out by its name.
The only difference between the Nexys A7-100T and Nexys A7-50T is the size of the Artix-7 part. The Artix-7 FPGAs both have the same
capabilities, but the XC7100T has about a 2 times larger internal FPGA than the XC750T. The differences between the two variants are
summarized below:
Product Variant Nexys A7-100T Nexys A7-50T
FPGA Part Number XC7A100T-1CSG324C XC7A50T-1CSG324I
Look-up Tables (LUTs) 63,400 32,600
Flip-Flops 126,800 65,200
Block RAM () 1,188 Kb 600 Kb
DSP Slices 240 120
Clock Management Tiles 6 5
The Nexys A7 is a rebrand of the Nexys 4 DDR board, which is an incremental update to the Nexys 4 board.
The only difference between the Nexys A7 and Nexys 4 DDR is the addition of the Nexys A7-50T variant of the Nexys A7, which has a
smaller gate array. The Nexys A7-100T variant is functionally identical to the Nexys 4 DDR.
Users of the Nexys A7 may find resources produced for the Nexys 4 DDR helpful, which can be found at the Nexys 4 DDR's Resource
Center (https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start).
The major improvement from the Nexys 4 to the Nexys 4 DDR is the replacement of the 16 MiB Cellular RAM () with a 128 MiB DDR2
SDRAM memory. Furthermore, to accommodate the new memory, the pin-out of the FPGA banks changed as well.
The audio output (AUD_PWM) needs to be driven open-drain as opposed to push-pull on the Nexys 4.
The Nexys A7 board can receive power from the Digilent USB-JTAG port (J6) or from an external power supply. Jumper JP3 (near the
power jack) determines which source is used.
Purchasing Options
Board Revisions
Migrating from Nexys 4 DDR
Migrating from Nexys 4
Functional Description
1 Power Supplies
12/25/2018 Nexys A7 Reference Manual [Reference.Digilentinc]
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All Nexys A7 power supplies can be turned on and off by a single logic-level power switch (SW16). A power-good LED () (LD22), driven
by the “power good” output of the ADP2118 supply, indicates that the supplies are turned on and operating normally. An overview of the
Nexys A7 power circuit is shown in Figure 1.1.
(https://reference.digilentinc.com/_detail/reference/programmable-logic/nexys-a7/n4d.png?id=reference%3Aprogrammable-logic%3Anexys-
a7%3Areference-manual) Figure 1.1 Nexys A7 Power Circuit
The USB port can deliver enough power for the vast majority of designs. Our out-of-box demo draws ~400mA of current from the 5V
input rail. A few demanding applications, including any that drive multiple peripheral boards, might require more power than the USB port
can provide. Also, some applications may need to run without being connected to a PC’s USB port. In these instances, an external power
supply or battery pack can be used.
An external power supply can be used by plugging into to the power jack (JP3) and setting jumper J13 to “wall”. The supply must use a
coax, center-positive 2.1mm internal-diameter plug, and deliver 4.5VDC to 5.5VDC and at least 1A of current (i.e., at least 5W of power).
Many suitable supplies can be purchased from Digilent, through Digi-Key, or other catalog vendors.
An external battery pack can be used by connecting the battery’s positive terminal to the center pin of JP3 and the negative terminal to the
pin labeled J12, directly below JP3. Since the main regulator on the Nexys A7 cannot accommodate input voltages over 5.5VDC, an external
battery pack must be limited to 5.5VDC. The minimum voltage of the battery pack depends on the application: if the USB Host function
(J5) is used, at least 4.6V needs to be provided. In other cases, the minimum voltage is 3.6V.
Voltage regulator circuits from Analog Devices create the required 3.3V, 1.8V, and 1.0V supplies from the main power input. Table 1.1
provides additional information. Typical currents depend strongly on FPGA configuration and the values provided are typical of medium
size/speed designs.
Table 1.1 Nexys A7 power supplies.
Supply Circuits Device Current (max/typical)
3.3V FPGA I/O, USB ports, Clocks, RAM () I/O, Ethernet, SD slot, Sensors, Flash IC17: ADP2118 3A/0.1 to 1.5A
1.0V FPGA Core IC22: ADP2118 3A/ 0.2 to 1.3A
1.8V DDR2, FPGA Auxiliary and RAM () IC23: ADP2118 0.8A/ 0.5A
The Nexys A7 features overcurrent and overvoltage protection on the input power rail. A 3.5A fuse (R287) and a 5V Zener diode (D16)
provide a non-resettable protection for other on-board integrated circuits, as displayed in Figure 2. Applying power outside of the specs
outlined in this document is not covered by warranty. If this happens, either or both might get permanently damaged. The damaged parts
are not user-replaceable.
1.1 Protection
12/25/2018 Nexys A7 Reference Manual [Reference.Digilentinc]
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After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA
in one of four ways:
1. A PC can use the Digilent USB-JTAG circuitry (portJ6, labeled “PROG”) to program the FPGA any time the power is on.
2. A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.
3. A programming file can be transferred to the FPGA from a micro SD card.
4. A programming file can be transferred from a USB memory stick attached to the USB HID port.
(https://reference.digilentinc.com/_detail/reference/programmable-logic/nexys-a7/n4e.png?id=reference%3Aprogrammable-logic%3Anexys-
a7%3Areference-manual) Figure 2.1 Nexys A7 DDR Configuration Options
Figure 2.1 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP1) and a media selection jumper
(JP2) select between the programming modes.
The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx
can create bitstreams from VHDL, Verilog®, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze™ embedded
processor-based designs).
Bitstreams are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA’s logic functions and circuit connections,
and it remains valid until it is erased by removing board power, by pressing the reset button attached to the PROG input, or by writing a
new configuration file using the JTAG port.
An Artix-7 100T bitstream is typically 30,606,304 bits and can take a long time to transfer. The time it takes to program the Nexys A7 can
be decreased by compressing the bitstream before programming, and then allowing the FPGA to decompress the bitstream itself during
configuration. Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within
the Xilinx tools (ISE or Vivado) to occur during generation. For instructions on how to do this, consult the Xilinx documentation for the
toolset being used. After being successfully programmed, the FPGA will cause the “DONE” LED () to illuminate. Pressing the “PROG”
button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately attempt to reprogram
itself from whatever method has been selected by the programming mode jumpers.
The following sections provide greater detail about programming the Nexys A7 using the different methods available.
The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as
JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port
J6) or an external JTAG programmer, such as the Digilent JTAG-HS2, attached to port J10. You can perform JTAG programming any time
after the Nexys A7 has been powered on, regardless of what the mode jumper (JP1) is set to. If the FPGA is already configured, then the
existing configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG setting (seen in
Figure 3) is useful to prevent the FPGA from being configured from any other bitstream source until a JTAG programming occurs.
Programming the Nexys A7 with an uncompressed bitstream using the on-board USB-JTAG circuitry usually takes around five seconds.
JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the Lab Tools version of
Vivado. The demonstration project available at www.digilentinc.com (http://www.digilentinc.com) gives an in-depth tutorial on how to
program your board.
2 FPGA Configuration
2.1 JTAG Configuration
2.2 Quad-SPI Configuration
12/25/2018 Nexys A7 Reference Manual [Reference.Digilentinc]
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Since the FPGA on the Nexys A7 is volatile, it relies on the Quad-SPI flash memory to store the configuration between power cycles. This
configuration mode is called Master SPI. The blank FPGA takes the role of master and reads the configuration file out of the flash device
upon power-up. To that effect, a configuration file needs to be downloaded first to the flash. When programming a nonvolatile flash device,
a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a circuit that can program flash
devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools).
This is called indirect programming. After the flash device has been programmed, it can automatically configure the FPGA at a subsequent
power-on or reset event as determined by the mode jumper setting (see Figure 3). Programming files stored in the flash device will remain
until they are overwritten, regardless of power-cycle events.
Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory
technology. Once written however, FPGA configuration can be very fast—less than a second. Bitstream compression, SPI bus width, and
configuration rate are factors controlled by the Xilinx tools that can affect configuration speed. The Nexys A7 supports x1, x2, and x4 bus
widths and data rates of up to 50 MHz () for Quad-SPI programming.
Quad-SPI programming can be done using the iMPACT tool included with ISE or the Lab Tools version of Vivado.
You can program the FPGA from a pen drive attached to the USB Host port (J5) or a microSD card inserted into J1 by doing the following:
1. Format the storage device (Pen drive or microSD card) with a FAT32 file system.
2. Place a single .bit configuration file in the root directory of the storage device.
3. Attach the storage device to the Nexys A7.
4. Set the JP1 Programming Mode jumper on the Nexys A7 to “USB/SD”.
5. Select the desired storage device using JP2.
6. Push the PROG button or power-cycle the Nexys A7.
The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are not built for the proper Artix-7
device will be rejected by the FPGA.
The Auxiliary Function Status, or “BUSY” LED (), gives visual feedback on the state of the configuration process when the FPGA is not
yet programmed:
When steadily lit, the auxiliary microcontroller is either booting up or currently reading the configuration medium (microSD or pen
drive) and downloading a bitstream to the FPGA.
A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.
In case of an error during configuration, the LED () will blink rapidly.
When the FPGA has been successfully configured, the behavior of the LED () is application-specific. For example, if a USB keyboard is
plugged in, a rapid blink will signal the receipt of an HID input report from the keyboard.
The Nexys A7 board contains two external memories: a 1Gib (128MiB) DDR2 SDRAM and a 128Mib (16MiB) non-volatile serial Flash
device. The DDR2 modules are integrated on-board and connect to the FPGA using the industry standard interface. The serial Flash is on a
dedicated quad-mode (x4) SPI bus. The connections and pin assignments between the FPGA and external memories are shown below.
The Nexys A7 includes one Micron MT47H64M16HR-25:H DDR2 memory component, creating a single rank, 16-bit wide interface. It is
routed to a 1.8V-powered HR (High Range) FPGA bank with 50 ohm controlled single-ended trace impedance. 50 ohm internal
terminations in the FPGA are used to match the trace characteristics. Similarly, on the memory side, on-die terminations (ODT) are used for
impedance matching.
For proper operation of the memory, a memory controller and physical layer (PHY) interface needs to be included in the FPGA design.
There are two recommended ways to do that, which are outlined below and differ in complexity and design flexibility.
The straightforward way is to use the Digilent-provided DDR-to-SRAM adapter module which instantiates the memory controller and uses
an asynchronous SRAM bus for interfacing with user logic. This module provides backward compatibility with projects written for older
Nexys-line boards featuring a CellularRAM instead of DDR2. It trades memory bandwidth for simplicity.
More advanced users or those who wish to learn more about DDR SDRAM technology may want to use the Xilinx 7-series memory
interface solutions core generated by the MIG (Memory Interface Generator) Wizard. Depending on the tool used (ISE, EDK or Vivado),
the MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect to user logic. This workflow allows the customization of
several DDR parameters optimized for the particular application. Table 3.1 below lists the MIG Wizard settings optimized for the Nexys
A7.
2.3 USB Host and Micro SD Programming
3 Memory
3.1 DDR2
12/25/2018 Nexys A7 Reference Manual [Reference.Digilentinc]
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Table 3.1.1 DDR2 settings for the Nexys A7.
Setting Value
Memory type DDR2 SDRAM
Max. clock period 3000ps (667Mbps data rate)
Recommended clock period (for easy clock generation) 3077ps (650Mbps data rate)
Memory part MT47H64M16HR-25E
Data width 16
Data mask Enabled
Chip Select pin Enabled
Rtt (nominal) – On-die termination 50ohms
Internal Vref Enabled
Internal termination impedance 50ohms
Although the FPGA, memory IC, and the board itself are capable of the maximum data rate of 667Mbps, the limitations in the clock
generation primitives restrict the clock frequencies that can be generated from the 100 MHz () system clock. Thus, for simplicity, the next
highest data rate of 650Mbps is recommended.
The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your
convenience, an importable UCF file is provided on the Digilent website to speed up the process.
For more details on the Xilinx memory interface solutions, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586)¹.
FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number S25FL128S), and mode settings are available to
cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 100T configuration file requires just less
than four MiB (mebibyte) of memory, leaving about 77% of the flash device available for user data. Or, if the FPGA is getting configured
from another source, the whole memory can be used for custom data.
The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is
outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration.
SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA
primitive called STARTUPE2.
NOTE: Refer to the manufacturer’s data sheets² and Xilinx user guides³ for more information.
(https://reference.digilentinc.com/_detail/reference/programmable-logic/nexys-a7/n4f.png?id=reference%3Aprogrammable-logic%3Anexys-
a7%3Areference-manual) Figure 3.2.1 Nexys A7 DDR SPI Flash Pin-out
3.2 Quad-SPI Flash
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