Mesa 4C81 Manuel utilisateur

4C81 MANUAL

Version 2.1

iii

Table of Contents

GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

DESCRIPTION ................................................. 1

HARDWARE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

GENERAL ..................................................... 2

BOOTOPTION ................................................. 2

FPGA/CPLD LVTTL CONNECTOR POWER . . . . . . . . . . . . . . . . . . . . . . . . . . 2

FPGA/CPLD LVTTL OUTPUT VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

NAND FLASH WRITE PROTECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

CONNECTOR AND DEFAULT JUMPER LOCATIONS . . . . . . . . . . . . . . . . . . . 3

POWER/SERIAL CONSOLE CONNECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4C81 SERIAL ADAPTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

FPGA/CPLD LVTTL CONNECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

FPGA/CPLD LVDS CONNECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

ETHERNET CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

JTAG CONNECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

CPU OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SERIAL CONSOLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PC/104-PCI EXPANSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MINI PCI EXPANSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ETHERNET PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

GPIOBITS..................................................... 9

FPGAOPTION ................................................ 10

FPGA/CPU CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

FPGA CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

EXAMPLE FPGA CONFIG FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

P4 PINOUT WITH EXAMPLE FPGA CONFIGURATION . . . . . . . . . . . . . . . . 12

P3 PINOUT WITH EXAMPLE FPGA CONFIGURATION . . . . . . . . . . . . . . . . 13

FPGAPOKE UTILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CPLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CPLD CPU INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

STANDARD CPLD CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

P4 PINOUT WITH STANDARD CPLD CONFIGURATION . . . . . . . . . . . . . . . 15

P3 PINOUT WITH STANDARD CPLD CONFIGURATION . . . . . . . . . . . . . . . 16

CPLD JTAG PINOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table of Contents

SOFTWARE

GENERAL .....................................................17

BOOTLOADER .................................................17

NET BOOT REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

NETBSD SOFTWARE

GENERAL .....................................................19

REMOTE FILE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

BOOT ROM UPDATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

NAND FLASH UPDATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

NETBSD NAND FLASH IMAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

CHANGING NAND FLASH FILESYSTEM MODE . . . . . . . . . . . . . . . . . . . . . . . 21

CHANGING PASSWORDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ENABLING SSHD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

CHANGING PASSWORDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

NETBSD NET BOOT BINARY DISTRIBUTION . . . . . . . . . . . . . . . . . . . . . . . . 22

NETBSD TOOLCHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

LINUX SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

GENERAL .....................................................24

KERNEL BOOT OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SEEPROM.....................................................24

KCMD/NETKCMD ...............................................24

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4C81 MANUAL 1

GENERAL

DESCRIPTION

The 4C81 is a low cost, low power ARM based PC104-PCI CPU. Designed for

networked applications, the 4C81 has two 10/100 baseT Ethernet interfaces and a slot for

a WI-FI card or other Mini-PCI device. The 166 MHz CPU card consumes less than 2 watts

total from a single 5V supply, making Solar powered applications practical.

System resources include 32M or 64M of RAM and 32M or more of NAND Flash

memory, 36 I/O bits provided by either a CPLD or an FPGA and an RS-232 serial port.

PC/104-PCI expansion is provided for up to 2 external bus master cards. The Ethernet

interfaces generates hardware TCP checksums allowing close to wire speed routing

through the 4C81.

An optional on card 200K or 400K gate Spartan3 FPGA with 32 bit local bus

connection provides flexible user I/O or a custom processing accelerator. The FPGA has

36UserI/O pinsavailable, 24singleended LVTTLI/Obitsonastandard50pinheaderwith

interleaved grounds, and 12 I/O bits on a 20 pin 2MM header organized as 6 LVDS pairs

with grounds between pairs.

The 4C81 can run Linux or NetBSD and has a jumper selectable netboot option with

NFS support to allow simple system debug and software development.

4C81 MANUAL 2

HARDWARE CONFIGURATION

GENERAL

Jumper positions are specified with an upright card orientation. The 4C81 is upright

when the top of the card (connector side) faces you, the PC/104-PLUS connector is away

from you and the Ethernet connectors are on the right hand side.

NETBOOT OPTION

The 4C81 can boot from its on card NAND flash or can netboot from a remote NFS

server. This is useful in case the NAND flash becomes corrupted and for initial setup. W8

determines whether the 4C81 boots from the on card NAND flash chip or attempts a

network boot. When W8 is in the right hand position, the 4C81 will boot from NAND flash.

When W8 is in the left hand position the 4C81 will attempt a net boot. Network boot is

always from Ethernet port 0.

FPGA LVTTL VCC

The I/O voltage for the FPGA pins that connect to the LVTTL connector can be user

selected. Jumper W7 selects the I/O voltage. When W7 is in the right hand position, the I/O

voltage is 2.5V. When W7 is in the left hand position, the I/O voltage is 3.3V.

FPGA LVTTL CONNECTOR POWER

The LVTTL connector can supply power to connected daughter cards. This power

can be either 3.3V or 5V. When jumper W9 is in the left hand position, 5V is supplied on pin

49 of the LVTTL I/O connector. When W9 is in the right hand position, 3.3V is supplied on

pin 49.

NAND FLASH WRITE PROTECT

The on card NAND flash can be protected against writes by removing jumper W3.

This will prevent any change of NAND flash contents.

4C81 MANUAL 3

CONNECTORS

CONNECTOR AND DEFAULT JUMPER LOCATIONS

4C81 MANUAL 4

CONNECTORS

SERIAL/POWER CONNECTOR

P1 is the serial console and power connector. Note that the first 6 pins match the

standard DE9 pin male (DTE) serial port pinout used on PC serial ports.

PIN FUNCTION DIRECTION

1 CD TO 4C81

2 DSR TO 4C81

3 RXD TO 4C81

4 RTS FROM 4C81

5 TXD FROM 4C81

6 CTS TO 4C81

7 +5V TO 4C81

8 GND TO 4C81

9 GND TO 4C81

10 +5V TO 4C81

4C81 SERIAL ADAPTER

The 4C81 serial adapter converts the DTE pinout of the 4C81 to DCE for direct

connection to PC type 9 pin serial ports, and also has a 4 pin .1" 5V power connector. The

5V connector on the serial adapter is pinned out as follows:

1 +5V

2 GND

3 GND

4 +5V

4C81 MANUAL 5

CONNECTORS

FPGA/CPLD LVTTL CONNECTOR

P4 is the FPGA/CPLD LVTTL connector. P4 is a 50 pin .1" header. P4 is compatible

with Mesa’s Anything-I/O daughter cards with the restriction that FPGA I/O signals are not

5V tolerant. The CPLD I/O is 5V tolerant.

P4 CONNECTOR PINOUT

P4 PIN FUNC FPGA PIN P4 PIN FUNC FPGA PIN

1 IO0 77 3 IO1 78

5 IO2 79 7 IO3 80

9 IO4 82 11 IO5 83

13 IO6 84 15 IO7 85

17 IO8 86 19 IO9 87

21 IO10 89 23 IO11 90

25 IO12 92 27 IO13 93

29 IO14 95 31 IO15 96

33 IO16 97 35 IO17 98

37 IO18 99 39 IO19 100

41 IO20 102 43 IO21 103

45 IO22 104 47 IO23 105

49 POWER

All even pins are connected to ground.

The POWER pin can be connected to either 3.3V or 5V power depending on the

position of W7.

4C81 MANUAL 6

CONNECTORS

FPGA/CPLD LVDS CONNECTOR

P3 is a 20 pin 2mm header that connects to 12 FPGA I/O pins intended for use as

a LVDS signals. P3 pinout is as follows:

P3 PIN FUNC FPGA PIN P3 PIN FUNC FPGA PIN

1 GND XX 11 LVDS3+ 127

2 LVDS0+ 118 12 LVDS3- 128

3 LVDS0- 119 13 GND XX

4 GND XX 14 LVDS4+ 129

5 LVDS1+ 122 15 LVDS4- 130

6 LVDS1- 123 16 GND XX

7 GND XX 17 LVDS5+ 131

8 LVDS2+ 124 18 LVDS5- 132

9 LVDS2- 125 19 GND XX

10 GND XX 20 +3.3V XX

Note that The DCI (internal termination) feature does not work properly on Rev.A

cards so if the LVDS feature is used, External termination must be supplied. This is fixed

on card rev.B and above. CPLDversions of the 4C81 provide 12 I/O bits onthe LVDS pins.

ETHERNET CONNECTORS

The 4C81 has 2 Ethernet ports. Port 0 and Port 1. Port 0 is the port closest to the

PC/104-PLUSconnector.BothportsarestandardRJ45jacks. Lowprofileunshieldedjacks

are used in order to meet the PC/104 component height specifications.

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