Lucid Technologies MCP6004 Manuel utilisateur
FGEN1
DIGITAL FUNCTION GENERATOR CIRCUIT BOARD
USER’S MANUAL
2023.04.06
Lucid Technologies
http://www.lucidtechnologies.info/
Email: info@lucidtechnologies.info
Copyright © 2023 by Lucid Technologies
All rights reserved
The information in this manual has been carefully checked and is believed to be accurate. However,
Lucid Technologies makes no warranty for the use of its products and assumes no responsibility for
any errors which may appear in this document. Lucid Technologies reserves the right to make
changes in the products contained in this manual in order to improve design or performance and to
supply the best possible product. Lucid Technologies assumes no liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license
under its patent rights, nor the rights of others.
CONTENTS
1.0 Introduction
2.0 Circuit Description
3.0 Software Description
4.0 Operation
5.0 FGEN1 Circuit Board Assembly
6.0 Installation
7.0 Customization
Appendix A FGEN1 Circuit Board Parts List
Appendix B User Supplied Parts
Appendix C Chassis Details
Appendix D RS-232 Serial Interface Connector
Appendix E RS-232 Communications Setup
Appendix F Waveform File Format
Appendix G Filter Bank Specifications
Appendix H Circuit Board Layout
Appendix I Schematics
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FGEN Digital Pulse Generator
1.0 Introduction
The Digital Function Generator (FGEN) is designed to provide arbitrary audio frequency
signals with high resolution. The FGEN can be set to precise values and is as stable as its master
crystal oscillator. The available frequency range is 0.1 Hz to 20 kHz with 0.1 Hz resolution. The
Waveform and Frequency can be controlled via the front panel (two switches and two push-buttons)
or via RS-232. The front panel switches are not active while in Host Mode. Gain and Offset
potentiometers on the front panel are always active. The FGEN can be used for a variety of
applications requiring audio frequency stimulus.
1.1 Specifications
OUTPUT
Output (PCB-J6)
DC coupled, BNC connector, 50 ohms
WAVEFORMS
Fourteen waveforms (00-13) can be permanently stored in onboard EEPROM.
Waveforms can be added or deleted from permanent storage using Host Mode.
Frequency is adjustable from 0.1 Hz to 20 kHz with 0.1 Hz resolution.
MODES
Manual Mode
Waveform selection and Frequency are controlled from front panel switches.
Host Mode
Initiated by connection of RS-232 cable to PCB-J4.
Required for management of waveform files in permanent storage.
Options are selected via a terminal program running on the Host computer.
CONTROLS
Filter bypass toggle switch - bypasses automatic filter bank selection.
Line toggle switch - moves LCD cursor to upper or lower line.
Advance pushbutton - on the Frequency line, it moves the LCD cursor right to the next
numeric character; it has no effect on the Waveform line. The cursor wraps
around to the first numeric character after reaching the right-most numeric
character.
Increment pushbutton - increments the numeric character at the LCD cursor. Numeric values
wrap around from 9 to 0.
Gain potentiometer (PCB-J1) - can vary the gain from 0.85 to 2.0.
Offset potentiometer (PCB-J7) - can vary the offset ±0.83 volts.
POWER
PCB connector J2, 5.5 mm diameter with 2.1 mm diameter center pin, center positive.
External power, 9 volts DC at 100 mA.
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FGEN Digital Pulse Generator
2.0 Circuit Description
This section describes the circuitry on the FGEN1 circuit board.
2.1 Power Supply
Schematic sheet 5 shows the power supply circuitry. The external 9 VDC input goes to two
78M05 linear voltage regulators, U10 and U11. Header SW1 allows the use of a power switch;
otherwise a jumper should be placed at SW1 and connection/disconnection of the external 9 VDC
supply will turn the FGEN1 on/off respectively. The voltage regulators are positioned on the board
so that they can share a common heatsink. U10 supplies power to the digital circuitry while U11
supplies power to the analog circuitry. Analog and digital grounds join at the voltage regulators.
2.2 Microcontroller and Memory
The PIC16F18875 microcontroller, or PIC for short, is designated as U1 on sheet 1 of the
schematics. This 40-pin PIC has 8192 words of flash program memory, 1024 bytes of data memory
(RAM), 256 bytes of EEPROM memory, a 16-bit timer with prescaler (TMR1), an internal clock
Figure 2.0. Block diagram of the FGEN
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oscillator, a universal asynchronous receiver transmitter (UART), a master synchronous serial port,
a numerically controlled oscillator and 36 multi-functional input/output (I/O) lines. Lucid
Technologies’ FGEN firmware is programmed in the PIC’s flash memory.
The 25LC320 chip (U2) is also shown on sheet 1 of the schematics. This is a SPI interface
EEPROM with 32K bits of storage organized as 4K bytes. The EEPROM can store 14 waveform
files numbered 00-13. At power up, the waveform stored in position 00 is output.
There are three places in the FGEN where waveform files may reside:
1. The EEPROM provides nonvolatile storage for waveform files.
2. The Output RAM contains the current waveform file. This will be discussed further in the
Waveform Generation section.
3. The PIC RAM buffers waveform files while they are being moved from one place to another -
such as from the EEPROM to the Output RAM.
2.2.1 Numerically Controlled Oscillator and Clock
The PIC’s Numerically Controlled Oscillator (NCO) is the basis for the FGEN’s frequency
control. The NCO has a 20-bit phase-increment value which is added to the 20-bit phase-
accumulator every NCO clock cycle. Overflows of the phase accumulator generate a pulse on the
NCO output pin. The PIC’s NCO output feeds an 8-bit counter in the waveform generation
circuitry; this makes the effective phase accumulator (the count for one cycle of the output
waveform) 28 bits. The NCO resolution, which is the frequency change when the phase-increment
equals 1 is: Resolution = (NCO_clock) / (2^28). For a resolution of 0.1 Hz the equation becomes:
0.1 * (2^28) = NCO_clock = 26,843,545 Hz. The custom clock oscillator, Y1 on schematic sheet 1,
that feeds the PIC operates at 26.8435 MHz which means the FGEN’s frequency resolution is
approximately 0.1 Hz.
2.3 Waveform Generation
The waveform generation circuitry is shown on sheet 2 of the schematics. The digital portion
of this circuitry is composed of a 74HC4040, ripple counter (U3); a 74HC573, octal transparent
latch with 3-state outputs (U4); and a 6116, 2Kx8 static RAM (U5). Only eight bits of the
74HC4040's twelve outputs are used; this 8-bit count goes through the 256 equally spaced phase
values in one cycle of the output waveform. This phase count continues to rollover, repeating the
periodic output waveform, as long as the NCO output from the PIC is active. Because the
74HC4040 is a ripple counter, its outputs don’t all change simultaneously. The NCO output pulse
increments the 74HC4040 and causes the 74HC573 to latch the last phase count while the
74HC4040 output ripples. At the end of the NCO output pulse the new, stable, phase count is
presented to the 6116 static RAM address lines. Only eight of the 6116's eleven address lines are
used because only 256 memory locations are needed. The 6116 RAM is called the Output RAM.
Even though the 6116 has more memory than needed, it was used because a smaller parallel I/O
static RAM was not available. As the phase count increments, the 256 bytes in the 6116 RAM,
which are the voltage values of the waveform, are sequentially output on the RAM’s eight data pins.
The eight 6116 RAM outputs connect to the R-2R resistor network inputs.
During normal operation the PIC holds the Output RAM in Read-mode with output enabled.
When it comes time to put a new waveform into the Output RAM, the PIC disconnects the NCO
from the NCO output pin, clears the 74HC4040 ripple counter and disables the 6116 output. The
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Figure 2.1
PIC then changes Port-B to output and sequentially presents the new 256 waveform values on Port-
B while incrementing the 74HC4040 ripple counter and toggling the Output RAM’s Write pin.
After the new waveform is written to the Output RAM, Port-
B is returned to a high-impedance input, the Output RAM is
put back in Read-mode with output enabled, and the NCO is
reconnected to the NCO output pin.
Converting the Output RAM’s byte wide output to an
analog signal requires a digital-to-analog-converter, or DAC.
Because the FGEN1 goes to 20 kHz with 256 phase values
per cycle, the DAC needs to operate at 5.12 MHz. Finding an
inexpensive high-speed single-supply 8-bit DAC in a DIP
package was difficult. The few parts available all used
current switches feeding an R-2R network. R-2R networks
are fast, reliable and inexpensive; see:
https://www.electronics-tutorials.ws/combination/r-2r-dac.ht
ml. As it turns out, the CMOS outputs of a 6116 static RAM
make decent current switches; see Figure 2.1. In fact, the
current switches don’t need to be perfect, going from 5V to
0V, as long as all eight span the same range. Thus, it is
possible to use the 6116's outputs as inputs to the R-2R DAC
network. The R-2R network is realized as a thick-film
resistor network in a 10-pin SIP. The R-2R network feeds
inverting amplifier U8.1 which is offset to analog ground -
one-half of the +5 volt analog supply.
2.4 Filter Bank
Schematic sheet 3 shows the filter bank circuitry. The block diagram (Fig. 2.0) shows the
relation of the filter bank to the rest of the FGEN circuitry. Appendix G shows the internal functions
of the filter bank and the design specifications of the filters.
Any DAC output requires some lowpass filtering to remove its “stair step” output. Some
waveforms can be heavily filtered because the waveform itself has low harmonic content - such as a
sine wave. Other waveforms - such as a sawtooth wave - have high order harmonics that, if filtered
out, would distort the desired waveform. To accommodate different filtering requirements, the
FGEN has six second-order Bessel lowpass filters that ratio metrically span the FGEN’s output
range, these are Filter Banks 0-5. The signal from the waveform generation circuitry feeds a six
Filter Banks in parallel. The outputs of Filter Banks 0-5 go to inputs 0-5, respectively, of the
74HC4051 (U9), 8:1 analog multiplexor. The last two inputs to the analog MUX are the unfiltered
waveform, on input 6, and analog ground on input 7.
There is a single order lowpass filter (U8.3), known as the Common Filter, on the output of
the analog MUX.
There are three different quad op-amps used in the Filter Banks and other analog circuitry.
To reduce costs, the gain-bandwidth-product (GBP) of the op-amps was matched to the bandwidth
requirements of the circuitry. The MCP6004 (U6) is used for DC voltages and the lowest frequency
Filter Bank. The MCP604 (U7) is used for the middle frequency Filter Banks. The MCP6024 (U8)
is used for the highest frequency Filter Bank and all op-amps through which the waveform signal
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must pass.
Op-amp type Schematic
designation
Gain-Bandwidth-
Product (GBP)
MCP6004 U6 1 MHz
MCP604 U7 2.8 MHz
MCP6024 U8 10 MHz
2.5 Gain and Offset
The Gain and Offset circuitry is shown on sheet 4 of the schematics. These controls should
both be 10k potentiometers on the front panel, see Appendices B and C for details. These can be
single-turn or multi-turn potentiometers. Section 6 has details on how the potentiometers should be
connected to the FGEN circuit board. The Gain potentiometer should vary the gain from 0.85 to 2.0.
The Offset potentiometer should vary the offset ±0.83 volts. With Gain and Offset it is possible to
drive the output waveform’s peaks or valleys to the +5V or Ground rails respectively. Therefore,
one should always monitor the output waveform to ensure it does not become clipped.
2.6 Front Panel Switches
There are four switches on the front panel; two toggle switches and two pushbuttons. See
Appendices B and C for details. Section 6 has details on how the switches should be connected to
the FGEN circuit board.
2.7 LCD interface
Liquid Crystal Display (LCD) modules compatible with the FGEN1 circuit board are shown
in Appendix B. These two-line by 16-character LCD modules have a 4/8-bit parallel interface with 4
control lines. The FGEN uses the 4-bit parallel interface and treats the LCD module as a write-only
device; this allows the LCD to be controlled with only seven I/O pins. Section 6 has details on how
the LCD should be connected to the FGEN circuit board.
The contrast of the LCD is controlled by potentiometer VR1. The LCD module is
illuminated by LED back-lights. Resistor R29 limits the current to the LED back-lights.
2.8 Host Serial Connector
The RS-232 serial port connector (J4 on schematic sheet 4) is described in detail in
Appendix D. U40 is a MAX232A, 5V-powered RS-232 interface with two drivers and two
receivers. One receiver/driver pair handles RS-232 data to/from the FGEN1. The other
receiver/driver pair receives RTS and sends it back to the host as CTS. RTS is also routed to the
RC0 input on the PIC.
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FGEN Digital Pulse Generator
3.0 Software Description
3.1 Assembler source code
The assembly language code for the standard Digital Function Generator is programmed into
the PIC16F18875 included with the kit. The assembly source code is available upon request. The
source code is well commented and highly modular. If you know PIC assembly language it should
be easy to understand. If you want to learn more about PIC programming and the free Microchip
Assembler (MPASM) consult some of the excellent resources on the Microchip web site.
3.2 Interrupts
No interrupts are used.
3.3 Subroutines
The subroutines are divided into six groups.
1) General Subroutines, such as data conversion; hex to ascii, ascii to hex, delays, etc.
2) UART Subroutines, such as setting baud rates, transmitting and receiving bytes, etc.
3) Synchronous Serial Port Subroutines handle the low level SPI data exchanges.
4) 32-bit Math Subroutines provide 32-bit add, subtract, binary to BCD, and BCD to binary.
5) LCD Module Interface Subroutines format data for display.
6) Function Generator Data Manipulation Subroutines parse ASCII input strings from the
host, keep NCO increment values within valid ranges, and swap waveform data locations.
3.4 Main Program
At power up, the PIC initializes all the on-chip peripherals. It then reads waveform 00 from
the EEPROM into PIC RAM, copies the PIC RAM to the Output RAM, and enables the NCO
output. The output waveform will then continue without further action by the PIC. The LED on the
PCB will blink eight times and the LCD will display the firmware version programmed in the PIC.
The FGEN then enters Manual Mode. It monitors the front panel switches and RTS every 50
milliseconds. If a front panel switch changes the PIC adjusts the LCD and NCO frequency or
waveform accordingly. If RTS goes active the program will jump to Host Mode.
In Host Mode the FGEN sends a menu of options to the Host. Section 4 goes into detail on
how these options function. Front panel switches are not functional in Host Mode; however, the
Gain and Offset controls still work.
3.5 Firmware modifications
Modification of the Digital Function Generator firmware should only be attempted by
someone who is an expert in PIC assembly language programming and possesses a PIC
programmer. That being said, for the knowledgeable, the source code provides well documented
subroutines and examples from which to learn. An easy way to try out new routines is to activate the
debug option on the host communications menu. The debug option in the menu and the jump to the
debug option routine are simply “commented out” in the source code.
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4.0 Operation
When power is applied to the Digital Function Generator the LED on the circuit board will
blink eight times. While the LED is blinking, the LCD display will show “LUCID TECH. Ver.
YYYY.MM.DD"; where YYYY.MM.DD is the date of the firmware version programmed in the
PIC. After four seconds the display will change to the normal display. The waveform stored at
location 00 in the EEPROM will be placed in the Output RAM, and the frequency will be set to
1000 Hz. Assuming a sine wave is stored at 00, the LCD screen should appear as follows:
00 SINE
FREQ 01000.0 Hz
4.1 Manual Mode Operation
The two toggle switches and two pushbuttons are active in Manual Mode. The Line toggle
switch will move the cursor between the waveform number on the top line and the frequency value
on the bottom line. With the cursor on the waveform number, pressing the Increment pushbutton
will change the waveform to the next one available in the EEPROM. With the cursor on one of the
digits in the frequency value on the bottom line, pressing the Increment pushbutton will increase
that digit by one. Incrementing a 9 will change the digit to 0 without affecting any other digit.
Pressing the Advance pushbutton will move the cursor one digit to the right. Advance will skip over
the decimal point and will jump from the tenths of Hz digit to the ten thousand Hz digit. These three
switches (Line, Advance and Increment) allow you to select the desired waveform and frequency.
When active, the Filter Bypass toggle switch tells the PIC to keep the analog MUX set to
input 6 which means the Common Filter is the only filter in the signal path for any waveform
frequency setting. See Appendix G for further information on filtering.
4.2 Host Mode
Host communication mode is entered by connecting an RS-232 cable between FGEN-J4 and
the COM port of a host computer. A terminal program must be operating on the host for
communication with the FGEN (see Appendix E). The FGEN’s RS-232 connection operates at 9600
baud. The FGEN sends the menu screen:
Lucid Technologies
FUNCTION GENERATOR 1
Firmware 2023.01.18
[L]ist waveforms in EEPROM
[U]pload waveform to PIC RAM
[C]opy PIC RAM waveform to output RAM
[S]tore PIC RAM waveform in EEPROM
[D]uplicate EEPROM waveform in PIC RAM
[E]rase waveform from EEPROM
[F]requency
[A]nalog mux
[X] Disconnect from host
[I]nitialize EEPROM chip
? _
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Menu options are selected by typing the corresponding single character, any other entry will
be ignored and the menu will be displayed again.
[L]ist waveforms in EEPROM
This option will list the waveforms stored in the EEPROM as shown below. # is the
waveform number in the EEPROM. The waveform number - which determines the storage location
in EEPROM - is how all waveforms are referenced. Name is the name that will be displayed on the
LCD, Date is the date of creation in the waveform file, and Filter is the filter option in the waveform
file.
? L
# Name Date Filter
00 SINE 2022-08-27 1
01 SQUARE 2022-08-27 2
02 TRIANGLE 2022-08-27 1
03 +SAWTOOTH 2022-08-27 2
04 -SAWTOOTH 2022-08-27 2
10 SINE^2 2022-08-30 1
11 ECG 2022-08-30 1
[U]pload waveform to PIC RAM
This option allows you to upload a waveform file to the PIC RAM. Pressing ESCape before
the upload begins will abort the option and return you to the menu. See Appendix F for details on
the format of waveform files.
? U
Press ESCape to abort.
Begin text file transfer now.
[C]opy PIC RAM waveform to output RAM
This option will copy the waveform from the PIC RAM to the output RAM. The waveform
file will remain in the PIC RAM following the copy. To test an experimental waveform file first
Upload it to PIC RAM then Copy it to output RAM.
? C
ERROR - NO WAVEFORM IN RAM BUFFER! (If PIC RAM is empty)
or
Done. (If waveform file in PIC RAM)
[S]tore PIC RAM waveform in EEPROM
This option will write the waveform file currently in PIC RAM into the desired location
(waveform number) in EEPROM. Pressing escape before the write begins will abort the option and
return you to the menu. The waveform file will remain in the PIC RAM following the write to the
EEPROM. This option will overwrite a file already stored in EEPROM with the same waveform
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