Lauterbach M32R Manuel utilisateur
MANUAL
Release 02.2023
M32R Debugger and Trace
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©1989-2023 Lauterbach
M32R Debugger and Trace
TRACE32 Online Help
TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................
ICD In-Circuit Debugger ................................................................................................................
Processor Architecture Manuals ..............................................................................................
M32R .........................................................................................................................................
M32R Debugger and Trace .................................................................................................. 1
Introduction ....................................................................................................................... 5
Brief Overview of Documents for New Users 5
Demo and Start-up Scripts 5
Warning .............................................................................................................................. 7
Quick Start ......................................................................................................................... 8
Troubleshooting ................................................................................................................ 11
SYStem.Up Errors 11
Memory Access Errors 11
FAQ ..................................................................................................................................... 11
CPU specific SYStem Settings and Restrictions ........................................................... 12
SYStem.CONFIG Configure debugger according to target topology 12
SYStem.CPU Select target CPU 12
SYStem.JtagClock Define JTAG clock 13
SYStem.LOCK Lock and tristate the debug port 13
SYStem.MemAccess Select memory access mode 14
SYStem.Mode Establish the communication with the target 15
SYStem.Option Display SYStem window 15
SYStem.Option.DBI Enables program break via debug interrupt 15
SYStem.Option.IMASKASM Disable interrupts while single stepping 16
SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping 16
SYStem.Option.KEYCODE Code protection 17
SYStem.Option.TriState Allow debugger to drive JTAG and reset 18
SYStem.state Display SYStem.state window 18
Trace specific Commands ................................................................................................ 19
SYStem.Option.BTM Enables program trace messages 19
SYStem.Option.DTM Enables data trace messages 19
SYStem.Option.STALL Trace message overrun control 19
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SYStem.Option.TRCLK Trace output clock ratio 20
SYStem.Option.TRDATA Trace port width 20
TrOnchip ............................................................................................................................ 21
TrOnchip.RESet Resets all TO settings 21
TrOnchip.state Opens configuration panel 22
Security Levels of the M32R Family ................................................................................ 23
Security Level 23
Flash Erase if Device is secured 24
General Restrictions and Hints 25
Floating Point Formats 26
Integer Access Keywords 26
JTAG Connection .............................................................................................................. 27
Mechanical Description of the 10-pin Debug Cable 27
Electrical Description of the 10-pin Debug Cable 27
Mechanical Description of the 20-pin Trace Connector 28
Memory Classes ................................................................................................................ 30
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M32R Debugger and Trace
Version 10-Feb-2023
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©1989-2023 Lauterbach
Introduction
This document describes the processor specific settings and features of the TRACE32 debugger for the
following Renesas M32R CPU families:
• (SDI-3) M32192, M32195, M32196, M32185, M32186
• (SDI-2) M32176, M32180
Please keep in mind that only the Processor Architecture Manual (the document you are reading at the
moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by
Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your
first choice.
If some of the described functions, options, signals or connections in this Processor Architecture Manual are
only valid for a single CPU or for specific families, the names of the families are added in brackets.
Brief Overview of Documents for New Users
Architecture-independent information:
•“Training Basic Debugging” (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
•“T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances
for different configurations of the debugger. T32Start is only available for Windows.
•“General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands.
Architecture-specific information:
•“Processor Architecture Manuals”: These manuals describe commands that are specific for the
processor architecture supported by your Debug Cable. To access the manual for your processor
architecture, proceed as follows:
- Choose Help menu > Processor Architecture Manual.
•“OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating
system-aware debugging. The appropriate OS Awareness manual informs you how to enable the
OS-aware debugging.
Demo and Start-up Scripts
Lauterbach provides ready-to-run start-up scripts for known M32R based hardware.
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To search for PRACTICE scripts, do one of the following in TRACE32 PowerView:
• Type at the command line: WELCOME.SCRIPTS
• or choose File menu > Search for Script.
You can now search the demo folder and its subdirectories for PRACTICE start-up scripts
(*.cmm) and other demo software.
You can also manually navigate in the ~~/demo/m32r/ subfolder of the system directory of TRACE32.
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Warning
WARNING: To prevent debugger and target from damage it is recommended to connect or
disconnect the Debug Cable only while the target power is OFF.
Recommendation for the software start:
1. Disconnect the Debug Cable from the target while the target power is
off.
2. Connect the host system, the TRACE32 hardware and the Debug
Cable.
3. Power ON the TRACE32 hardware.
4. Start the TRACE32 software to load the debugger firmware.
5. Connect the Debug Cable to the target.
6. Switch the target power ON.
7. Configure your debugger e.g. via a start-up script.
Power down:
1. Switch off the target power.
2. Disconnect the Debug Cable from the target.
3. Close the TRACE32 software.
4. Power OFF the TRACE32 hardware.
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Quick Start
Starting up the debugger is done as follows:
1. Select the device prompt for the ICD Debugger and reset the system.
The device prompt B:: is normally already selected in the TRACE32 command line. If this is not the
case, enter B:: to set the correct device prompt. The RESet command is only necessary if you do
not start directly after booting the TRACE32 development tool.
2. Specify the CPU specific settings.
The default values of all other options are set in such a way that it should be possible to work without
modification. Please consider that this is probably not the best configuration for your target.
3. Set up data for electrical interface.
Normally the default value is 10.0 MHz, but the it can be increased up to 25 MHz.
4. Inform the debugger about read only and none-readable address ranges (ROM, FLASH).
The BreakOnchip information is necessary to decide where on-chip breakpoints must be used. On-
chip breakpoints are necessary to set program breakpoints to FLASH/ROM. The sections of FLASH
and ROM depend on the specific CPU and its chip selects. Accesses to invalid addresses can cause
unrecoverable bus errors. To avoid bus errors from the debugger side use the subcommands of MAP
to define inaccessible memory areas. Bus errors can be removed by executing SYStem.Up. Make
sure that there isn’t any TRACE32 window open which accesses to a inaccessible memory that is not
masked out, otherwise the bus error can occur again.
B::
RESet
SYStem.CPU <cpu_type>
SYStem.JtagClock <frequency>
MAP.DenyAccess
MAP.NoDenyAccess <range>
MAP.BOnchip <range>
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5. Enter debug mode.
This command resets the CPU and enters debug mode. After this command is executed, it is possible
to access memory and registers.
6. Configure chip according application.
Before loading binary data into the processor memory, the memory should be made writable for the
debugger. Therefore processor configuration registers have to be set e.g. chip select register.
7. Load the program.
The format of the Data.LOAD command depends on the file format generated by the compiler. It is
recommended to use the option /Verify that verifies all written data. This test discovers a problem with
the electrical connection, wrong chip configurations or linker command file settings.
For a detailed description of the Data.LOAD command and all available options, see “Data” in
“General Commands Reference Guide D” (general_ref_d.pdf).
SYStem.Up
Data.LOAD.SR program.abs /Verify ; SR specifies the format,
; program.abs is the file name
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A typical start sequence for the MSC8101 is shown below. This sequence can be written to a PRACTICE
script file (*.cmm, ASCII format) and executed with the command DO <file>. Other sequences can be found
in the directory ~~/demo/m32r.
*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.
B:: ; Select the ICD device prompt
WinClear ; Clear all windows
SYS.CPU M32196 ; Select CPU
SYS.JC 15000000. ; Choose JTAG frequency
SYStem.Up ; Reset the target and enter debug
; mode
MAP.DENYACCESS ; Forbid any access to the memory in
; general
MAP.BONCHIP 0x0000--0x007FFF
; ROM
; Specifies the program memory where
; on-chip breakpoints must be used
Data.LOAD.SR Sieve.abs /Verify ; Load the application, verify the
; process
Go main ; Run and break at main()
List.Mix ; Open source window *)
Register.view /SpotLight ; Open register window *)
Var.Local ; Open window with local variables *)
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