Lattice Semiconductor LatticeMico32/DSP Manuel utilisateur

October 2007

Revision: EB17_01.4

LatticeMico32/DSP Development Board

User’s Guide

LatticeMico32/DSP Development Board

Lattice Semiconductor User’s Guide

Introduction

This document describes the features and functionality of the LatticeMico32/DSP Development Board. This board

is designed as a hardware platform for design and development with the LatticeMico32 microprocessor, as well as

for the LatticeMico8 microcontroller, and for various DSP functions.

This document describes the numerous functional elements of the board. The schematics of the board can be

found in the appendix at the end of this document.

Features

• LatticeECP™ FPGA with 33,800 LUT4s, 131 kbit of embedded RAM, 4 PLLs, and 360 user I/O pins

• Lattice MachXO™ with 640 LUTs

• Serial Flash with 8 Mbit for non-volatile storage of FPGA conﬁguration data.

• DDR SODIMM socket for DDR SDRAM modules (DDR1, 100-133MHz, 32-bit data bus)

• Parallel Flash 2x128 Mbit, organized as 8M 32-bit words

• SRAM 2x4 Mbit, organized as 256K 32-bit words

• USB 2.0 connector and integrated ispDOWNLOAD

cable for programming the FPGA

• Flywire connector for programming using an ispDOWNLOAD cable (available separately)

• 9-pin RS232 serial port (230 Kbps)

• 15-pin VGA (64 color encoding)

• Ethernet 10/100 M full/half duplex

• Two USB 2.0 compatible host connectors

• One USB 2.0 compatible target connector

• One USB OTG (On-the-Go) connector

• Expansion connector with 46 user I/Os

• 12x12 prototyping area for the integration of individual components (connections to the FPGA)

• 8x6 prototyping area for the integration of individual components (connections to the MachXO)

• Sigma Delta D/A converter

• Crimp connector with 5 signal pairs for high-speed data transfer

• Audio interface (line-in, line-out, and microphone) CODEC

• LCD connector for character displays, with contrast potentiometer

• 25 MHz oscillator with clock distribution buffer

• Eight LEDs with test points for each LED

• Two-character 7-segment display

• Green LED to indicate the proper operation of the 3.3V and 2.5 V power supplies

• Blue LED which shows the conﬁguration status (“DONE”)

• Red LED to signal that the FPGA can be conﬁgured (“INIT”)

• Yellow LED indicating the FPGA PROGRAM# I/O is asserted (“PROGRAM#”)

• 3x4 key matrix

LatticeMico32/DSP Development Board

Lattice Semiconductor User’s Guide

• Four DIP switches

• Single step key

• Program key to initiate the conﬁguration sequence of the FPGA

• Reset key

• 5V power supply

• Switching regulator for the generation of the 3.3V I/O voltage, the 2.5V DDR and LVDS voltages and the 1.2V

core voltage

Getting Started

1. Unpack all components and compare them to the packaging list. All boards leave the factory fully tested.

Detailed information can be found in the Troubleshooting section of this document.

2. Place the board in front of you so that the keyboard is on the left side.

3. Take the regulated DC power supply which has been supplied with the package and connect it to the power

jack on the board. Two green power-on LEDs will illuminate to conﬁrm that power is correctly applied to the

board (regulating 5V to 3.3V and 2.5V).

4. To check the basic functionality, please see the Troubleshooting section of this document.

A number of example and demonstration programs are available for the LatticeMico32/DSP Development board.

Check the Lattice web site at: www.latticesemi.com/boards (and navigate to the correct board) to ﬁnd additional

documentation, and design and programming ﬁles.

Note: Unless described otherwise, positional statements (left, right etc.) refer to the board positioned in front of you

so that the key pad is in the bottom left corner.

Related Literature

•

LatticeMico32 Development Kit User’s Guide

: This guide includes a tutorial for using the LatticeMico32 Sys-

tem software with the LatticeMico32/DSP Development Board.

•

LatticeMico32/DSP Demonstration

: This includes a documented demonstration of a DSP example using the

LatticeMico32/DSP Development board.

These documents can be downloaded from the Lattice web site at: www.latticesemi.com/boards. Select the

FPGA/FPSC Boards -> LatticeMico32/DSP Development board

and click on the

User Manuals

link.

Overview

The following block diagram gives you an overview of the functionality of your LatticeMico32/DSP Development

Board. Subsequent pages illustrate the position of connectors, user interfaces, and modules.

LatticeMico32/DSP Development Board

Lattice Semiconductor User’s Guide

Figure 1. LatticeMico32/DSP Development Board Block Diagram

Table 1. Board Defaults

Peripheral Interfaces

This section describes all peripheral interfaces of the LatticeMico32/DSP Development Board in alphabetical order.

Figure 2 shows the position of peripheral interfaces available on the board.

Item Type

Default

Status Comments

LatticeECP33 FPGA Programmed

The bitstream is based on Example PlatformA and the

LED7SegsTest project. The LED7SegsTest.mem and

LED7SegsTest.bit ﬁles are included in the LED7SegsTest

project.

Visual indications of operation are:

• Left to Right and Right to Left scanning of the 8 LEDs.

• Upcount and roll over of the 7 segment displays from 0 to 99

decimal at ~1 second intervals.

LCD Backlight (X5) Jumper Open Backlight is off.

Conﬁguration Switch TMS Switch Off (Down) LatticeECP33 device can be programmed.

Sigma Delta DAC Converter Jumper Open

Contrast Control Reostat Varible Not set to any speciﬁc level.

4-place DIP - Logic 1 Switch Off Logic 0 on selected pins - see Table 18.

SODIMM DDR 400 Setting (X18) Jumper Shorts Pins

1 and 2 Set to below DDR400 memory use.

LatticeMico32/DSP Development Board

Lattice Semiconductor User’s Guide

Figure 2. Peripheral Interfaces

Audio Interface

The audio interface has two connectors for 3.5 mm stereo jacks. The upper one is for line-out, the lower for line-in.

They are connected to the audio codec TLV320AIC23BIPW from Texas Instruments.

LCD

Contrast

Potentiometer

Microphone

Input

Audio

Line In

Line Out

LCD

Connector

Ethernet

10/100M

3.3V

Testpoint

2.5V

Testpoint

GND

Testpoint

1.2V

Testpoint

CLK

Testpoint

Flywire-

Connector X3

High-Speed

USB for

Configuration

DIP-Switch

for the

Configuration

X13

X12 Expansion

Connector

DDR SDRAM

Socket X4

USB Host

Connector

Mini USB

OTG-Connector

Power PlugRS232

X1A

VGA

X1B

Sigma Delta

DAC Connector

LatticeMico32/DSP Development Board

Lattice Semiconductor User’s Guide

Table 2. Audio Codec U1001 Pin Deﬁnitions

The signal CODEC CS# has a pull-up resistor of 10 k

. The Signal CODEC MODE selects the interface to use for

the codec. Driving it high corresponds to SPI, low to I

Detailed information on the audio codec can be found at the Texas Instruments web site at www.ti.com.

Clock Sources

A 25 MHz oscillator supplies the FPGA (primary clock pin A10 and PLL input V1), the MachXO (pin A8), the Ether-

net controller and the Expansion Connector (pin 29 of X12). The frequency can be measured via testpoint CLK. A

25MHz input clock is required by the Ethernet controller. To generate other clock frequencies, use the PLLs of the

FPGA.You can ﬁnd detailed information for the usage of the PLLs on the Lattice web site and in the LatticeECP/EC

Family Data Sheet.

The USB controller requires a 24 MHz quartz oscillator for conﬁguration. Another 12 MHz quartz supplies the USB

host/peripheral controller.

DDR SODIMM Socket for DDR SDRAM Modules

The board includes a standard DDR1 SODIMM socket with 200 contacts (DDR SDRAM Module is not included).

The upper four bytes of the data bus are not connected. Thus, only half of the capacity of the memory module is

available.

The DDR SODIMM socket is factory conﬁgured to provide a regulated 2.5V. DDR400 modules require a power

supply of 2.6V (±0.1V). To support DDR400, you must short-circuit pins 2 and 3 of connector X18. Position 1-2 is

used for 2.5V mode. If you have your board in front of you so that the power supply is in the upper left corner, pin 1

is the right-most one and is marked with a copper etched triangle

Note:In bank 2, there are four DQSs. Two of them do not have the required DQ pins available. Therefore, only two

DDR interfaces are valid. So, the LatticeECP33 can have a 16-bit DDR interface

Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin

3 CODEC BCLK W1 21 CODEC CS# W4

4 CODEC DIN W2 6 CODEC DOUT W3

5 CODEC LRCIN AA1 7 CODEC LRCOUT Y2

25 CODEC MCLK Y3 24 CODEC SCLK Y1

23 CODEC SDIN AA2 22 CODEC MODE V4

Table 3. DDR SODIMM Socket (X4) - Data Bus, n.c. ... Not Connected

Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin

11 DDR DQS0 A16 47 DDR DQS2 H18

12 DDR DM0 B15 48 DDR DM2 H19

5 DDR DQ0 A14 41 DDR DQ16 D21

7 DDR DQ1 B14 43 DDR DQ17 F20

13 DDR DQ2 A15 49 DDR DQ18 G21

17 DDR DQ3 B16 53 DDR DQ19 G20

6 DDR DQ4 A17 42 DDR DQ20 H20

8 DDR DQ5 B17 44 DDR DQ21 J19

14 DDR DQ6 A18 50 DDR DQ22 J18

18 DDR DQ7 B18 54 DDR DQ23 H17

25 DDR DQS1 D21 61 DDR DQS3 J20

26 DDR DM1 D21 62 DDR DM3 K20

LatticeMico32/DSP Development Board

Lattice Semiconductor User’s Guide

Table 4. DDR SODIMM Socket (X4) - Address Bus

Table 5. DDR SODIMM Socket (X4) - Other Signals

Ethernet Interface

An Intel LXT971A is included for Ethernet PHY. This is an IEEE-compliant Fast Ethernet PHY Transceiver that

directly supports both 100BASE-TX and 10BASE-T applications, full and half duplex. For more information, please

refer to the data sheet of this component.

Table 6. Ethernet Controller U0801 Pin Deﬁnition

19 DDR DQ8 B22 55 DDR DQ24 F22

23 DDR DQ9 B21 59 DDR DQ25 G22

29 DDR DQ10 C21 65 DDR DQ26 H22

31 DDR DQ11 C22 67 DDR DQ27 H21

20 DDR DQ12 E20 56 DDR DQ28 K19

24 DDR DQ13 E18 60 DDR DQ29 K18

30 DDR DQ14 F19 66 DDR DQ30 L18

32 DDR DQ15 F18 68 DDR DQ31 L19

Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin

112 DDR A0 D16 111 DDR A1 C16

110 DDR A2 E15 109 DDR A3 D15

108 DDR A4 C15 107 DDR A5 E14

106 DDR A6 D14 105 DDR A7 C14

102 DDR A8 E13 101 DDR A9 D13

115 DDR A10 E16 100 DDR A11 C13

99 DDR A12 B13 123 DDR A13 C17

117 DDR BA0 E17 116 DDR BA1 D17

Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin

35 DDR CK0+ B12 37 DDR CK0- A12

160 DDR CK1+ A20 158 DDR CK1- B19

96 DDR CKE0 A13 95 DDR CKE1 C12

118 DDR RAS# C18 119 DDR WE# D18

120 DDR CAS# A19 121 DDR S0# C19

Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin

4HPE RESOUT# H6 42 ETH MDIO K4

43 ETH MDC K5 45 ETH RXD3 F2

46 ETH RXD2 G3 47 ETH RXD1 G2

48 ETH RXD0 G1 49 ETH RXDV J4

52 ETH RXCLK K1 53 ETH RXER J5

54 ETH TXER J2 55 ETH TXEN J3

56 ETH TXCLK J1 57 ETH TXD0 H1

58 ETH TXD1 H2 59 ETH TXD2 H3

60 ETH TXD3 H4 62 ETH COL K2

63 ETH CRS K3 64 ETH MDINTR# F1

Table 3. DDR SODIMM Socket (X4) - Data Bus, n.c. ... Not Connected (Continued)

LatticeMico32/DSP Development Board

Lattice Semiconductor User’s Guide

Expansion Connector

The expansion connector provides 46 user I/Os connected to the FPGA. The remaining pins serve as power and

clock supplies for expansion boards. The expansion connector is conﬁgured as two 2x20 100mil centered pin head-

ers (X12 and X13). Tables 7 and 8 describe the connections to the FPGA.

Table 7. Expansion Connector X12

Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin

1 GND — 2 n.c. (coding) —

3 VCC2V5 — 4 EXPCON IO29 W21

5 EXPCON IO30 W20 6 EXPCON IO31 W19

7 EXPCON IO32 Y20 8 EXPCON IO33 AA22

9 EXPCON IO34 AA21 10 EXPCON IO35 AB21

11 EXPCON IO36 T17 12 EXPCON IO37 T14

13 EXPCON IO38 T13 14 EXPCON IO39 U14

15 EXPCON IO40 U13 16 EXPCON IO41 U12

17 EXPCON IO42 U11 18 EXPCON IO43 V14

19 EXPCON IO44 V13 20 EXPCON IO45 W13

21 VCC5V0 — 22 GND —

23 VCC2V5 — 24 GND —

25 VCC3V3 — 26 GND —

27 VCC3V3 — 28 GND —

29 EXPCON OSC — 30 GND —

31 EXPCON CLKIN — 32 GND —

33 EXPCON CLKOUT — 34 GND —

35 VCC3V3 — 36 GND —

37 VCC3V3 — 38 GND —

39 VCC3V3 — 40 GND —

Table 8. Expansion Connector X13

Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin

1HPE RESET# — 2 GND —

3 EXPCON IO0 K22 4 EXPCON IO01 K21

5 EXPCON IO2 L22 6 EXPCON IO03 L21

7 EXPCON IO4 L20 8 EXPCON IO05 M22

9 EXPCON IO6 M21 10 EXPCON IO07 M20

11 EXPCON IO8 M19 12 EXPCON IO09 M18

13 EXPCON IO10 N22 14 EXPCON IO11 N21

15 EXPCON IO12 N20 16 EXPCON IO13 N19

17 EXPCON IO14 N18 18 EXPCON IO15 P22

19 GND — 20 VCC3V3 —

21 EXPCON IO16 P21 22 GND —

23 EXPCON IO17 P20 24 GND —

25 EXPCON IO18 P18 26 GND —

27 EXPCON IO19 P19 28 EXPCON IO20 R22

29 EXPCON IO21 R21 30 GND —

31 EXPCON IO22 R19 32 EXPCON IO23 R18

LatticeMico32/DSP Development Board

Lattice Semiconductor User’s Guide

ispDOWNLOAD Cable Connector

There are two ways to conﬁgure the programmable Lattice devices on the board. The USB connector requires a

standard USB cable, and is described later in this document. Connector X3 is available to connect a Lattice isp-

DOWNLOAD cable. An ispDOWNLOAD cable is used to program IEEE 1532 compliant programmable devices.

Lattice provides either a parallel port or a USB port download cable. The FPGA and CPLD are programmed using

the cable and ispVM

programming software.

DIP switch SW0302

controls the device to be conﬁgured: the FPGA or the MachXO. If it is on (in top position), the

MachXO is selected; if off, the FPGA is selected.

The ispVM System software can be downloaded from the Lattice web site at: www.latticesemi.com/ispvm.

Note: Do not change the switch when the conﬁguration of a device is in progress!

Note: The board as conﬁgured from the factory, has a built-in USB ispDOWNLOAD cable. The built-in cable and an

external ispDOWNLOAD cable cannot be used at the same time.

Table 9. ispDOWNLOAD Connector X3 Pin Deﬁnition

High-Speed LVDS Connector

On the right side of the board there is a 20-pin jack for connecting crimp cables. Five LVDS signal pairs of the

FPGA are wired with the connector (see Table 10). This interface serves as a means for high-speed data transfer.

Figure 3. 20-pin DF13 Connector by Hirose

33 EXPCON IO24 R17 34 GND —

35 EXPCON IO25 T22 36 EXPCON IO26 T18

37 EXPCON IO27 U22 38 CARDSEL# V20

39 EXPCON IO28 V19 40 GND —

1. Caption on the board: CONF.

Pin Signal Name Pin Signal Name

1VCC3V3 2 JTAG_TDO

3 JTAG_TDI 4 JTAG_PROG

5 JTAG_TRST 6 JTAG_TMS

7 GND 8 JTAG_TCK

9 JTAG_DONE 10 JTAG_INIT

Table 8. Expansion Connector X13 (Continued)

LatticeMico32/DSP Development Board

Lattice Semiconductor User’s Guide

Table 10. High-Speed Connector X14 Pin Deﬁnition

LCD Connector (Optional)

The LCD connector is a 16-pin header with a standard pinning for LCD modules with back-light (e.g. Truly MTC-

C202DPRN-1N). In order to use an LCD module, attach it to the connector via a 16-pin ribbon cable.

Note: The LCD module is tied to a 5V supply. The LatticeECP33 to LCD interface is 3.3V.

Put a jumper on connector X5 to turn on the backlight of the LCD. The contrast of the LCD module is adjustable

with the potentiometer R0526, because different LCD modules need different voltages for the best contrast.

Figure 4. LCD Panel (Not Included)

Table 11. LCD Connector X6 Pin Deﬁnition

Serial Interface

The board includes an RS232 serial interface port. The interface provides transmit (TX), receive (RX), and hard-

ware handshaking. The MAXIM MAX3232 data sheet provides detailed information on the interface circuit. A 9-pin

female to 9-pin female null modem cable is required.

Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin

1HSCON DAT0- E21 2 HSCON DAT0+ D22

3 GND — 4 GND —

5 HSCON DAT1- G19 6 HSCON DAT1+ G18

7 GND — 8 GND —

9 HSCON DAT2- F21 10 HSCON DAT2+ E22

11 GND — 12 GND —

13 HSCON DAT3- J22 14 HSCON DAT3+ J21

15 GND — 16 GND —

17 HSCON DAT4- G17 18 HSCON DAT4+ F17

19 GND — 20 GND —

Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin

1GND — 2 VCC5V —

3 CONTRAST — 4 LCD REGSEL P3

5 LCD RW P4 6 LCD ENABLE P5

7 SEG A#/DB0 M3 8 SEG B#/DB1 M4

9 SEG C#/DB2 M5 10 SEG D#/DB3 N1

11 SEG E#/DB4 N2 12 SEG F#/DB5 N3

13 SEG G#/DB6 N4 14 SEG DP#/DB7 N5

15 BACKLIGHT — 16 GND —

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