Lattice Semiconductor SysCLOCK ECP5 Manuel de la liste des pièces

www.latticesemi.com 1TN1263_1.1

November 2015 Technical Note TN1263

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

This usage guide describes the clock resources available in the ECP5TM and ECP5-5GTM device architecture.

Details are provided for primary clocks, edge clocks, PLLs, the internal oscillator, and clocking elements such as

clock dividers, clock multiplexers, and clock stop blocks available in the ECP5 and ECP5-5G device.

The number of PLLs, Edge clocks, and Clock dividers for each device is listed in Table 1.

Table 1. Number of PLLs, Edge Clocks, and Clock Dividers1

It is very important to note that the user needs to validate their pinout so that correct pin placement is used. The

Lattice Diamond®tools should be used to validate the pinout while designing the printed circuit board.

Clock/Control Distribution Network

ECP5 and ECP5-5G devices provide global clock distribution in the form of 16 global primary clocks. These Pri-

mary clocks can be divided into 16 clocks per each of the four quadrants; however there is a maximum of 60 unique

clock input sources. The ECP5 and ECP5-5G primary clocking structure is enhanced as it features more Edge

clock resources, more low-skew Primary clock resources and removes the Secondary clock resources.

Parameter Description LFE5-85 LFE5-45 LFE5-25

Number of PLLs General purpose PLLs. 4 4 2

Number of Edge Clocks Edge Clocks for high speed applica-

tions. 888

Number of Clock Dividers Edge Clock Dividers for DDR applica-

tions. 444

Number of PCS Clock Dividers1Clock dividers for domain crossing appli-

cations. 221

Number of DDRDLLs DDRDLL used to DDR memory and

High Speed IO interfaces 442

1. LFE5U devices do not have PCS Clock Dividers.

ECP5 and ECP5-5G sysCLOCK

PLL/DLL Design and Usage Guide

ECP5 and ECP5-5G sysCLOCK

PLL/DLL Design and Usage Guide

ECP5 and ECP5-5G Top-Level View

A top level view of the major clocking resources for the ECP5 and ECP5-5G devices is shown in Figure 1.

Figure 1. ECP5 and ECP5-5G Clocking Structure (LFE5-85)

Clocking Architecture Overview

Below is a brief overview of the clocking structure, elements, and PLL. Greater detail is provided starting with the

Appendix A. Primary Clock Sources and Distribution section.

Primary Clock Network

Up to 60 Primary Clock Sources (PLLs, External Inputs, SERDES, etc.) can be selected and routed to the Primary

Clock Network. This gives the user an available 60 unique clock domains in the ECP5 and ECP5-5G.

The Primary Clock Network provides low-skew, high fanout clock distribution to all synchronous elements in the

FPGA fabric. The Primary Clock Network is divided into four clocking quadrants: Top Left (TL), Bottom Left (BL),

Top Right (TR), and Bottom Right (BR). Each of these quadrants has 16 clocks that can be distributed to the fabric

in the quadrant. Initially, the Lattice Diamond software automatically routes each clock to all four quadrants; up to a

maximum of 16 clocks since each clock is routed to all four quadrants. The user can change how the clocks are

routed by specifying a preference in the Lattice Diamond software to locate the clock to specific quadrants.

Edge Clock Network

Edge clocks are low skew, high speed clock resources used to clock data into/out of the I/O logic of the ECP5 and

ECP5-5G. There are two edge clocks per bank located on the left and right sides.

Center MUX

Mid

MUX

Mid

MUX

Quadrant TL

Quadrant BL

Quadrant TR

Quadrant BR

GPLL

CLK

DIV

PIOPIOPIOPIO

CLK

DIV

PIO PIO PIO PIO

Edge Clocks

Mid

MUX

Edge Clocks

GPLL

CLK

DIV

PIO PIO PIO PIO

CLK

DIV

Edge Clocks

Mid

MUX

Edge Clocks

SERDES DCU1

Bank 0 Bank 1

Bank 2 Bank 3

Bank 6 Bank 7

PCSCLKDIVPCSCLKDIV

SERDES DCU0

Fabric

Entry

Fabric

Entry

Fabric

Entry

Fabric

Entry

Primary Sources Primary Sources

Primary Sources

Primary

Clocks

Primary

Clocks

Primary

Clocks

Primary

Clocks

Bank 8

14 DCC

12 DCC

16 DCC

Bank 4

GPLL GPLL

Note: LFE4U devices do not have PCS Clock Dividers

ECP5 and ECP5-5G sysCLOCK

PLL/DLL Design and Usage Guide

Overview of Other Clocking Elements

Edge Clock Dividers (CLKDIVF)

Clock dividers are provided to create the divided down clocks used with the I/O Mux/DeMux gearing logic (SCLK

inputs to the DDR) and drives to the Primary Clock routing to the fabric. There are four clock dividers on the ECP5

and ECP5-5G device.

PCS Clock Dividers (PCSCLKDIV)

A new clock divider is provided to create phase-matched divided-down clocks for bus-widening/narrowing circuits.

A port is provided to dynamically change the divide value of the input clock. The PCSCLKDIVwill mainly be used to

slow the clock rate from high speed SERDES applications by providing the clocks for domain crossing circuits.

There is one PCSCLKDIVper SERDES on an LFE5UM device.

Dynamic Clock Select (DCSC)

The ECP5 and ECP5-5G dynamic clock select provides run-time selectable glitchless or non-glitchless operation

between two independent clock sources to the primary clock network. This clock select allows the selection of clock

sources without leaving the dedicated clock resources in the device. There are two dynamic clock select blocks on

the ECP5 and ECP5-5G device.

Edge Clock Bridge with Clock Select (ECLKBRIDGECS)

The ECLKBRIDGECS allows non-glitchless ECLK selection between two ECLKs. The ECLKBRIDGECS will allow

user bridge ECLK from one side to the other. There are two of these elements and they are used for ECLK clock

bridging and ECLK selection.

Edge Clock Stop (ECLKSYNCB)

Each ECLK has a block to allow dynamic stopping of the edge clock. This allows the user to start and stop the

clock synchronous to an event or external signal. These are important for applications requiring exact clock timing

relationships on the inputs, such as DDR memories and video applications.

Oscillator (OSCG)

An internal programmable rate oscillator is provided. The oscillator can be used for master configuration modes

when the FPGA sources the configuration clock, Soft Error Detect (SED), and as a user logic clock source that is

available after FPGA configuration. There is one OSCG on the ECP5 and ECP5-5G device. The oscillator clock

output is routed directly to primary clocking.

The oscillator output is not a high-accuracy clock, having a +/- 15% variation in its output frequency. It is mainly

used for circuits that do not require a high degree of clock accuracy. Examples of usage would be asynchronous

logic blocks such as a timer or reset generator, or other logic that require a constantly running clock.

ECP5 and ECP5-5G sysCLOCK

PLL/DLL Design and Usage Guide

sysCLOCK PLL Overview

The sysCLOCK PLLs can be used in a variety of clock management applications such as clock injection removal,

clock phase adjustment, clock timing adjustment, and frequency synthesis (multiplication and division of a clock).

The ECP5 and ECP5-5G Clarity Designer PLL GUI shows important timing parameters such as the VCO rate and

the PLL loop bandwidth.

PLL Input sources are:

• Dedicated PLL Input Pins

• Primary Clock Routing

• Edge Clock Routing

• FPGA Fabric

Figure 2. ECP5 and ECP5-5G PLL Block Diagram

There are four PLLs on the bigger density devices LFE5-85 and LFE5-45 and two PLLs on the smaller density

LFE5-25 device. There is one PLL on each corner of the device on the bigger density devices and the smaller den-

sity devices have one PLL only on the Lower Left and Lower Right corner. Each PLL has four outputs. All four PLL

outputs can go to the Primary Clock network. Only the CLKOP and CLKOS outputs can go to the ECLK network.

Refclk Divider M Phase

Detector,

VCO, and

Loop Filter

CLKOP

Divider

(1-128)

Lock

Detect

Feedback

Clock Divider

CLK0

CLK1

SEL Refclk

ENCLKOP

CLKOP

CLKOS

CLKOS2

CLKOS3

CLKI

PLLCSOUT

PLLREFCS

VCO

CLKFB

FBKSEL

CLKOS

Divider

(1-128)

CLKOS2

Divider

(1-128)

CLKOS3

Divider

(1-128)

VCO

Internal Feedback

CLKOP, CLKOS, CLKOS2, CLKOS3

RST

STDBY

PHASESTEP

PHASEDIR

PHASESEL[1: 0] Dynamic

Phase

Adjust

PHASELOADREG

LOCK

ENCLKOS

ENCLKOS2

ENCLKOS3

CLKI

CLKI2

ECP5 and ECP5-5G sysCLOCK

PLL/DLL Design and Usage Guide

PLL Features

Dedicated PLL Inputs

The PLLs have dedicated PLL input pins that are not Primary Clock input pins. Each of the Top Left and Right cor-

ner PLLs have two pairs of dedicated PLL input pins, one from the Left/Right side bank and the other from the Top

bank. Either one of these can be used as input to the PLL.

The bottom two PLLs have one pair of dedicated input pin on the Left/Right side banks.

Figure 3. PLL Input Pins for LFE5UM/LFE5UM5G-85 and LFE5UM/LFE5UM5G-45

Figure 4. PLL Input Structure for LFE5-25

Input PLL Clock Selection (PLLREFCS)

The PLLREFCS component is a non-glitchless multiplexor that allows the user to dynamically select between two

PLL input reference clocks. The PLLREFCS has the same input clock sources as the PLL. Since the dedicated

PLL inputs are routed to the input of the PLLREFCS components a user can dynamically select between two exter-

nal reference clock inputs for the top corners of the FPGA. This mux can also be used stand-alone with the PLL in

bypass mode for more clock muxing capabilities.

Clock Injection Delay Removal

The clock injection delay removal feature of the PLL removes the delay associated with the PLL and clock tree.

This feature is typically used to reduce clock to out timing and remove the delay differences between the PLL out-

put clock and the data input. This feature is performed by aligning the input clock with a feedback clock from the

clock tree. Optional delay may also be added to the feedback path to further reduce the clock injection time.

Clock Phase Adjustment

The clock phase adjustment feature of the PLL provides the ability to set a specific phase offset between the out-

puts of the PLL. New to the ECP5 and ECP5-5G device, phase adjustments can be calculated in much finer incre-

ments since the frequency is used to calculate the available phase increments. This feature is detailed further in

the Dynamic Phase Adjustment section.

Quadrant TL

Quadrant BL

Quadrant TR

Quadrant BR

CLKI

PLL0

CLKI

Dedicated External PLL Input 0

PLL0

CLKI

PLL0

CLKI

Dedicated External PLL Input 1

Primary Clock/Edge Clock/Fabric Inputs

Dedicated External PLL Input 0

Primary Clock/Edge Clock/Fabric Inputs

Dedicated External PLL Input 0

Dedicated External PLL Input 1

Primary Clock/Edge Clock/Fabric Inputs

Dedicated External PLL Input 0

Primary Clock/Edge Clock/Fabric Inputs

PLL_BRPLL_BL

PLL_TL PLL_TR

PLL0

Quadrant TL

Quadrant BL

Quadrant TR

Quadrant BR

PLL0

CLKI

PLL0

CLKI

Dedicated External PLL Input 0

Primary Clock/Edge Clock/Fabric Inputs

Dedicated External PLL Input 0

Primary Clock/Edge Clock/Fabric Inputs

PLL_BRPLL_BL

ECP5 and ECP5-5G sysCLOCK

PLL/DLL Design and Usage Guide

Frequency Synthesis

The PLL can be used to multiply up or divide down an input clock.

Additional Features

In addition to the major features, the PLL has several other options that can be used in conjunction with the major

modes.

• A Standby mode to reduce power.

• Smaller phase shift increments are supported, based upon frequency.

Primary Clocks

Primary Clock Sources

The primary clock network has multiple inputs, called primary clock sources, which can be routed directly to the pri-

mary clock routing to clock the FPGA fabric.

The primary clock sources that can get to the primary clock routing are:

• Dedicated Clock Input Pins

• PLL Outputs

•CLKDIVOutputs

• Internal FPGA Fabric Entries (with minimum general routing)

• SERDES/PCS/PCSDIVclocks

• OSC Clock

All potential primary clock sources are multiplexed prior to going to the primary clock routing by a mid-mux. There

are 56 mid-mux connections and four FPGA fabric connections, 60 total, routed to a multiplexor in the center of the

chip called the centermux. From the centermux primary clocks are selected and distributed to the FPGA fabric. The

maximum number of unique clock sources is 16 bottom mid-mux sources + 12 top mid-mux sources + 14 left mid-

mux sources + 14 right mid-mux sources + 4 direct FPGA fabric entry points (from general routing) = 60. The basic

clocking structure is shown in Figure 1 and elaborated in Appendix A. Primary Clock Sources and Distribution.

Primary Clock Routing

The primary clock routing network is made up of low skew clock routing resources with connectivity to every syn-

chronous element of the device. Primary clock sources are selected at the mid-mux, then selected in the center-

mux and distributed on the primary clock routing to clock the synchronous elements in the FPGA fabric.

The primary clock routing network is divided into four sections, called quadrants. Figure 5 is a simplified view of

Figure 1.

ECP5 and ECP5-5G sysCLOCK

PLL/DLL Design and Usage Guide

Figure 5. Primary Clock Routing Architecture

The centermux can source up to 16 independent primary clocks per quadrant which can clock the logic located in

that quadrant. The centermux can also route each clock source to all quadrants. The Diamond software will auto-

matically route a primary clock to all four quadrants in the FPGA.

Dedicated Clock Inputs

The ECP5 and ECP5-5G device has dedicated pins, called PCLK pins, to bring an external clock source into the

FPGA and allow them to be used as FPGA primary clocks. These inputs route directly to the Primary clock net-

work, or to Edge clock routing resources. A dedicated PCLK clock pin must always be used to route an external

clock source to FPGA logic and I/O.

If an external input clock is being sourced to a PLL, then in most cases the input clock should use a dedicated PLL

input pin. SERDES reference clocks also have dedicated SERDES reference clock pins. The ECP5 and ECP5-5G

device allows a PLL reference clock or a SERDES reference clock to come from an external Primary Clock (PCLK)

pin and route through the Primary clock network to drive the reference clock to the SERDES or the input of a PLL.

PCS Clock Dividers (PCSCLKDIV)

The ECP5 and ECP5-5G device has a new clock divider called the PCSCLKDIV. The PCSCLKDIVis built with our

PCS / IP Core interaction in mind. Its main purpose is to allow our IP cores to do multi-rate clocking for cores that

can change data rates. The specific features are:

• Capability to generate different divider clocks

• Input mux to change the divider value on-the-fly.

• Non-glitchless when the divider’s select mux input is changed.

• Data width changes in the fabric for widening / narrowing circuits. This element must allow clock domain crossing

in the fabric registers.

Center MUX

Quadrant TL

Quadrant BL

Quadrant TR

Quadrant BR

Mid

MUX

Fabric

Entry

Fabric

Entry

Fabric

Entry

Fabric

Entry

Primary Clock Routing to Fabric Resources in

TR Quadrant of the FPGA

Primary Clock Routing to Fabric Resources in

TL Quadrant of the FPGA

Primary Clock Routing to Fabric Resources in

TL Quadrant of the FPGA

Primary Clock Routing to Fabric Resources in

TL Quadrant of the FPGA

Mid

MUX

Mid

MUX

Mid

MUX

Primary Clock Sources Into the Mid-Mux

Primary Clock

Sources

Into the Mid-Mux

Primary Clock

Sources

Into the Mid-Mux

ECP5 and ECP5-5G sysCLOCK

PLL/DLL Design and Usage Guide

There is one PCSCLKDIVper SERDES Channel on the bottom of the device where the SERDES blocks are

located. The clock outputs of the PCSCLKDIV(CDIV1, CDIVX) are delay and phase matched to each other and

has a run-time selectable divider value. The PCSCLKDIVclock input sources are:

• Up to four TX Channel Clocks

• Up to four RX Channel Clocks

• Clock from Routing

Figure 6. PCSCLKDIV Connection Diagram

The output PCS channel clocks route directly to the input of the PCSCLKDIVwithout requiring the use of a primary

clock. The CDIV1 and CDIVX outputs route directly to the primary clock routing. Its function is to do bus widening /

narrowing circuits in the FPGA fabric to reduce the fabric frequency. The PCSCLKDIVis not suitable for DDR I/O

interfaces (ECLK to SCLK domain crossing).

Figure 7. Logical Functional Timing of PCSCLKDIV Block

Clock from routing

4 TX Channel Clocks

4 RX Channel Clocks

RST

SEL[2:0]

PCSCLKDIV

/1,/2,/4,/5,/8or /10

Primary Clocks

Mid MUX

CLKI

RST

CDIV_1

CDIV_2

CDIV_4

CDIV_5

CDIV_8

CDIV_10

De-asserted RST

is registered

Asserted RST

is asynchronized

Delayed output

clocks start

toggling

ECP5 and ECP5-5G sysCLOCK

PLL/DLL Design and Usage Guide

An example design is shown in Figure 8. It is a flip-flop based clock domain crossing circuit between the CDIV1 and

the CDIVX = 2 clock outputs of the PCSCLKDIV. In this example an IP core is using the PCSCLKDIVto change the

operating frequency and bus width for a PCS (SERDES) application.

Figure 8. PCSCLKDIV Example Usage

PCSCLKDIV Component Definition

The PCSCLKDIVcomponent can be instantiated in the source code of a design as defined in this section. Figure 9,

Table 2 and Table 3 define the PCSCLKDIVcomponent. Verilog and VHDL instantiations are included.

Figure 9. PCSCLKDIV Component Symbol

Table 2. PCSCLKDIV Component Port Definition

Table 3. PCSCLKDIV Component Attribute Definition

Port Name I/O Description

CLKI I Clock Input.

RST I Reset input – Active High, Asynchronously forces all outputs low.

—RST = 0 Clock output outputs are active

—RST = 1 Clock output outputs are OFF

SEL(2:0) I Signals are used for dynamically changing divide value.

—SEL = 000, Output = ‘0’

—SEL = 001, ÷1

—SEL = 010, ÷2

—SEL = 011, ÷4

—SEL = 100, ÷5

—SEL = 101, ÷8

—SEL = 110, ÷10

—SEL = 111, Output = ‘0’

CDIV1 O Output is the same frequency as the input clock. Delay matched to CDIVX.

CDIVX O Divide by 1, 2, 4, 5, 8, 10 Output Port

Name Description Value Default

GSR Enable or Disable Global Reset Signal to Component ENABLED, DISABLED DISABLED

PCS

rxdata_0

TX_Full_Clk

rxiclk

FF FF

PCSCLK

DIV

8-bit

Data

8-bit

Data

16-bit

Data

CLKI

CLKDIVX = ‘2’

CDIV1

FF FF

8-bit

Data

8-bit

Data

16-bit

Data

SEL

txiclk

txdata_0

Core

PCSCLKDIV

CLKI

RST CDIV 1

CDIVX

SEL (2 :0 )

ECP5 and ECP5-5G sysCLOCK

PLL/DLL Design and Usage Guide

PCSCLKDIV Usage in VHDL

Component Instantiation

Library lattice;

use lattice.components.all;

Component and Attribute Declaration

component PCSCLKDIV

Generic (GSR : string);

Port (RST : in STD_LOGIC;

CLKI : in STD_LOGIC;

SEL : in STD_LOGIC_VECTOR(2 downto 0);

CDIV1 : in STD_LOGIC;

CDIVX : out STD_LOGIC);

end component;

PCSCLKDIV Instantiation

attribute GSR : string;

attribute GSR of I1 : label is “DISABLED”;

I1: PCSCLKDIV

generic map (

GSR => “DISABLED”)

port map (

RST => RST

,CLKI => CLKI

,SEL => SEL

,CDIV1 => CDIV1

,CDIVX => CDIVX);

PCSCLKDIV Usage in Verilog

Component and Attribute Declaration

module PCSCLKDIV (RST, CLKI, SEL, CDIV1, CDIVX);

parameter GSR = “DISABLED”;// “ENABLED”, “DISABLED”

input RST, CLKI;

input [2:0] SEL;

output CDIVX;

endmodule

PCSCLKDIV Instantiation

defparam I1.GSR = “DISABLED”;

PCSCLKDIV I1 (

.RST (RST)

,.CLKI (CLKI)

,.SEL (SEL)

,.CDIV1 (CDIV1)

,.CDIVX (CDIVX));

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