Keysight Technologies D9020DDRC Manuel utilisateur

Keysight D9020DDRC

DDR2(+LP) Compliance Test

Application

Methods of

Implementation

2 DDR2(+LP) Compliance Testing Methods of Implementation

Notices

No part of this manual may be reproduced in

any form or by any means (including elec-

tronic storage and retrieval or translation

into a foreign language) without prior agree-

ment and written consent from Keysight

Technologies as governed by United States

and international copyright laws.

Manual Part Number

D9020DDRC-97006

Software Version

1.27.0000

Edition

June 2019

Printed in Malaysia

Keysight Technologies.

1900 Garden of the Gods Road

Colorado Springs, CO 80907 USA

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NOTICE, IN FUTURE EDITIONS. FURTHER,

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applicable in any technical data.

Safety Notices

CAUTION

A CAUTION notice denotes a hazard. It

calls attention to an operating proce-

dure, practice, or the like that, if not

correctly performed or adhered to,

could result in damage to the product

or loss of important data. Do not pro-

ceed beyond a CAUTION notice until

the indicated conditions are fully

understood and met.

WARNING

A WARNING notice denotes a hazard.

It calls attention to an operating pro-

cedure, practice, or the like that, if not

correctly performed or adhered to,

could result in personal injury or

death. Do not proceed beyond a

WARNING notice until the indicated

conditions are fully understood and

met.

DDR2(+LP) Compliance Testing Methods of Implementation 3

DDR2 —Quick Reference

Table 1 DDR2 Cycles and Signals

NOTE: 1 = Single Ended signal; 2 = Differential signal; 3 = 2 x Single Ended signal

TEST Cycle Based on Test Definition Required Connection Type to Perform

Test on Scope

Opt.

Read Write DQ DQS CK ADD Ctrl Data

Mask

Ctrl

DQ DQS CK ADD Ctrl Data

Mask

Ctrl

CS#

tJIT(per)    

tJIT(cc)    

tERR(nper)    

tCH(avg)    

tCL(avg)    

tJIT(duty)    

tCK(avg)    

VIH(ac)         

VIH(dc)         

VIL(ac)         

VIL(dc)         

SlewR         

SlewF         

Overshoot

        

Undershoot

        

VID(ac)    

VIX(ac)    

VOX(ac)   

tAC      

tDQSCK      

tHZ(DQ)      

tLZ(DQS)      

tLZ(DQ)      

4 DDR2(+LP) Compliance Testing Methods of Implementation

TEST Cycle Based on Test Definition Required to Perform on Scope Opt.

Read Write DQ DQS CK ADD Ctrl Data

Mask

Ctrl

DQ DQS CK ADD Ctrl Data

Mask

Ctrl

CS#

tDQSQ    

tQH    

tDQSS      

tDQSH    

tDQSL    

tDSS      

tDSH      

tWPST    

tWPRE    

tRPRE    

tRPST    

tDS(base)    

tDH(base)    

tDS1(base)    

tDH1(base)    

tIS(base)      

tIH(base)      

Eye

Diagram -

Read

   

Eye

Diagram -

Write

   

Table 1 DDR2 Cycles and Signals

NOTE: 1 = Single Ended signal; 2 = Differential signal; 3 = 2 x Single Ended signal

DDR2(+LP) Compliance Testing Methods of Implementation 5

DDR2(+LP) Compliance Test Application — At A Glance

The Keysight D9020DDRC DDR2(+LP) Compliance Test Application is a DDR2 (Double Data Rate 2)

test solution that covers electrical, clock and timing parameters of the JEDEC (Joint Electronic

Device Engineering Council) specifications. The software helps you in testing all the un-buffered

DDR2 DUTs (devices under test) compliance, with the Keysight 9000, 90000 series, and UXR series

Infiniium digital storage oscilloscope.

There are 2 main categories of test modes:

• Compliance Tests - These tests are based on the DDR2 JEDEC compliance specifications and are

compared to corresponding compliance test limits.

• Custom Mode Tests - These tests are not based on any compliance specification. The primary use

of these tests is to perform non-JEDEC specific speed signal testing.

The DDR2(+LP) Compliance Test Application:

• Lets you select individual or multiple tests to run.

• Lets you identify the device being tested and its configuration.

• Shows you how to make oscilloscope connections to the device under test.

• Automatically checks for proper oscilloscope configuration.

• Automatically sets up the oscilloscope for each test.

• Allows you to determine the number of trials for each test, with the new multi trial run capability.

• Allows you to customize the test limits in the application which determines the pass or/and fail of

each test.

• Provides detailed information of each test that has been run. The result of maximum twenty five

worst trials can be displayed at any one time.

• Creates a printable HTML report of the tests that have been run.

The minimum number of probes required for the tests are:

• Clock tests - 1 probe.

• Electrical tests - 3 probes.

• Clock Timing tests - 3 probes.

• Custom Mode tests - 3 probes.

DDR2 SDRAM electrical, clock and timing test standards and specifications are described in the

JESD79-2E and JESD208 document. For more information, please refer to JEDEC web site at

www.jedec.org.

NOTE

The tests performed by the DDR2(+LP) Compliance Test Application are intended to provide a quick

check of the physical layer performance of the DUT. These testing are not replacement for an

exhaustive test validation plan.

6 DDR2(+LP) Compliance Testing Methods of Implementation

Required Equipment and Software

In order to run the DDR2 automated tests, you need the following equipment and software:

• The minimum version of Infiniium oscilloscope software (see the D9020DDRC DDR2(+LP) test

application release notes)

• Use one of the following oscilloscope models:

• Keysight DSO9000A-Series, DSO90000A-Series, and DSOX90000A/Q/Z/V-Series

Oscilloscopes with a minimum bandwidth of 8 GHz (recommended) for accurate

measurements. For faster speed grade devices, a minimum bandwidth of 13 GHz

bandwidth is recommended.

• Keysight UXR Oscilloscopes

• D9020DDRC DDR2(+LP) Compliance Test Application, version 1.27 or higher

• RAM reliability test software

• 1169A, 1168A, 1134A, 1132A, or 1131A InfiniiMax probe amplifiers

• N5381A or E2677A differential solder-in probe head, N5382A or E2675A differential browser

probe head, N5425A ZIF probe head with N5426A or N5451A ZIF tip accessories, E2678A

differential socketed probe head

• Any computer motherboard system that supports DDR2 memory

• Keyboard, qty = 1, (provided with the Keysight Infiniium oscilloscope)

• Mouse, qty = 1, (provided with the Keysight Infiniium oscilloscope)

Below are the required licenses:

• D9020DDRC DDR2(+LP) Compliance Test Application license

• N5414A InfiniiScan software license

• E2688A Serial Data Analysis and Clock Recovery software license

• N5404A Deep memory option (optional)

DDR2(+LP) Compliance Testing Methods of Implementation 7

In This Book

This manual describes the tests that are performed by the DDR2(+LP) Compliance Test Application in

more detail; it contains information from (and refers to) the JESD79-2E and JESD208, and it

describes how the tests are performed.

•Chapter 1, “Installing the DDR2(+LP) Compliance Test Application"” shows how to install and

license the automated test application software (if it was purchased separately).

•Chapter 2, “Preparing to Take Measurements" shows how to start the DDR2(+LP) Compliance

Test Application and gives a brief overview of how it is used.

•Chapter 3, “Measurement Clock Tests" describes the measurement clock tests including clock

period jitter, clock to clock period jitter, cumulative error, average HIGH and LOW pulse width,

half period jitter and average clock period tests.

•Chapter 4, “Single-Ended Signals AC Input Parameters Tests" shows how to run the

single-ended signals AC input parameters tests. This chapter includes input signal maximum

peak to peak swing tests, input signal minimum slew rate (rising) tests, input signal minimum

slew rate (falling) tests, input logic HIGH tests and input logic LOW tests.

•Chapter 5, “Single-Ended Signals VIH/VIL (Address, Control) Tests" describes the AC/DC input

logic high/low tests (address, control).

•Chapter 6, “Single-Ended Signals VIH/VIL (Data, Mask) Tests" describes the AC/DC input logic

high/low tests (data, mask).

•Chapter 7, “Single-Ended Signals AC Parameters Tests for Strobe Signals" describes the VSEH(AC)

and VSEL(AC) tests for strobe signals.

•Chapter 8, “Single-Ended Signals AC Parameters Tests for Clock" describes the VSEH(AC) and

VSEL(AC) tests for clocks.

•Chapter 9, “Single-Ended Signals Overshoot/Undershoot Tests" describes the AC overshoot and

undershoot tests probing and method of implementation.

•Chapter 10, “Differential Signals AC Input Parameters Tests" describes the VID AC differential

input voltage tests and VIX AC differential cross point voltage tests. The VIHdiff and VILdiff tests for

both AC and DC are also described.

•Chapter 11, “Differential Signal AC Output Parameters Tests" contains information on the VOX AC

differential cross point voltage tests. It also describes the SRQdiffR (40 and 60 ohm), SQRdiffF

(40 and 60 ohm), VOHdiff(AC), and VOLdiff(AC) tests.

•Chapter 12, “Differential Signal Clock Cross Point Voltage Tests" describes the VIXCA Clock Cross

Point Voltage test.

•Chapter 13, “Differential Signals Strobe Cross Point Voltage Tests" describes the VIXDQ Strobe

Cross Point Voltage test.

•Chapter 14, “Clock Timing (CT) Tests" describes the clock timing operating conditions of

DDR2/LPDDR2 SDRAM as defined in the specification.

•Chapter 15, “Data Strobe Timing (DST) Tests" describes various data strobe timing tests

including tHZ(DQ), tLZ(DQS), tLZ(DQ), tDQSQ, tQH, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST,

tWPRE, tRPRE, tRPST, tHZ(DQ) Low Power, tHZ(DQS) Low Power, tLZ(DQS) Low Power, tLZ(DQ)

Low Power, tQSH, tQSL, tDQSS, and tDVAC (Strobe) tests.

•Chapter 16, “Data Timing Tests" describes the measurement clock tests including clock period

jitter, clock to clock period jitter, cumulative error, average HIGH and LOW pulse width, half

period jitter and average clock period tests.

•Chapter 17, “Command and Address Timing (CAT) Tests" describes the measurement clock tests

including clock period jitter, clock to clock period jitter, cumulative error, average HIGH and LOW

pulse width, half period jitter and average clock period tests.

•Chapter 18, “Custom Mode Read-Write Eye-Diagram Tests" describes the user defined real-

time eye- diagram test for read cycle and write cycle.

•Chapter 19, “Calibrating the Infiniium Oscilloscope and Probe" describes how to calibrate the

oscilloscope in preparation for running the DDR2(+LP) automated tests.

8 DDR2(+LP) Compliance Testing Methods of Implementation

•Chapter 20, “InfiniiMax Probing" describes the probe amplifier and probe head recommendations

for DDR2(+LP) testing.

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