JRC NJU6676 Manuel utilisateur

NJU6676

Ver.2004-03-01

-1-

64-common X 132-segment + 1-icon common

Bit Map LCD Driver

■GENERAL DESCRIPTION ■PACKAGE

The NJU6676 is a bit map LCD driver to display

graphics or characters. It contains 8,580 bits display

data RAM, microprocessor interface circuits,

instruction decoder, 132-segment drivers, 64-common

drivers and 1-icon common driver.

The bit image display data is transferred to the

display data RAM by serial or 8-bit parallel interface.

65 x 132 dots graphics or 8-character 4-line by 16 x

16 dots character with icon are displayed by NJU6676

itself.

The wide operating voltage from 2.2 to 5.5V and low

operating current are useful for small size battery

operating items.

The build-in Electrical Variable Resistance is very

precision, furthermore the rectangle outlook is very

applicable to COG or Slim TCP.

■FEATURES

●Direct Correspondence between Display Data RAM and LCD Pixel

●Display Data RAM - 8,580 bits

●197 LCD Drivers - 64-common and 132-segment + 1-icon common

●Direct Microprocessor Interface for both of 68 and 80 type MPU

●Serial Interface

●Programmable Bias selection ; 1/7,1/9 bias

●Useful Instruction Set

Display ON/OFF Cont, Display Start Line Set, Page Address Set, Column Address Set, Status Read,

Display Data Read/Write,ADC Select, Inverse Display,All On/Off, Bias Select, Read Modify Write,

End, Reset, Common Driver orderAssignment, Power control set, Driver On/Off, EVR Mode Set,

EVR Register Set, Static Indicator On/Off, Static Indicator Register Set, Power Saving.

●Power Supply Circuits for LCD Incorporated

Voltage Booster Circuits (4-time Maximum), Regulator, Voltage Follower x 4

●Precision Electrical Variable Resistance (64-step)

●Low Power Consumption 80uA(Typ.).

●Operating Voltage (All the voltages are based on VDD=0V.)

- Logic Operating Voltage : -2.2V ∼-5.5V

- Voltage Booster Operating Voltage : -2.5V ∼

- LCD Driving Voltage : -6.0V ∼-18.0V

●Rectangle outlook for COG

●Package Outline : Bump-chip

●C-MOS Technology (Substrate : N)

NJU6676CL

NJU6676

Ver.2004-03-01

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■PAD LOCATION

COMM

OSC2

VSS2

VDD

RD(E)

D6(SCL)

VDD

D7(SI)

VDD

VSS

VSS2

VOUT

C3-

VOUT

C3-

C1+

C1-

C2-

C1-

C2-

C2+

VSS

VDD

VSS

VDD

CLS

M/S

VSS

P/S

C86

VDD

VSS

S130

S131

C31

C30

VSS

DOF

CS1

VDD

CS2

RES

VSS

WR(R/W)

FRS

OSC1

DUMMY4

DUMMY2

DUMMY3

DUMMY1

COMM

C63

C32

C33

Chip Center : X=0um, Y=0um

Chip Size

:X=8.72mm,Y=2.37mm

Chip Thickness : 675um ±30um

Bump Size

: 45um x 83um

Bump Pitch : 60um(Min.)

Bump Height : 15um(Typ.)

Bump Material : Au

Voltage Boosting Polarity

: Negative Voltage (VDD common)

Substrate : N

Ver.2004-03-01

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NJU6676

■PAD COORDINATES

Chip Size 8.72 x 2.37mm(Chip Center X=0um, Y=0um)

PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um)

1 DUMMY1 -4139 -1025 51 VDD 1655 -1025

2 OSC1 -3347 -1025 52 VDD 1715 -1025

3 OSC2 -3287 -1025 53 V1 1775 -1025

4 FRS -3129 -1025 54 V1 1835 -1025

5 FR -2909 -1025 55 V2 1895 -1025

6 CL -2688 -1025 56 V2 1955 -1025

7 DOF -2468 -1025 57 V3 2015 -1025

8 VSS -2311 -1025 58 V3 2075 -1025

9 CS1 -2251 -1025 59 V4 2135 -1025

10 CS2 -2191 -1025 60 V4 2195 -1025

11 VDD -2131 -1025 61 V5 2255 -1025

12 RES -2071 -1025 62 V5 2315 -1025

13 A0 -2011 -1025 63 VR 2375 -1025

14 VSS -1951 -1025 64 VR 2435 -1025

15 WR -1891 -1025 65 VDD 2495 -1025

16 RD -1831 -1025 66 VDD 2555 -1025

17 VDD -1771 -1025 67 VDD 2615 -1025

18 D0 -1613 -1025 68 M/S 2675 -1025

19 D1 -1393 -1025 69 CLS 2810 -1025

20 D2 -1172 -1025 70 VSS 2870 -1025

21 D3 -952 -1025 71 C86 2930 -1025

22 D4 -731 -1025 72 P/S 3065 -1025

23 D5 -511 -1025 73 VDD 3125 -1025

24 D6(SCL) -291 -1025 74 VSS 3185 -1025

25 D7(SI) -70 -1025 75 VDD 3245 -1025

26 VDD 155 -1025 76 DUMMY2 4139 -1025

27 VDD 215 -1025 77 C31 4200 -935

28 VDD 275 -1025 78 C30 4200 -875

29 VDD 335 -1025 79 C29 4200 -815

30 VSS 395 -1025 80 C28 4200 -755

31 VSS 455 -1025 81 C27 4200 -695

32 VSS 515 -1025 82 C26 4200 -635

33 VSS2 575 -1025 83 C25 4200 -575

34 VSS2 635 -1025 84 C24 4200 -515

35 VSS2 695 -1025 85 C23 4200 -455

36 VSS2 755 -1025 86 C22 4200 -395

37 VOUT 815 -1025 87 C21 4200 -335

38 VOUT 875 -1025 88 C20 4200 -275

39 C3

935 -1025 89 C19 4200 -215

40 C3

995 -1025 90 C18 4200 -155

41 C1

1055 -1025 91 C17 4200 -95

42 C1

1115 -1025 92 C16 4200 -35

43 C1

1175 -1025 93 C15 4200 25

44 C1

1235 -1025 94 C14 4200 85

45 C2

1295 -1025 95 C13 4200 145

46 C2

1355 -1025 96 C12 4200 205

47 C2

1415 -1025 97 C11 4200 265

48 C2

1475 -1025 98 C10 4200 325

49 VSS 1535 -1025 99 C9 4200 385

50 VSS 1595 -1025 100 C8 4200 445

NJU6676

Ver.2004-03-01

- 4 -

PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um)

101 C7 4200 505 151 S40 1533 1025

102 C6 4200 565 152 S41 1473 1025

103 C5 4200 625 153 S42 1413 1025

104 C4 4200 685 154 S43 1353 1025

105 C3 4200 745 155 S44 1293 1025

106 C2 4200 805 156 S45 1233 1025

107 C1 4200 865 157 S46 1173 1025

108 C0 4200 925 158 S47 1113 1025

109 COMM 4200 985 159 S48 1053 1025

110 DUMMY3 4119 1025 160 S49 993 1025

111 S0 3933 1025 161 S50 933 1025

112 S1 3873 1025 162 S51 873 1025

113 S2 3813 1025 163 S52 813 1025

114 S3 3753 1025 164 S53 753 1025

115 S4 3693 1025 165 S54 693 1025

116 S5 3633 1025 166 S55 633 1025

117 S6 3573 1025 167 S56 573 1025

118 S7 3513 1025 168 S57 513 1025

119 S8 3453 1025 169 S58 453 1025

120 S9 3393 1025 170 S59 393 1025

121 S10 3333 1025 171 S60 333 1025

122 S11 3273 1025 172 S61 273 1025

123 S12 3213 1025 173 S62 213 1025

124 S13 3153 1025 174 S63 153 1025

125 S14 3093 1025 175 S64 93 1025

126 S15 3033 1025 176 S65 33 1025

127 S16 2973 1025 177 S66 -27 1025

128 S17 2913 1025 178 S67 -87 1025

129 S18 2853 1025 179 S68 -147 1025

130 S19 2793 1025 180 S69 -207 1025

131 S20 2733 1025 181 S70 -267 1025

132 S21 2673 1025 182 S71 -327 1025

133 S22 2613 1025 183 S72 -387 1025

134 S23 2553 1025 184 S73 -447 1025

135 S24 2493 1025 185 S74 -507 1025

136 S25 2433 1025 186 S75 -567 1025

137 S26 2373 1025 187 S76 -627 1025

138 S27 2313 1025 188 S77 -687 1025

139 S28 2253 1025 189 S78 -747 1025

140 S29 2193 1025 190 S79 -807 1025

141 S30 2133 1025 191 S80 -867 1025

142 S31 2073 1025 192 S81 -927 1025

143 S32 2013 1025 193 S82 -987 1025

144 S33 1953 1025 194 S83 -1047 1025

145 S34 1893 1025 195 S84 -1107 1025

146 S35 1833 1025 196 S85 -1167 1025

147 S36 1773 1025 197 S86 -1227 1025

148 S37 1713 1025 198 S87 -1287 1025

149 S38 1653 1025 199 S88 -1347 1025

150 S39 1593 1025 200 S89 -1407 1025

Ver.2004-03-01

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NJU6676

PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um)

201 S90 -1467 1025 251 C39 -4200 565

202 S91 -1527 1025 252 C40 -4200 505

203 S92 -1587 1025 253 C41 -4200 445

204 S93 -1647 1025 254 C42 -4200 385

205 S94 -1707 1025 255 C43 -4200 325

206 S95 -1767 1025 256 C44 -4200 265

207 S96 -1827 1025 257 C45 -4200 205

208 S97 -1887 1025 258 C46 -4200 145

209 S98 -1947 1025 259 C47 -4200 85

210 S99 -2007 1025 260 C48 -4200 25

211 S100 -2067 1025 261 C49 -4200 -35

212 S101 -2127 1025 262 C50 -4200 -95

213 S102 -2187 1025 263 C51 -4200 -155

214 S103 -2247 1025 264 C52 -4200 -215

215 S104 -2307 1025 265 C53 -4200 -275

216 S105 -2367 1025 266 C54 -4200 -335

217 S106 -2427 1025 267 C55 -4200 -395

218 S107 -2487 1025 268 C56 -4200 -455

219 S108 -2547 1025 269 C57 -4200 -515

220 S109 -2607 1025 270 C58 -4200 -575

221 S110 -2667 1025 271 C59 -4200 -635

222 S111 -2727 1025 272 C60 -4200 -695

223 S112 -2787 1025 273 C61 -4200 -755

224 S113 -2847 1025 274 C62 -4200 -815

225 S114 -2907 1025 275 C63 -4200 -875

226 S115 -2967 1025 276 COMM -4200 -935

227 S116 -3027 1025

228 S117 -3087 1025

229 S118 -3147 1025

230 S119 -3207 1025

231 S120 -3267 1025

232 S121 -3327 1025

233 S122 -3387 1025

234 S123 -3447 1025

235 S124 -3507 1025

236 S125 -3567 1025

237 S126 -3627 1025

238 S127 -3687 1025

239 S128 -3747 1025

240 S129 -3807 1025

241 S130 -3867 1025

242 S131 -3927 1025

243 DUMMY4 -4119 1025

244 C32 -4200 985

245 C33 -4200 925

246 C34 -4200 865

247 C35 -4200 805

248 C36 -4200 745

249 C37 -4200 685

250 C38 -4200 625

NJU6676

Ver.2004-03-01

- 6 -

■BLOCK DIAGRAM

C0 - - - - C31 C63 - - - - C32

S0 - - - - - - - - - - - - - S131 COMM

Vss

VDD

V1 to V5

C1+/C1-

C2+/C2-

C3-

Vout

Vss2

CS2 A0 C86 D7

(SI) D6

(SCL) D5 to D0

RES CS1 WRRD

Reset MPU Interface

Instruction

Decoder Status Busy Flag Bus Holder

Internal Bus Line

Multiplexer

Column Address Register

Column Address Counter

Column Address Decoder

Page Address Register

Oscillator

Display

Timing

Line Counter

Line Address Decoder

Low Address Decoder

Common Direction

Display Data RAM

65 X 132 = 8,580-bit

Display Data Latch

Segment DriversCommon

Drivers Common

Drivers

Shift

Voltage

Converter

Common

Timing

OSC1

OSC2

Voltage

Regulator

Voltage

Followers

Internal

Power

Circuits

M/S

DOF

FRS

CLS

Initial Display Line

P/S

Ver.2004-03-01

-7-

NJU6676

■TERMINAL DESCRIPTION

No. Symbol Description

1,76,

110,243 DUMMY1~

DUMMY4 Dummy Terminals.

These are open terminals electrically.

11,17

26∼29

51,52

65∼67

73,75

VDD VDD=+3V

8,14,

30,31,

32,49,

50,70,74

VSS VSS=0V

33∼36 VSS2 Reference voltage for voltage booster

LCD Driving Voltage Supplying Terminal. When the internal voltage booster

is not used, supply each level of LCD driving voltage from outside with

following relation.

VDD≥V1≥V2≥V3≥V4≥V5≥VOUT

When the internal power supply is on, the internal circuits generate and

supply following LCD bias voltage from V1 to V4 terminal.

Bias V1 V2 V3 V4

1/7 Bias V5+6/7VLCD V5+5/7VLCD V5+2/7VLCD V5+1/7VLCD

1/9 Bias V5+8/9VLCD V5+7/9VLCD V5+2/9VLCD V5+1/9VLCD

53,54

55,56

57,58

59,60

61,62

(VLCD=VDD-V5)

41,42

43,44 C1+

C1- Boosted capacitor connecting terminals used for voltage booster.

47,48

45,46 C2+

C2- Boosted capacitor connecting terminals used for voltage booster.

39,40 C3-

Boosted capacitor connecting terminals used for voltage booster.

37,38 Vout Voltage booster output terminal. Connect the boosted capacitor between

this terminal and VSS2.

63,64 VR Voltage adjust terminal. V5 level is adjusted by external bleeder resistance

connecting between VDD and V5 terminal.

18∼25

(24,25) D0∼D7

(SCL,

SI)

P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation.

P/S="L" : D7=Serial data input terminal. D6=Serial data clock signal inpu

terminal. Data from SI is loaded at the rising edge of SCL and

latched as the parallel data at 8th rising edge of SCL.

Connect to the Address bus of MPU. The data on the D0 to D7 is

distinguished between Display data and Instruction by status of A0.

A0 H LDistin

. Display Data Instruction

13 A0

12 RES Reset terminal. When the RES terminal goes to “L”, the initialization is

performed.

Reset operation is executing during “L” state of RES.

10 CS1

CS2 Chip select terminal. Data Input/Output are available during CS1=”L” and

CS2=”H”.

NJU6676

Ver.2004-03-01

- 8 -

No. Symbol Description

16 RD

(E) <In case of 80 Type MPU>

RD signal of 80 type MPU input terminal. Active "L"

During this signal is "L" , D0 to D7 terminals are output.

Enable signal of 68 type MPU input terminal. Active "H"

Connect to the 80 type MPU WR signal. Active "L".

The data on the data bus input synchronizing the rise edge of this signal.

The read/write control signal of 68 type MPU input terminal.

R/W H LState Read Write

15 WR

(R/W)

MPU interface type selection terminal.

This terminal must connect to VDD or VSS.

C86 H LState 68 Type 80 Type

71 C86

Serial or parallel interface selection terminal.

P/S Chip Select Data/Command Data Read/Write Serial

Clock

“H” CS1, CS2 A0 D0∼D7 RD,WR -

“L” CS1, CS2 A0 SI(D7) - SCL(D6)

72 P/S

RAM data and status read operation do not work in mode of the serial

interface.

In case of the serial interface (P/S="L"),RD and WR must be fixed "H" or

"L", and D0 to D5 are high impedance.

3 OSC1

OSC2 System clock input terminal for Maker testing.(This terminal should be

Open) For external clock operation, the clock should be input to OSC1

terminal.

69 CLS Terminal to select whether or enable or disable the display clock internal

oscillator circuit.

CLS=”H” : Internal oscillator circuit is enable

CLS=”L” : Internal oscillator circuit is disabled (requires external input)

When CLS=”L”, input the display clock through the CL terminal.

This terminal selects the master/slave operation for the NJU6676. Master

operation outputs the timing signals that are required for the LCD display,

while slave operation inputs the timing signals required for the LCD,

synchronizing the LCD system.

M/S = ”H” : Master operation

M/S = ”L” : Slave operation

The following is true depending on the M/S and CLS status:

M/S CLS OSC. Power Supply

Circuit CL FR FRS DOF

“H” Available Available Output Output Output Output

“H” “L” Not Avail. Available Input Output Output Output

“L” * Not Avail. Not Avail. Input Input Output Input

68 M/S

*:Don’t Care

Ver.2004-03-01

-9-

NJU6676

No. Symbol Description

Display clock input/output terminal.

The following is true depending on the M/S and CLS status.

M/S CLS CL

“H” Output

“H” “L” Input

“L” * Input

6 CL

*:Don’t Care

5 FR LCD alternating current signal I/O terminal.

M/S = ”H” : Output

M/S = ”L” : Input

LCD Display blanking control terminal.

M/S = ”H” : Output terminal. Display “On” = “H”, Display “Off” = “L”

M/S = ”L” : Input terminal. External control. Refer to the following table.

DOF

Command H L

Display On” On Off

Display Off” Off Off

7 DOF

4 FRS The output terminal for the static drive.

This terminal is used in conjunction with the FR terminal.

∼108 C31∼C0 LCD driving signal output terminals.

-Common output terminal : C0 ∼C63

-Segment output terminals : S0 ∼S131

Common output terminal

The following output voltages are selected by the combination of FR and

status of common.

Scan

Data FR Output Voltage

H V5

H L VDD

H V1

L L V4

111

∼242 S0∼S131

Segment output terminal

The following output voltages are selected by the combination of FR and

data in the RAM. Output VoltageRAM

Data FR Normal Reverse

H VDD V2

H L V5 V3

H V2 VDD

L L V3 V5

244

∼275 C

∼C

109,

276 COMM COM output terminals for the indicator. Both terminals output the same

signal.

Leave these open if they are not used.

NJU6676

Ver.2004-03-01

- 10 -

■Functional description

(1) Block circuits description

(1-1) Busy Flag (BF)

During internal operation, the LSI is being busy and can’t accept any instructions except “status

read”. The BF data is output through D7 terminal by the “status read” instruction.

When the cycle time (tcyc) mentioned in the “AC characteristics” is satisfied, the BF check isn’t

required after each instruction, so that MPU processing performance can be improved.

(1-2) Initial display line register

The initial display line register assigns a DDRAM line address which corresponds to COM0 by

“initial display line set” instruction. It is used for not only normal display but also vertical display

scrolling and page switching without changing the contents of the DDRAM.

However, the 65

address for icon display can’t be assigned for initial display line address.

(1-3) Line counter

The line counter provides a DDRAM line address. It initializes its contents at the switching of frame

timing signal (FR), and also counts-up in synchronization with common timing signal.

(1-4) Column address counter

The column address counter is an 8-bit preset counter which provides a DDRAM column address,

and it is independent of below-mentioned page address register.

It will increment (+1) the column address whenever “display data read” or “display data write”

instructions are issued. However, the counter will be locked when no-existing address above (84)H

are addressed. The count-lock will be able to be released by the “column address set” instruction

again. The counter can invert the correspondence between the column address and segment driver

direction by means of “ADC set” instruction.

(1-5) Page address register

The page address register provides a DDRAM page address.

The last page address “8H” should be used for icon display because the only D0 is valid.

(1-6) Display data RAM (DDRAM)

The DDRAM contains 8,580-bit, and stores display data which is 1-to-1 correspondent to LCD panel

pixels.

When normal display mode, the display data “1” turns on and “0” turns off LCD pixels. When

inverse display mode, “1” turns off and “0” turns on.

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