Intel INTELLEC Guide rapide de l'utilisateur

INTELLECT

DOUBLEDENSITY

DISKETTEOPERATINGSYSTEM

HARDWARE

REFERENCE

MANUAL

1977

Intel

Corporation

IntelCorporation,3065Bowers

Avenue,

SantaClara,California95051OrderNumber:

9800422-01

Additional

copies

thismanual

otherIntelliterature

maybe

obtainedfrom:

Literature

Department

Intel

Corporation

3065

BowersAvenue

Santa

Clara,

95051

The

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thisdocument

subject

changewithoutnotice.

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Corporationmakes

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ofany

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implied

warranties

merchantability

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may

appear

thisdocument.IntelCorporationmakes

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update

norto

keepcurrent

the

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thisdocument.

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Intel

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reproduced

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orbyany

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consent

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Corporation.

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following

are

trademarks

IntelCorporation

andits

affiliates

andmaybe

used

identifyIntel

products:

BXP

CREDIT

ICE

iCS

iMMX

Insite

Intel

lntel

Intclevision

Intellec

Imellink

iOSP

iPDS

iRMX

iSBC

iSBX

iSXM

Librar>

Manager

MCS

Mcgachassis

Micromainframe

Micromap

Multibus

Multichannel

Multimodulc

Plug-A-Bubble

PROMPT

RMX/80

System

2000

UP1

A946/583/4K

Jay

PREFACE

This

reference

manual

isthe

primarysource

information

forthe

hardware

within

the

INTELLEC

DoubleDensityDisketteOperatingSystem.

explains

how

the

DisketteSystem

installed,

howit

communicates

with

the

INTELLEC

Microcomputer

DevelopmentSystem,

andhowit

functions

internally.

Refer

tothe

ISIS-II

System

User's

Guide(ordernumber98-306)

for

complete

instructions

onhowto

operate

the

DisketteSystem.

For

information

onthe

hostsystem,

refer

tothe

INTELLECMicrocomputerDevelopmentSystemHard-

ware

Reference

Manual

andtothe

INTELLEC

MicrocomputerDevelopment

SystemOperator'sManual.

Chapter

Title

TABLE

CONTENTS

Page

Chapter Title

Page

INTRODUCTION

1-1

1.1

SYSTEMOVERVIEW

1-1

1.2

RECORDINGFORMAT

1-4

OPERATIONAL

SUMMARY

AND

PROGRAMMINGCONSIDERATIONS

2-1

2.1

CHANNELCOMMANDS

2-2

2.2

DISKETTEOPERATIONS

2-5

2.3I/O

PARAMETERBLOCK

2-8

2.4

ERROR

INDICATIONS

2-11

THE

CHANNEL

BOARD

3-1

3.1

FUNCTIONALORGANIZATION

THE

CHANNEL

BOARD

3-1

3.2

THEORY

OPERATION:

CHANNELBOARD

3-3

3.2.1CHANNEL

COMMAND

BLOCK

. 3-3

3.2.2MICROCONTROL

UNIT

(MCU)

BLOCK

3-5

3.2.3MICROPROGRAMMEMORY

BLOCK

3-8

3.2.4CENTRAL

PROCESSING

ELEMENT

(CPE)

BLOCK

3-12

3.2.5DATA/CLOCK

SHI

BLOCK

3-15

3.2.6DATAFLOWCONTROLBLOCK

3-16

3.3

SCHEMATICS/PIN

LISTS:

CHANNEL

BOARD

3-17

THE

INTERFACE

BOARD

4-1

4.1

FUNCTIONALORGANIZATION

THE

INTERFACE

BOARD

4-1

4.2

THEORY

OPERATION:INTERFACE

BOARD

4-3

4.2.1DISKDRIVECONTROL

....

4-3

4.2.2WRITE

DATA

GENERATOR

4-6

4.2.3SERIALDATA/CLOCK

SYNCHRONIZATION

4-10

4.2.4

CYCLIC

REDUNDANCY

CHECK

(CRC)

4-10

4.2.5

BUS

CONTROL

4-13

4.3

SCHEMATICS/PINLISTS:

INTERFACE

BOARD

4-15

THE

DISKETTEDRIVES

5-1

5.1

FUNCTIONALDESCRIPTION

5-1

5.2

PERFORMANCECHARACTERISTICS

..5-2

5.2.1RECORDINGCHARAC-

TERISTICS

5-2

5.2.2

BIT

TRANSFERRATE

:'....

5-2

5.2.3

DATA

CAPACITY

5-2

5.2.4LATENCYTIME

5-3

5.2.5POSITIONINGCHARAC-

TERISTICS

5-3

5.2.6

FDD

START

AND

STOP

TIME

5-3

''•'

5.2.7

ERRORRECOVERY

5-3

-**«'•

5.2.8

ENVIRONMENTALLIMITS

•-•

5-4

5.2.9WRITEPROTECT

5-4

5.3

INTERFACESPECIFICATIONS

5-4

5.4

DISKETTECARTRIDGESTORAGE

AND

HANDLING

5-9

5.5

DISKETTECARTRIDGEWRITE

PROTECT

NOTCH

5-11

5.6

ADDITIONALINFORMATION

5-11

DISKETTESYSTEMMICROPROGRAM

6-1

6.1

INTRODUCTION

6-1

6.2

MICROPROGRAM

MODULE

DESCRIPTION

6-1

UTILIZATION

7-1

7.1

ENVIRONMENTALEXTREMES

7-1

7.2

MOUNTING

RECOMMENDATIONS

...

7-1

7.3

ELECTRICALCONNECTIONS

7-1

7.4

BASEADDRESSSELECTION

7-2

7.5

INTERRUPTLEVELSELECTION

....

7-2

OPERATINGCHARACTERISTICS

8-1

8.1AC

CHARACTERISTICS

8-1

8.2DC

CHARACTERISTICS

8-9

-IV

LIST

ILLUSTRATIONS

Chapter

Title

Page

INTRODUCTION

1-1

DISKETTESYSTEMBLOCKDIAGRAM

1-2

PHYSICALDATAFORMAT

1-6

1-3

BYTEREPRESENTATION

1-7

1-4

DATA

BYTES

1-7

1-5

DATA

BIT1-8

1-6

BIT

CELL

1-8

1-7

TRACKFORMAT

1-9

1-8

INDEXADDRESSMARK1-10

1-9

ADDRESSMARK1-10

1-10

DATA

ADDRESSMARK1-11

1-11

DELETED

DATA

ADDRESSMARK1-11

OPERATIONAL

SUMMARY

AND

PROGRAMMINGCONSIDERATIONS

2-1

SECTOR

FORMAT

2-7

2-2

'DATA'

ADDRESSMARK

2-7

2-3

'DELETED

DATA'

ADDRESSMARK

2-7

2-4

I/O

PARAMETERBLOCK

(IOPB)

FORMAT

2-9

CHANNELBOARD

3-1

CHANNELBOARD:FUNCTIONALBLOCKDIAGRAM

3-2

3001MICROPROGRAMCONTROL

UNIT:

FUNCTIONALBLOCK

DIAGRAM

3-6

3-3

3002

CENTRAL

PROCESSING

ELEMENT:FUNCTIONALBLOCK

DIAGRAM3-14

3-4

SCHEMATICDRAWING:CHANNELBOARD3-21

INTERFACEBOARD

4-1

INTERFACEBOARD:FUNCTIONALBLOCKDIAGRAM

4-2

HEADMOVEMENTCONTROLTIMING

4-5

4-3

READ

INITIATE

TIMING

4-6

4-4

M2FM

DATAENCODING

4-7

4-5

PRECOMPENSATION

TIMING

4-8

4-6

WRITEDATATIMING

4-9

4-7

PHASELOCKEDOSCILLATOR4-11

4-8

READSYNCHRONIZATIONTIMING4-12

4-9BUS

CONTROLTIMING4-14

4-10

CLK1/

AND

CLK2/

TIMING4-15

4-11

SCHEMATICDRAWING:INTERFACEBOARD4-22

DISKETTEDRIVES

5-1

FDD/FDCCINTERFACELINES

5-6

5-2

FDD

DRIVER/RECEIVERCIRCUITS

5-7

5-3

WRITEDATATIMING

5-8

5-4

READ

DATA

TIMING5-10

5-5

FLEXIBLEDISKCARTRIDGE

5-11

LIST

ILLUSTRATIONS

(Continued)

Chapter

Title

Page

DISKETTESYSTEMMICROPROGRAM

6-1

INITIALIZATION

6-2

MAINLINE

6-3

LOAD

LOWER

6-4

LOAD

UPPER

AND

START

I/O6-5

6-5

READRESULTBYTE

6-6

IOPBLOADER/OPDECODE

6-7

I/O

FINISH

6-8

SEEK

6-9

FORMAT6-10

6-10RECALIBRATE6-12

6-11

VERIFY/READ6-13

6-12WRITEDELETED/WRITE6-15

6-13ADDRESSPARAMETERCHECKER6-16

6-14READNEXTMEMORYWORD6-17

6-15WRITE

DATA

FIELD

6-18

6-16WRITECURRENTCHECK6-19

6-17

TIME-OUT

6-20

6-18ADDRESS

MARK

DETECT

6-21

6-19HEAD

STEPPER

6-22

6-20READDISKBYTE6-23

6-21

PROCESS

ADDRESS

FIELD

6-24

6-22WRITEADDRESS

FIELD

6-25

UTILIZATION

7-1

CONNECTORS

THE

CHANNEL

AND

INTERFACE

BOARDS

7-3

OPERATINGCHARACTERISTICS

8-1

'8-1

SLAVECOMMAND

TIMING

FDCC

8-2

8-2BUS

EXCHANGE

TIMING

8-3

MASTERCOMMAND

TIMING

8-4

-8-4

STEP/SETTLING

TIMINGS

8-6

8-5

READ

TIMING

8-7

xB-6

WRITE

TIMING

8-7

3-7

INDEX

TIMING

8-8

WRITE

FAULT

RESET

TIMING

8-8

LIST

TABLES

Chapter

Title

Page

INTRODUCTION

1-1

DISKETTEDRIVEPERFORMANCESPECIFICATIONS

1-3

OPERATIONALSUMMARY

AND

PROGRAMMINGCONSIDERATIONS

2-1

INTERRUPTCONTROLBITS

2-11

3THE

CHANNELBOARD

3-1

AGO

INPUT

SELECTION

3-7

3-2

MICROINSTRUCTION

BIT

ASSIGNMENTS

3-9

3-3

CONTROL

PULSES

AND

LEVELS

GENERATED

MICROPROGRAM

3-10

3-4

I-BUS

SELECTION

MASK

FIELD

BITS

3-12

3-5

K-BUS

INPUT

SELECTION

3-13

3-6

LIST:

P1BUS

CONNECTOR

3-17

3-7

LIST:

CONTROLLERCONNECTOR

3-19

4THE

INTERFACEBOARD

4-1

LIST:

P1BUS

CONNECTOR

4-16

4-2

LIST:

CONTROLLERCONNECTOR

4-18

4-3

DRIVECONNECTOR

4-19

OPERATINGCHARACTERISTICS

8-1

DISKETTEOPERATINGSYSTEM/INTELLEC

BUSAC

CHARACTERISTICS

8-1

8-2

DISKETTEOPERATINGSYSTEM/DRIVEINTERFACE

CHARACTERISTICS

...

8-5

8-3

DISKETTEOPERATINGSYSTEM

CHARACTERISTICS(INTELLECBUS)

8-9

8-4

DISKETTEOPERATINGSYSTEM

CHARACTERISTICS(DRIVE/DISPLAY

INTERFACE)

8-12

VII

-•*:-.

"»•'

CHAPTER

INTRODUCTION

The

INTELLEC

Double

DensityDiskette

Operating

Systemprovides

bulk

storage

capability

for

Intel's

INTELLEC

Microcomputer

DevelopmentSystem.

The

DisketteSystemincludes

intelligentcontroller

andupto

four

diskette

drives.

Eachdriveprovides

4,100,096

user-accessible

databits

storage

with

datatransferrate

500,000

bits/

second.

The

controller

has

beenimplemented

with

Intel'spowerful

Series

3000

Bipolar

Computing

Elements.

The

controller

provides

interface

tothe

INTELLEC

Systembus,

well

supporting

the

four

diskette

drives.

The

DisketteSystemrecords

all

data

inthe

Intelsoft-sectored

format,

described

Section

1.2.

1.1

SYSTEMOVERVIEW

addition

totwoor

four

diskettedrives,

their

enclosure(s)

(twodrives

per

enclosure)

and

powersupplies,

the

DisketteSystem

consists

ofthe

ChannelBoard

andthe

InterfaceBoard.These

two

printed

circuit

boards

reside

the

INTELLEC

Systemcabinet

and

constitute

the

diskettecontroller.Each

ofthe

systemcomponents

shown

-9

...

...~

.~,.~

g.-,

The

ChannelBoard

the

primary

control

module

within

the

DisketteSystem.

The

ChannelBoard

receives,

decodes

and

responds

channelcommands

from

Central

Processor

Unit

(CPU)

inthe

INTELLEC

System.

The

Channel

Board

can

access

INTELLEC

System

memory

determine

the

particular

diskette

operations

tobe

performed

and

fetch

the

parametersrequired

forthe

successful

completion

ofthe

specifiedoperations.

The

ChannelBoard

also

monitors

DisketteSystemstatus

and

error

conditions,

and

organizes

theseindications

into

'result

type'

and

'result

byte'

words

that

canbe

read

bya CPUinthe

INTELLEC

System.

«•'

-i

The

control

functions

ofthe

Channel

and

InterfaceBoards

are

provided

byan

8-bit

microprogrammedprocessor,

implemented

with

Intel's

Series

3000

Bipolar

Computing

Elements.

The

8-bit

controller

includes

four

3002

Central

Processing

Elements(2-bit

slice

per

CPE),

3001Microprogram

Control

Unit

and

512

x 32

bits

3604

programmable-

read-only-memory

(PROM)

which

stores

the

microprogram.

The

processing

and

control

capabilities

ofthe

Diskette

System

are

achieved

execution

ofthe

microprogram.

The

InterfaceBoardprovides

the

diskettecontroller

with

means

communicating

with

the

diskettedrives,

well

with

the

INTELLEC

Systembus.

Under

control

ofthe

microprogram

executed

from

the

Channel

Board,

the

InterfaceBoard

generates

those

signals

which

cause

the

read/writehead

onthe

selecteddrive

tobe

loaded

(i.e.,

come

contact

with

the

diskette

platter),

then

cause

the

head

move

tothe

propertrack.

The

Interface

Boardaccepts

the

databeing

read

offthe

diskette,interpretscertainsynchronizing

bit

patterns,checks

the

validity

ofthe

datausing

cyclic

redundancy

check(CRC)

polynomial,

and

passes

the

data

tothe

ChannelBoard.

During

write

operations,

the

InterfaceBoard

outputs

the

data

and

clockbits

tothe

selecteddrive

atthe

proper

times.

also

generates

CRC

characters

which

are

appended

tothe

data;thisallows

the

data

tobe

verifiedwhen

itis

subsequently

read.

1-1

LLJ

1-2

Table des matières

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