Intel F-Tile SDI II Intel Agilex Manuel utilisateur
Contents
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide......................... 3
1.1. Directory Structure................................................................................................ 3
1.2. Generating the Design............................................................................................6
1.3. Simulating the Design............................................................................................ 7
1.4. Compiling and Testing the Design in Hardware...........................................................9
1.5. Design Example Parameters.................................................................................. 11
2. Design Example Detailed Description............................................................................13
2.1. Features............................................................................................................. 13
2.2. Hardware and Software Requirements.................................................................... 14
2.3. Functional Description.......................................................................................... 15
2.3.1. Design Components................................................................................. 19
2.3.2. Clocking Scheme..................................................................................... 22
2.4. Simulation.......................................................................................................... 27
2.4.1. Testbench Components............................................................................. 27
2.4.2. Test Description....................................................................................... 28
2.4.3. Hardware Testing..................................................................................... 29
2.4.4. Signal.................................................................................................... 30
3. Document Revision History for the F-Tile SDI II Intel Agilex Design Example User
Guide....................................................................................................................... 39
Contents
F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide Send Feedback
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1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example
Quick Start Guide
The SDI II Intel® FPGA IP design examples for Intel Agilex™ F-tile devices feature a
simulating testbench and a hardware design that supports compilation and hardware
testing.
When you generate a design example, the parameter editor automatically creates the
files necessary to simulate, compile, and test the design in hardware.
Note: The support for 21.4 Intel Agilex SDI II Design Example hardware is preliminary and
only supports static rate.
Figure 1. Development Stages
Design
Example
Generation
Compilation
(Simulator)
Compilation
(Quartus Prime)
Functional
Simulation
Hardware
Testing
1.1. Directory Structure
The directories contain the generated files for the design examples.
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Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
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*Other names and brands may be claimed as the property of others.
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Registered
Figure 2. Directory Structure for the Design Examples
<Design Example>
qdb
quartus
sdi_ii_agi_demo.qpf
sdi_ii_agi_demo.qsf
sdi_ii_agi_demo.sv
sdi_ii_agi_demo.sdc
edge_detector.sv
clock_heartbeat.v
sgpio_slave.v
vid_pattgen (for serial loopback design)
rx (for simplex mode design)
tx (for simplex mode design)
du (for duplex mode design)
loopback (for parallel loopback design)
phy_adapter
alt_reset_delay.v
device_init.sv
<xcvr_ref_sysclk ip generated folder>
xcvr_ref_sysclk.ip
rtl
tpg.ctrl.tcl
generation.log
hwtest
(for serial loopback design)
simulation
mentor
synopsys
testbench
xcelium
<reset_release ip generated folder>
reset_release.ip
jtag.sdc
sim_setup_gen.sh
Table 1. Other Generated Files in RTL Folder
Folders Files
vid_pattgen /sdi_ii_colorbar_gen.v
/sdi_ii_ed_vid_pattgen.v
/sdi_ii_makeframe.v
/sdi_ii_patho_gen.v
/pattgen_ctrl.qsys
<qsys generated folder>
loopback /loopback_top.v
/fifo/sdi_ii_ed_loopback.sdc
/fifo/sdi_ii_ed_loopback.v
du /du_<vid_std>_top.v
sdi_<vid_std>_du_sys.qsys (optional)
<qsys generated folder>
rx /rx_<vid_std>_top.v
/sdi_<vid_std>_rx_sys.qsys
continued...
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Folders Files
<qsys generated folder>
tx /tx_<vid_std>_top.sv
/sdi_<vid_std>_tx_sys.qsys
<qsys generated folder>
phy_adapter /sdi_ftile_phy_adapter.sv
/sdi_ftile_phy_adapter.sdc
/rxdata_dcfifo.ip
/rxdata_mwfifo.ip (optional)
[Only in 12-SDI single rate mode Design Example]
txdata_fifo.ip
<ip generated folder>
Table 2. Other Generated Files in Simulation Folder
Folders Files
mentor /mentor.do
synopsys /vcs/filelist.f
/vcs/vcs_sim.sh
/vcsmx/vcsmx_sim.sh
testbench tb_top.sv
rx_checker/sdi_ii_tb_rx_checker.v
rx_checker/tb_data_compare.v
rx_checker/tb_dual_link_sync.v
rx_checker/tb_fifo_line_test.v
rx_checker/tb_frame_locked_test.sv
rx_checker/tb_ln_check.v
rx_checker/tb_rxsample_test.v
rx_checker/tb_trs_locked_test.sv
rx_checker/tb_txpll_test.sv
rx_checker/tb_vpid_check.v
tb_control/sdi_ii_tb_control.v
tb_control/tb_clk_rst.v
tb_control/tb_data_delay.v
tb_control/tb_serial_delay.sv
tb_control/tb_tasks.v
tb_checker/sdi_ii_tb_tx_checker.v
continued...
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Folders Files
tb_checker/tb_serial_check_counter.v
tb_checker/tb_serial_descrambler.v
tb_checker/tb_tx_clkout_check.v
vid_pattgen/sdi_ii_colorbar_gen.v (for parallel loopback design)
vid_pattgen/sdi_ii_ed_vid_pattgen.v (for parallel loopback design)
vid_pattgen/sdi_ii_makeframe.v (for parallel loopback design)
vid_pattgen/sdi_ii_patho_gen.v (for parallel loopback design)
xcelium /xcelium_sim.sh
1.2. Generating the Design
Configure the SDI II Intel FPGA IP parameter editor in the Intel Quartus® Prime
software to generate the design examples.
Figure 3. Generating the Design Flow
Start Parameter
Editor
Specify IP Variation
and Select Device
Select
Design Parameters
Specify
Example Design
Initiate
Design Generation
1. Create an empty project targeting Intel Agilex device family and select the desired
device.
2. In the IP Catalog, locate and double-click SDI II Intel FPGA IP. The IP
Parameter Editor window appears.
3. Specify a top-level name for your custom IP variation. The parameter editor saves
the IP variation settings in a file named <your_ip>.ip or <your_ip>.qsys.
4. On the Design Example tab, select the desired parameter for the design
example. Select Simulation to generate the testbench, and select Synthesis to
generate the hardware design example.
5. For Target Development Kit, select the relevant FPGA development kit. You may
change the target device using the Change Target Device parameter if your
board revision does not match the grade of the default targeted device.
6. Click Generate Example Design button to initiate the design generation.
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Figure 4. Design Example Tab in SDI II IP Parameter Editor
1.3. Simulating the Design
Figure 5. Simulating the Design flow
Run
Support Logic Generation
in Quartus
Run
Generate Simulator Setup
Script for IP
in Quartus
Go to
simulation/<Simulator>
Directory
Run
<Simulation Script>
To run example design simulation, follow these steps:
1. Generate the necessary simulation setup files.
a. Using GUI method:
i. Open the Intel Quartus Prime Project in Intel Quartus Prime directory.
ii. Run Support-Logic Generation to generate the transceiver RTL files.
Figure 6. Support-Logic Generation in Compilation Dashboard
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iii. To generate the simulation setup files, click Tools ➤ Generate Simulator
Setup Script for IP....
iv. Set the output directory to .../simulation.
Figure 7. Generating Simulation Setup File Using GUI
b. Using command-line:
i. Open a command-line terminal.
ii. Make sure your environment variable points to the bin/bin64 in your
Intel Quartus Prime installation directory
iii. Change the current directory to the generated simulation folder in your
terminal.
iv. Run this command source sim_setup_gen.sh.
2. Go to simulation folder.
3. Go to the desired simulator folder and run the simulation script:
a. ModelSim* SE or Questa* FE: Bring up the simulator GUI, change directory
to mentor folder and type do mentor.do
b. VCS*: Go to synopsys/vcs folder and type source vcs_sim.sh.
c. VCS MX: Go to synopsys/vcsmx folder and type source vcsmx_sim.sh
d. Xcelium* (supported verilog only): Go to xcelium folder and type source
xcelium_sim.sh(1)
4. A successful simulation ends with the following message:
(1) Xcelium is not supporting VHDL format.
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1.4. Compiling and Testing the Design in Hardware
Figure 8. Compiling and Testing the Design Flow
Compile Design
in Quartus Prime
Software
Set Up Hardware Test Design
in Hardware
Program Device
To compile and run a demonstration test on the hardware design example, follow
these steps:
1. Open the Intel Quartus Prime project (sdi_ii_agi_demo.qpf) located in
Quartus directory.
2. To perform Intel Quartus Prime compilation, click Processing ➤ Start
Compilation.
3. Connects the Nextera SDI daughter card to FMC port A on the development kit.
4. For parallel loopback design, connects the BNC RX connector (J1/12G In) to an
external video source and connects the TX connector (J2/12G Out) to a video
analyzer. For serial loopback design, connects the BNC TX connector (J2/12G
Out) to RX connector (J1/12G In) or a video analyzer.
5. Ensure all the switches on the development kit are in their default position per
Agilex I-series SoC Development Kit User Guide.
6. After the compilation completes, open Programmer and program the
generated .sof file to the development kit.
7. For serial loopback design, you need to open System Console to control the
internal video pattern generator.
a. Go to Tools ➤ System Debugging Tools and click System Console.
b. After the initialization, type source ../hwtest/tpg_ctrl.tcl to open the
pattern generator control UI.
c. Select your desired video format through the UI.
Note: To allow segmented frame video format (1080sF30, 1080sF25) and
interlaced video format (1080i60, 1080i50) to be correctly differentiated in
external analyzer, you must insert Payload ID in the serial loopback design
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Figure 9. Selecting Video Format Through System Console
8. The analyzer should be able to display the video generated from the source. Refer
to jumper settings in the Jumper Settings and Descriptions Table to change the
jumper (J8) position before switching between fractional frame rate and integer
frame rate video format. You must press the push button (PB0) to trigger a device
(LMK03328) power cycling through the PDN pin every time you change the jumper
(J8) position.
Figure 10. Jumper Settings on Nextera 12G-SDI FMC Daughtercard
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