Holtek HT49RA0 Manuel utilisateur

HT49RA0/HT49CA0

Remote Type 8-Bit MCU with LCD

Rev. 1.50 1 March 20, 2014

Features

·Operating voltage: 2.0V~3.6V

·8 bidirectional I/O lines and 8 input lines

·Two external interrupt input

·One 8-bit programmable timer/event counter

·LCD driver with 21´2, 21´3or20´4 segments

·2K´14 program memory

·96´8 data memory RAM

·Real Time Clock (RTC)

·8-bit prescaler for RTC

·One carrier output (1/2or1

/3 duty)

·Software LCD, RTC control

·On-chip RC and 32768Hz crystal oscillator

·Watchdog Timer

·HALT function and wake-up feature reduce power

consumption

·4-level subroutine nesting

·Bit manipulation instruction

·14-bit table read instruction

·Up to 1ms instruction cycle with 4MHz system clock

·63 powerful instructions

·All instructions in 1 or 2 machine cycles

·Low voltage reset/detector function

·64-pin LQFP package

General Description

The HT49RA0/HT49CA0 are 8-bit high performance,

RISC architecture microcontroller devices specifically

designed for multiple I/O control product applications.

The mask version HT49CA0 is fully pin and functionally

compatible with the OTP version HT49RA0 device.

The advantages of low power consumption, I/O

flexibility, timer functions, oscillator options, watchdog

timer, HALT and wake-up functions, as well as low cost,

enhance the versatility of this device to suit a wide range

of application possibilities such as industrial control,

consumer products, and particularly suitable for use in

products such as infrared LCD remote controllers and

various subsystem controllers.

Block Diagram

Pin Assignment

HT49RA0/HT49CA0

Rev. 1.50 2 March 20, 2014

P r o g r a m

C o u n t e r

P r o g r a m

m e m o r y

I n s t r u c t i o n

R e g i s t e r

I n s t r u c t i o n

D ecoder

T i m i n g

G e n e r a t i o n

O S C 4 O S C 1

V D D

V S S

O S C 3

I n t e r r u p t

C i r c u i t

I N T C

M P MX

M X

D A T A

M e m o r y

A L

S h i f t e r

S T A T S

A C C

P A

P O R T A

T M R C

T M R

W D T O S C

P A 0 ~ P A 7

R T C O S C

O S C 3

O S C 4

R T C

S T A C K

L C D

M e m o r y

B P

L C D D r i v e r

C O M 0 ~

C O M 2

C O M 3 /

S E G 2 0

S E G 0 ~

S E G 1 9

T i m e B a s e

W D T

fS Y S / 4

fS Y S

R T C I n t e r r u p t

P B 2 / T M R

H A L T E N / D I S

L V D / L V R

S Y S C L K / 4

R E S B

P B

P O R T B

P B 2 / T M R

P B 0 / I N T 0

P B 1 / I N T 1

P B 3 ~ P B 7

S Y S C L K / 4

F r e q u e n c y D i v i d e r

C a r r i e r C o n t r o l

L e v e l o r C a r r i e r

P C 0 / R E M

P C 0 C o n t r o l

P A 5

P A 6

P A 7

P B 0 / I N T 0

P B 1 / I N T 1

P B 2 / T M R

P B 3

P B 4

P B 5

V S S

P C 0 / R E M

P B 6

P B 7

N C

S E G 0

S E G 1

S E G 2

S E G 3

S E G 4

S E G 5

S E G 6

S E G 7

S E G 8

S E G 9

S E G 1 0

S E G 1 1

S E G 1 2

S E G 1 3

S E G 1 4

S E G 1 5

N C

O S C 4

O S C 3

V D D

N C

O S C 1

R E S

P A 0

P A 1

P A 2

P A 3

P A 4

N C

S E G 1 6

S E G 1 7

S E G 1 8

S E G 1 9

C O M 3 / S E G 2 0

C O M 2

C O M 1

C O M 0

C 2

C 1

V 2

V 1

V L C D

H T 4 9 R A 0 / H T 4 9 C A 0

6 4 L Q F P - A

1 0

1 1

1 2

1 3

2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8

4 3

4 4

4 5

4 6

4 7

4 8

6 06 16 26 36 4

2 9 3 0 3 1 3 2

3 6

3 7

3 8

3 9

4 0

4 1

4 2

5 25 35 45 55 65 75 85 9

1 4

1 5

1 6

3 3

3 4

3 5

1 7 1 8 1 9

4 95 05 1

Pin Description

Pin Name I/O Options Description

PA0~PA7 I/O ¾

Bidirectional 8-bit input/output port with pull-high resistors. Each bit can

be determined as NMOS output or Schmitt trigger input by software in-

structions.

PB0/INT0

PB1/INT1

PB2/TMR

PB3~PB7

I Wake-up

8-bit Schmitt trigger input port with pull-high resistors. Eash bit can be

configured as a wake-up input by code option.

Pins PB0, PB1 and PB2 are pin-shared with INT0, INT1 and TMR respec-

tively.

PC0/REM I/O Level or Carrier

Pull-high

Level or carrier output pin

PC0 can be set as CMOS output pin or carrier output pin by code option.

V1, V2, C1, C2 I ¾Voltage pump

VLCD LCD power supply

VLCD should be larger than VDD for correct operation i.e. VLCD ³VDD.

COM0~COM2

COM3/SEG20 O1/2, 1/3or1

Duty

COM3/SEG20 can be set as a segment or as a common output driver for

LCD panel by options. COM0~COM2 are output for LCD panel plate.

SEG0~SEG11 O ¾LCD driver outputs for LCD panel segments.

SEG12~SEG19 O SEG12~SEG19

CMOS output

LCD driver outputs for LCD panel segments.

SEG12~SEG19 can be optioned as logical outputs.

OSC1 I RC OSC1 connect a resistor to GND for internal system clock.

OSC3

OSC4

O¾

Real time clock oscillator. OSC3 and OSC4 are connected to a 32768Hz

crystal oscillator for timing purpose. It can¢t be used as a system clock. No

capacitor is built-in. If RTC is not selected as fs. OSC3,OSC4 should be

left floating.

RES I¾Schmitt trigger reset input, active low.

VSS ¾¾

Negative power supply, ground

VDD ¾¾

Positive power supply

Absolute Maximum Ratings

Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°Cto125°C

Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°Cto85°C

IOL Total ..............................................................150mA IOH Total............................................................-100mA

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings²may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed

in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics Ta=25°C

Symbol Parameter

Test Conditions

Min. Typ. Max. Unit

VDD Conditions

VDD Operating Voltage ¾¾ 2.0 ¾3.6 V

IDD Operating Current

(RC OSC) 3V No load, fSYS=4MHz ¾0.7 1.5 mA

ISTB1 Standby Current

(*fS=T1) 3V No load, system HALT,

LCD off at HALT ¾0.1 1 mA

ISTB2 Standby Current

(*fS=32.768kHz OSC) 3V No load, system HALT,

LCD On at HALT, C type ¾2.5 5 mA

HT49RA0/HT49CA0

Rev. 1.50 3 March 20, 2014

Symbol Parameter

Test Conditions

Min. Typ. Max. Unit

VDD Conditions

ISTB3 Standby Current

(*fS=WDT RC OSC) 3V No load, system HALT

LCD On at HALT, C type ¾25

VIL1 Input Low Voltage for I/O

Ports, TMR, INT0 and INT1 3V ¾0¾0.3VDD V

VIH1 Input High Voltage for I/O

Ports, TMR, INT0 and INT1 3V ¾0.7VDD ¾VDD V

VIL2 Input Low Voltage (RES)3V ¾0¾0.4VDD V

VIH2 Input High Voltage (RES)3V ¾0.9VDD ¾VDD V

IOL1 I/O Port & REM Sink Current 3V VOL=0.1VDD 48

¾mA

IOH1 I/O Port & REM Source Current 3V VOH=0.9VDD -5-7¾mA

IOL2 LCD Common and Segment

Current 3V VOL=0.1VDD 210 420 ¾mA

IOH2 LCD Common and Segment

Current 3V VOH=0.9VDD -80 -160 ¾mA

RPH Pull-high Resistance of I/O Ports 3V ¾100 150 200 kW

VLVR Low Voltage Reset Voltage ¾¾ 2.0 2.1 2.2 V

VLVD Low Voltage Detector Voltage ¾¾ 2.2 2.3 2.4 V

VPOR VDD Start Voltage to Ensure

Power-on Reset ¾¾ ¾¾

100 mV

RPOR VDD Rise Rate to Ensure

Power-on Reset ¾¾0.035 ¾¾

V/ms

Note: ²*²for the value of VA refer to the LCD driver section.

tSYS=1/fSYS

²*fS²please refer to WDT clock option

A.C. Characteristics Ta=25°C

Symbol Parameter

Test Conditions

Min. Typ. Max. Unit

VDD Conditions

fSYS System Clock ¾2.0V~3.6V, 4MHz ±3%,

Temp.= 0°C~50°C¾4000 ¾kHz

fRTCOSC RTC Frequency ¾¾ ¾

32768 ¾Hz

fTIMER Timer I/P Frequency (TMR) 3V ¾0¾4000 kHz

tWDTOSC Watchdog Oscillator Period 3V ¾45 90 180 ms

tRES External Reset Low Pulse Width ¾¾ 1¾¾ms

tLVR Low Voltage Width to Reset ¾¾0.25 1 2 ms

tSST System Start-up Timer Period ¾Wake-up from HALT ¾1024 ¾*tSYS

tINT Interrupt Pulse Width ¾¾ 1¾¾ms

Note: *tSYS=1/fSYS

HT49RA0/HT49CA0

Rev. 1.50 4 March 20, 2014

HT49RA0/HT49CA0

Rev. 1.50 5 March 20, 2014

Functional Description

Execution Flow

The system clock is derived from RC oscillator. It is inter-

nally divided into four non-overlapping clocks. One in-

struction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such

a way that a fetch takes one instruction cycle while de-

coding and execution takes the next instruction cycle.

The pipelining scheme causes each instruction to effec-

tively execute in a cycle. If an instruction changes the

value of the program counter, two cycles are required to

complete the instruction.

Program Counter -PC

The program counter (PC) is of 11 bits wide and controls

the sequence in which the instructions stored in the pro-

gram ROM are executed. The contents of the PC can

specify a maximum of 2048 addresses.

After accessing a program memory word to fetch an in-

struction code, the value of the PC is incremented by

one. The PC then points to the memory word containing

the next instruction code.

When executing a jump instruction, conditional skip ex-

ecution, loading a PCL register, a subroutine call, an ini-

tial reset, an internal interrupt, an external interrupt, or

returning from a subroutine, the PC manipulates the

program transfer by loading the address corresponding

to each instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get a proper instruction; oth-

erwise proceed with the next instruction.

The lower byte of the PC (PCL) is a readable and

writeable register (06H). Moving data into the PCL per-

forms a short jump. The destination is within 256 locations.

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

P C P C + 1 P C + 2

S y s t e m C l o c k

O S C 2 ( R C o n l y )

P C

Execution Flow

Mode

Program Counter

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Initial Reset 00000000000

External Interrupt 0 00000000100

External Interrupt 1 00000001000

Timer/Event Counter overflow 00000001100

Time Base Interrupt 00000010000

RTC Interrupt 00000010100

Skip Program Counter + 2

Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return From Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Note: *10~*0: Program counter bits S10~S0: Stack register bits

#10~#0: Instruction code bits @7~@0: PCL bits

HT49RA0/HT49CA0

Rev. 1.50 6 March 20, 2014

When a control transfer takes place, an additional

dummy cycle is required.

Program Memory -ROM

The program memory (ROM) is used to store the pro-

gram instructions which are to be executed. It also con-

tains data, table, and interrupt entries, and is organized

into 2048 ´14 bits which are addressed by the program

counter and table pointer.

Certain locations in the ROM are reserved for special

usage:

·Location 000H

Location 000H is reserved for program initialization.

After chip reset, the program always begins execution

at this location.

·Location 004H

Location 004H is reserved for the external interrupt

service program. If the INT0 input pin is activated, and

the interrupt is enabled, and the stack is not full, the

program begins execution at location 004H.

·Location 008H

Location 008H is reserved for the external interrupt

service program also. If the INT1 input pin is activated,

and the interrupt is enabled, and the stack is not full,

the program begins execution at location 008H.

·Location 00CH

Location 00CH is reserved for the Timer/Event Coun-

ter interrupt service program. If a timer interrupt re-

sults from a Timer/Event Counter overflow, and if the

interrupt is enabled and the stack is not full, the pro-

gram begins execution at location 00CH.

·Location 010H

Location 010H is reserved for the Time Base interrupt

service program. If a Time Base interrupt occurs, and

the interrupt is enabled, and the stack is not full, the

program begins execution at location 010H.

·Location 014H

Location 014H is reserved for the real time clock inter-

rupt service program. If a real time clock interrupt oc-

curs, and the interrupt is enabled, and the stack is not

full, the program begins execution at location 014H.

·Table location

Any location in the ROM can be used as a look-up ta-

ble. The instructions ²TABRDC [m]²(the current page,

1 page=256 words) and ²TABRDL [m]²(the last page)

transfer the contents of the lower-order byte to the

specified data memory, and the contents of the

higher-order byte to TBLH (Table Higher-order byte

byte in the table is well-defined; the other bits of the ta-

ble word are all transferred to the lower portion of

TBLH, and the remaining 2 bit is read as ²0². The

TBLH is read only, and the table pointer (TBLP) is a

read/write register (07H), indicating the table location.

Before accessing the table, the location should be

placed in TBLP. All the table related instructions re-

quire 2 cycles to complete the operation. These areas

may function as a normal ROM depending upon the

user¢s requirements.

000H

D e v i c e i n i t i a l i z a t i o n p r o g r a m

E x t e r n a l i n t e r r u p t 0 s u b r o u t i n e

T i m e r / e v e n t c o u n t e r 0 i n t e r r u p t s u b r o u t i n e

P r o g r a m

R O M

1 4 b i t s

014H

Look-up table (256 w ords)

7 F F H

N o t e : n r a n g e s f r o m 0 t o 6

E x t e r n a l i n t e r r u p t 1 s u b r o u t i n e

0 0 C H

T i m e B a s e I n t e r r u p t

R T C I n t e r r u p t

Look-up table (256 w ords)

100H

1 F F H

010H

700H

008H

004H

n F F H

Program Memory

Instruction(s)

Table Location

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table Location

Note: *10~*0: Table location bits P10~P8: Current program Counter bits

@7~@0: Table pointer bits

HT49RA0/HT49CA0

Rev. 1.50 7 March 20, 2014

Stack Register -STACK

The stack register is a special part of the memory used

to save the contents of the program counter. The stack

is organized into 4 levels and is neither part of the data

nor part of the program, and is neither readable nor

writeable. Its activated level is indexed by a stack

pointer (SP) and is neither readable nor writeable. At a

commencement of a subroutine call or an interrupt ac-

knowledgment, the contents of the program counter is

pushed onto the stack. At the end of the subroutine or in-

terrupt routine, signaled by a return instruction (RET or

RETI), the contents of the program counter is restored

to its previous value from the stack. After chip reset, the

SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag is recorded but the ac-

knowledgment is still inhibited. Once the SP is decre-

mented (by RET or RETI), the interrupt is serviced. This

feature prevents stack overflow, allowing the program-

mer to use the structure easily. Likewise, if the stack is

full, and a ²CALL²is subsequently executed, a stack

overflow occurs and the first entry is lost (only the most

recent 4 return addresses are stored).

Data Memory -RAM

The data memory is divided into two functional group :

special function registers (20´8) and general purpose

data memory (96´8). Most of them are read/write, but

some are read only.

The unused space before 20H is reserved for future ex-

panded usage and reading these locations will return

the result 00H. The general purpose data memory, ad-

dressed from 20H to 7FH, is used for data and control

information under instruction command. The areas in

the RAM can directly handle arithmetic, logic, incre-

ment, decrement, and rotate operations. Except some

dedicated bits, each bit in the RAM can be set and reset

by ²SET [m].i²and ²CLR [m].i². They are also indirectly

accessible through the Memory pointer register 0

(MP0;01H) or the Memory pointer register 1 (MP1;03H).

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] and [02H] accesses the RAM pointed to

by MP0 (01H) and MP1(03H) respectively. Reading lo-

cation 00H or 02H indirectly returns the result 00H.

While, writing it indirectly leads to no operation.

The function of data movement between two indirect ad-

dressing registers is not supported. The memory pointer

registers, MP0 and MP1, are both 7-bit registers used to

access the RAM by combining corresponding indirect

addressing registers. MP0 can only be applied to data

memory, while MP1 can be applied to data memory and

LCD display memory.

Accumulator -ACC

The accumulator (ACC) is related to the ALU opera-

tions. It is also mapped to location 05H of the RAM and

is capable of operating with immediate data. The data

movement between two data memory locations must

pass through the ACC.

Arithmetic and Logic Unit -ALU

This circuit performs 8-bit arithmetic and logic opera-

tions and provides the following functions:

·Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

·Logic operations (AND, OR, XOR, CPL)

·Rotation (RL, RR, RLC, RRC)

·Increment and Decrement (INC, DEC)

·Branch decision (SZ, SNZ, SIZ, SDZ etc.)

The ALU not only saves the results of a data operation but

also changes the status register.

G e n e r a l P u r p o s e

D a t a M e m o r y

( 9 6 B y t e s )

S p e c i a l P u r p o s e

D a t a M e m o r y

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

7 F H

: n u s e d .

R e a d a s

0 0

20H

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

M P 0

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

M P 1

B P

A C C

P C L

T B L P

T B L H

R T C C

S T A T S

I N T C 0

T M R

TM R C

P A

P B

P C

P C C

I N T C 1

L C D C

RAM Mapping

HT49RA0/HT49CA0

Rev. 1.50 8 March 20, 2014

Status Register -STATUS

The status register (0AH) is of 8 bits wide and contains,

a carry flag (C), an auxiliary carry flag (AC), a zero flag

(Z), an overflow flag (OV), a power down flag (PDF), and

a watchdog time-out flag (TO). It also records the status

information and controls the operation sequence.

Except the TO and PDF flags, bits in the status register

can be altered by instructions similar to other registers.

Data written into the status register does not alter the TO

or PDF flags. Operations related to the status register,

however, may yield different results from those in-

tended. The TO and PDF flags can only be changed by

a Watchdog Timer overflow, chip power-up, or clearing

the Watchdog Timer and executing the ²HALT²instruc-

tion. The Z, OV, AC, and C flags reflect the status of the

latest operations.

On entering the interrupt sequence or executing the

subroutine call, the status register will not be automati-

cally pushed onto the stack. If the contents of the status

is important, and if the subroutine is likely to corrupt the

status register, the programmer should take precautions

and save it properly.

Interrupts

The devices provides two external interrupts, one inter-

nal timer/event counter interrupts, an internal time base

interrupt, and an internal real time clock interrupt. The

interrupt control register 0 (INTC0;0BH) and interrupt

control register 1 (INTC1;1EH) both contain the interrupt

control bits that are used to set the enable/disable status

and interrupt request flags.

Once an interrupt subroutine is serviced, other inter-

rupts are all blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may take place during this interval,

but only the interrupt request flag will be recorded. If a

certain interrupt requires servicing within the service

routine, the EMI bit and the corresponding bit of the

INTC0 or of INTC1 may be set in order to allow interrupt

nesting. Once the stack is full, the interrupt request will

not be acknowledged, even if the related interrupt is en-

abled, until the Stack Pointer is decremented. If immedi-

ate service is desired, the stack should be prevented

from becoming full.

All these interrupts can support a wake-up function. As

an interrupt is serviced, a control transfer occurs by

pushing the contents of the program counter onto the

stack followed by a branch to a subroutine at the speci-

fied location in the ROM. Only the contents of the pro-

gram counter is pushed onto the stack. If the contents of

the register or of the status register (STATUS) is altered

by the interrupt service program which corrupts the de-

sired control sequence, the contents should be saved in

advance.

External interrupts are triggered by a high to low or low

to high or both transition of INT0 or INT1, and the related

interrupt request flag (EIF0;bit 4 of INTC0, EIF1;bit 5 of

INTC0) is set as well. After the interrupt is enabled, the

stack is not full, and the external interrupt is active, a

subroutine call to location 04H or 08H occurs. The inter-

rupt request flag (EIF0 or EIF1) and EMI bits are all

cleared to disable other interrupts.

Bit No. Label Function

C is set if the operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-

tate through carry instruction.

1AC

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

2 Z Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

3OV

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

4 PDF PDF is cleared by either a system power-up or executing the ²CLR WDT²instruction. PDF is

set by executing the ²HALT²instruction.

5TO

TO is cleared by a system power-up or executing the ²CLR WDT²or ²HALT²instruction. TO

is set by a WDT time-out.

6, 7 ¾Unused bit, read as ²0²

Status (0AH) Register

HT49RA0/HT49CA0

Rev. 1.50 9 March 20, 2014

The internal Timer/Event Counter interrupt is initialized

by setting the Timer/Event Counter interrupt request flag

(TF;bit 6 of INTC0), which is normally caused by a timer

overflow. After the interrupt is enabled, and the stack is

not full, and the TF bit is set, a subroutine call to location

0CH occurs. The related interrupt request flag (TF) is re-

set, and the EMI bit is cleared to disable further interrupts.

The time base interrupt is initialized by setting the time

base interrupt request flag (TBF;bit 4 of INTC1), that is

caused by a regular time base signal. After the interrupt

is enabled, and the stack is not full, and the TBF bit is

set, a subroutine call to location 10H occurs. The related

interrupt request flag (TBF) is reset and the EMI bit is

cleared to disable further interrupts.

The real time clock interrupt is initialized by setting the

real time clock interrupt request flag (RTF; bit 5 of

INTC1), that is caused by a regular real time clock signal.

After the interrupt is enabled, and the stack is not full, and

the RTF bit is set, a subroutine call to location 14H oc-

curs. The related interrupt request flag (RTF) is reset and

the EMI bit is cleared to disable further interrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are all held until the ²RETI²in-

struction is executed or the EMI bit and the related

interrupt control bit are set both to 1 (if the stack is not

full). To return from the interrupt subroutine, ²RET²or

²RETI²may be invoked. RETI sets the EMI bit and en-

ables an interrupt service, but RET does not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts

are enabled. In the case of simultaneous requests, the

priorities in the following table apply. These can be

masked by resetting the EMI bit.

Interrupt Source Priority Vector

External interrupt 0 1 04H

External interrupt 1 2 08H

Timer/Event Counter overflow 3 0CH

Time base interrupt 4 10H

Real time clock interrupt 5 14H

The EMI, EEI0, EEI1, ETI, ETBI and ERTI are all used to

control the enable/disable status of interrupts. These

bits prevent the requested interrupt from being serviced.

Once the interrupt request flags (RTF, TBF, TF, EIF1,

EIF0) are all set, they remain in the INTC1 or INTC0 re-

spectively until the interrupts are serviced or cleared by

a software instruction.

Bit No. Label Function

0 EMI Controls the master (global) interrupt (1=enabled; 0=disabled)

1 EEI0 Controls the external interrupt 0 (1=enabled; 0=disabled)

2 EEI1 Controls the external interrupt 1 (1=enabled; 0=disabled)

3 ETI Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)

4 EIF0 External interrupt 0 request flag (1=active; 0=inactive)

5 EIF1 External interrupt 1 request flag (1=active; 0=inactive)

6 TF Internal Timer/Event Counter request flag (1=active; 0=inactive)

7¾Unused bit, read as ²0²

INTC0 (0BH) Register

Bit No. Label Function

0 ETBI Controls the time base interrupt (1=enabled; 0:disabled)

1 ERTI Controls the real time clock interrupt (1=enabled; 0:disabled)

2, 3 ¾Unused bit, read as ²0²

4 TBF Time base request flag (1=active; 0=inactive)

5 RTF Real time clock request flag (1=active; 0=inactive)

6, 7 ¾Unused bit, read as ²0²

INTC1 (1EH) Register

HT49RA0/HT49CA0

Rev. 1.50 10 March 20, 2014

It is recommended that a program not use the ²CALL

subroutine²within the interrupt subroutine. It¢s because

interrupts often occur in an unpredictable manner or re-

quire to be serviced immediately in some applications.

At this time, if only one stack is left, and enabling the in-

terrupt is not well controlled, operation of the ²call²in the

interrupt subroutine may damage the original control se-

quence.

Oscillator Configuration

An external resistor between OSC1 and VSS in needed

and the resistance is about 12kW. The RC oscillator

provides a ±3% accuracy, the conditions are:

·VDD=2.0V~3.6V

·Temp.= 0°C~50°C

·fSYS=4MHz

R C O s c i l l a t o r

O S C 1

System Oscillator

LCD/RTC OSC Control Register

Two bit in (1FH) are for controlling LCD and RTC OSC.

Bit No. Label Function

0 RTCEN Controls RTC OSC enable (1=enabled; 0=disabled)

1 LCDEN Controls LCD enable (1=enabled; 0=disabled)

2~7 ¾Unused bit, read as ²0²

LCDC (1FH) Register

LCDEN and RTCEN may decide LCD and RTC On/Off condition on normal operation.

fSClock

Source

LCD/WDT Control Bits

LCDEN, RTCEN=0, 0 LCDEN, RTCEN=0, 1 LCDEN, RTCEN=1, 0 LCDEN, RTCEN=1, 1

fSYS/4 LCD off, RTC off LCD off, RTC off LCD on, RTC off LCD on, RTC off

WDT OSC LCD off, RTC off LCD off, RTC off LCD on, RTC off LCD on, RTC off

RTC OSC

(WDT enable) LCD off, RTC on LCD off, RTC on LCD on, RTC on LCD on, RTC on

RTC OSC

(WDT disable) LCD off, RTC off LCD off, RTC on LCD on, RTC on LCD on, RTC on

Ce manuel convient aux modèles suivants

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