Fujitsu F2MC-16LX Series Manuel utilisateur

FUJITSU SEMICONDUCTOR

CONTROLLER MANUAL

F2MC-16LX

16-BIT MICROCONTROLLER

MB90580 SERIES

HARDWARE MANUAL

查询MB90580供应商捷多邦，专业PCB打样工厂，24小时加急出货

iii

PREFACE

Thank you for selecting FUJITSU Semiconductor Devices.

The FUJITSU MB90580 series has been developed as one general-application version of the

F2MC®*16LX series of original 16-bit one-chip microcontrollers for ASIC (application specific

IC) applications. This manual describes the functions and operations of the MB90580 series,

and is intended for use by engineers actually designing products using these semiconductors.

Please be sure to read it carefully.

*: F2MC is an abbreviation for FUJITSU Flexible Microcontroller, and is a registered

trademark of Fujitsu.

This document is organized as follows.

Chapter 1 OVERVIEW

This section presents an overview of MB90580 series features and functions.

Chapter 2 CPU

This section describes the functions of the F2MC-16LX series CPU.

Chapter 3 MEMORY

This section describes the functions of the F2MC-16LX series memory.

Chapter 4 CLOCK AND RESET

This section describes the functions of the MB90580 series clocks and resets.

Chapter 5 WATCHDOG TIMER, TIME BASE TIMER, AND WATCH TIMER FUNCTION

This section describes the functions and operation of the MB90580 series watchdog timer,

timebase timer and watch timer function.

Chapter 6 LOW POWER CONTROL CIRCUIT

This section describes the MB90580 series low power control circuits (CPU intermittent

operation function, oscillator stabilization wait time, PLL clock multiplier function).

Chapter 7 INTERRUPT

This section describes the functions of each MB90580 each interrupt and interrupt source.

Chapter 8 PARALLEL PORTS

This section describes the functions of the MB90580 series parallel port.

Chapter 9 DTP/EXTERNAL INTERRUPT

This section describes the function and operation of the MB90580 series DTP and external

interrupts.

Chapter 10 DELAY INTERRUPT MODULE

This section describes the functions and operation of the MB90580 series delay interrupt

module.

Chapter 11

Chapter 12 COMMUNICATION PRESCALER

This section describes the MB90580 series communication prescaler.

Chapter 13 UART

This section describes the function and operation of the MB90580 UART.

Chapter 14 IE BUS

This section describes the functions and operation of the MB90580 series IE Bus.

Chapter 15 8/16-BIT PPG

This section describes the functions and operation of the MB90580 series 8/16-bit PPG.

Chapter 16 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)

This section describes the functions and operation of the MB90580 series 16-bit reload timer.

Chapter 17 A/D CONVERTERr

This section describes the functions and oeration of the MB90580 series A/D converter.

Chapter 18 D/A CONVERTER

This section describes the functions and oeration of the MB90580 series D/A converter

Chapter 19 PULSE WIDTH COUNTER (PWC) TIMER

This section describes the functions and oeration of the MB90580 series pulse width counter

(PWC) timer.

Chapter 20 CLOCK MONITOR FUNCTION

This section describes the functions of the MB90580 series clock monitor function.

Chapter 21 16-bit I/O Timers

This section describes the functions and operation of the MB90580 series 16-bit I/O timers which

consists of 16-bit free-run timer, 2 output compare regsiters and 4 input capture registers.

Chapter 22 ROM CORRECTION module

This section describes the function and operation of the MB90580 series rom correction module.

Chapter 23 ROM MIRRORING MODULE

This section describes the function of the MB90580 series ROM mirrorIing module.

Appendix A I/O MAP

The appendix A provides I/O maps, and low power mode status transition charts.

Appendix B INSTRUCTION

The appendix B describes addressing in the F2MC®*-16LX series, and provides instruction lists

and instruction maps.

Appendix C PROGRAMMING THE FLASH MEMORY ON THE MB90F584

The appendix C provides programming method of the flash memory on the MB90F584.

MB90580 Series v

CONTENTS

Chapter 1 Overview ...........................................................................................................................................1

1.1 Features ..........................................................................................................................................1

1.2 Product Lineup ................................................................................................................................3

1.3 Block Diagram .................................................................................................................................4

1.4 Pin Assignment ...............................................................................................................................5

1.4.1 SQFP-100 Pin Assignment ....................................................................................................5

1.4.1 QFP-100 Pin Assignment ......................................................................................................6

1.5 Pin Functions ..................................................................................................................................7

1.6 Handling the Device ......................................................................................................................14

Chapter 2 CPU ..................................................................................................................................................15

2.1 CPU ...............................................................................................................................................15

2.1.1 Memory space .....................................................................................................................16

2.1.2 Registers .............................................................................................................................20

2.1.3 Prefix codes .........................................................................................................................28

Chapter 3 Memory ............................................................................................................................................31

3.1 Memory Access Modes .................................................................................................................31

3.1.1 Mode pins ............................................................................................................................32

3.1.2 Mode data ............................................................................................................................33

3.1.3 Bus Mode ............................................................................................................................34

3.2 External Memory Access ...............................................................................................................36

3.2.1 Block diagram ......................................................................................................................36

3.2.2 Registers and Register details .............................................................................................37

3.2.1 Operations ...........................................................................................................................42

Chapter 4 Clock and Reset ..............................................................................................................................47

4.1 Clock Generator ............................................................................................................................47

4.2 Reset Causes ................................................................................................................................48

4.3 Operation after reset release ........................................................................................................50

Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions ...............................................51

5.1 Outline ...........................................................................................................................................51

5.2 Block diagram ...............................................................................................................................52

5.3 Registers and register details ........................................................................................................53

5.3.1 WDTC (Watch-Dog Timer Control Register) .......................................................................54

5.3.2 TBTC (Time Base Timer Control Register) .........................................................................56

5.3.3 Watch Timer Control Register (WTC) ..................................................................................57

5.4 Operation ......................................................................................................................................59

5.4.1 Watch-Dog Timer ................................................................................................................59

5.4.2 Time Base Timer .................................................................................................................60

5.4.3 Watch Timer ........................................................................................................................60

Chapter 6 Low Power Control Circuit .............................................................................................................61

6.1 Outline ...........................................................................................................................................61

6.2 Block Diagram ...............................................................................................................................62

6.3 Registers and register details ........................................................................................................63

6.3.1 LPMCR (Low power mode control register) ........................................................................63

6.3.2 CKSCR (Clock selection register) .......................................................................................65

6.4 Operations .....................................................................................................................................67

6.4.1 Sleep mode .........................................................................................................................68

6.4.2 Pseudo-watch mode ............................................................................................................68

vi MB90580 Series

6.4.3 Watch mode ........................................................................................................................69

6.4.4 Stop mode ...........................................................................................................................69

6.4.5 Hardware standby mode .....................................................................................................70

6.4.6 CPU intermittent operation function .....................................................................................70

6.4.7 Setting the main clock oscillation stabilization waiting period ..............................................71

6.4.8 Switching the machine clock ...............................................................................................71

6.4.9 State transition .....................................................................................................................73

Chapter 7 Interrupt ...........................................................................................................................................81

7.1 Outline ...........................................................................................................................................81

7.2 Causes of Interrupt ........................................................................................................................82

7.3 Interrupt Vector .............................................................................................................................83

7.4 Hardware Interrupt ........................................................................................................................84

7.4.1 Overview ..............................................................................................................................84

7.4.2 Structure ..............................................................................................................................84

7.4.3 Operation .............................................................................................................................84

7.4.4 Hardware Interrupt Ocurrence When Internal Resource Is Being Accessed ......................87

7.4.5 Interrupt Inhibit Instruction ...................................................................................................87

7.4.6 Multiple Interrupts ................................................................................................................87

7.4.7 Register Saving In Stack Upon Interrupt .............................................................................87

7.4.8 Precaution in Using Hardware Interrupt ..............................................................................87

7.5 Software Interrupt ..........................................................................................................................88

7.5.1 Overview ..............................................................................................................................88

7.5.2 Structure ..............................................................................................................................88

7.5.3 Operation .............................................................................................................................89

7.5.4 Others ..................................................................................................................................89

7.6 Extended intelligent I/O service (EI2OS) .......................................................................................90

7.6.1 Overview ..............................................................................................................................90

7.6.2 Structure ..............................................................................................................................91

7.6.3 Operation .............................................................................................................................97

7.6.4 EI2OS Execution Time ........................................................................................................99

7.7 Exceptions ...................................................................................................................................100

7.7.1 Exception due to execution of an undefined instruction ....................................................100

Chapter 8 Parallel Ports .................................................................................................................................101

8.1 Outline .........................................................................................................................................101

8.2 Block Diagram .............................................................................................................................102

8.3 Registers and register details ......................................................................................................103

8.3.1 Port data register ...............................................................................................................104

8.3.2 Port direction registers .......................................................................................................105

8.3.3 Output pin register .............................................................................................................106

8.3.4 Input resistor register .........................................................................................................106

8.3.5 Analogue Input Enable Register ........................................................................................107

8.3.6 Low Noise Output Select Register .....................................................................................107

Chapter 9 DTP/External Interrupt ..................................................................................................................109

9.1 Outline .........................................................................................................................................109

9.2 Block Diagram .............................................................................................................................109

9.3 Registers and Register Details ....................................................................................................110

9.3.1 Interrupt/DTP enable register (ENIR: Enable interrupt request register) ...........................110

9.3.2 Interrupt/DTP cause register (EIRR: External interrupt request register) ..........................111

9.3.3 Request level setting register (ELVR: External level register) ...........................................111

MB90580 Series vii

9.4 Operations ...................................................................................................................................112

9.4.1 External interrupts .............................................................................................................112

9.4.2 DTP operation ...................................................................................................................113

9.4.3 Switching between external interrupt and DTP requests ...................................................114

9.5 Notes on use ...............................................................................................................................115

9.5.1 Conditions on the externally connected peripheral when DTP is used .............................115

9.5.2 Recovery from standby ......................................................................................................115

9.5.3 External interrupt/DTP operation procedure ......................................................................115

9.5.4 External interrupt request level ..........................................................................................115

Chapter 10 Delayed Interrupt Generation Module .......................................................................................117

10.1 Outline .......................................................................................................................................117

10.2 Block Diagram ...........................................................................................................................117

10.3 Registers and Register Details ..................................................................................................117

10.4 Operations .................................................................................................................................118

10.4.1 Delayed interrupt occurrence ..........................................................................................118

10.5 Notes on operation ....................................................................................................................118

10.5.1 Delayed interrupt request lock .........................................................................................118

Chapter 11 Communication Prescaler ..........................................................................................................119

11.1 Outline .......................................................................................................................................119

11.2 Block Diagram ...........................................................................................................................119

11.3 Register and Register Details ....................................................................................................120

11.3.1 Clock Division Control Registers .....................................................................................120

11.4 Operations .................................................................................................................................121

Chapter 12 UART ............................................................................................................................................123

12.1 Outline .......................................................................................................................................123

12.2 Block Diagram ...........................................................................................................................124

12.3 Register and Register Details ....................................................................................................125

12.3.1 Serial Mode Register (SMR0/1/2/3/4) ..............................................................................126

12.3.2 Serial Control Register (SCR0/1/2/3/4) ...........................................................................128

12.3.3 Serial Input Data Register (SIDR0/1/2/3/4)/ Serial Ouput Data Register (SODR0/1/2/3/4) 130

12.3.4 Serial Status Register (SSR0/1/2/3/4) .............................................................................130

12.4 Operations .................................................................................................................................132

12.4.1 Operation modes .............................................................................................................132

12.4.2 UART clock selection ......................................................................................................132

12.4.3 Asynchronous mode ........................................................................................................134

12.4.4 CLK synchronous mode ..................................................................................................135

12.4.5 Interrupt occurrence and flag set timing ..........................................................................137

12.4.6 I2OS (Intelligent I/O service) ...........................................................................................139

12.4.7 Notes on use ..................................................................................................................139

12.4.8 Application .......................................................................................................................139

Chapter 13 IE Bus ...........................................................................................................................................141

13.1 Outline .......................................................................................................................................141

13.2 Block Diagram ...........................................................................................................................142

13.3 Registers and Register Details ..................................................................................................143

13.3.1 Command register upper byte (CMRH) ...........................................................................146

13.3.2 Command register lower byte (CMRL) ............................................................................148

13.3.3 Unit address register (MAWH, MAWL) ............................................................................150

13.3.4 Slave address register (SAWH, SAWL) ..........................................................................150

13.3.5 Mutliaddress, control bit set register (DCWR) .................................................................151

viii MB90580 Series

13.3.6 Telegraph length set register (DEWR) ............................................................................152

13.3.7 Status register upper byte (STRH) ..................................................................................153

13.3.8 Status register lower byte (STRL) ...................................................................................155

13.3.9 Lock read register (LRRH, LRRL) ...................................................................................157

13.3.10 Master address read register (MARH, MARL) ...............................................................158

13.3.11 Multiaddress, control bit read register (DCRR) ..............................................................159

13.3.12 Telegraph length read register (DERR) .........................................................................160

13.3.13 Read data buffer (RDB) .................................................................................................161

13.3.14 Write data buffer (WDB) ................................................................................................162

13.4 IEBus Communication Protocol ................................................................................................163

13.4.1 Overview ..........................................................................................................................163

13.4.2 Determining bus mastership (arbitration) ........................................................................164

13.4.3 Communication mode ......................................................................................................164

13.4.4 Communication address ..................................................................................................165

13.4.5 Multiaddress communication ...........................................................................................165

13.4.6 Transfer protocol .............................................................................................................166

13.4.7 Transmit data ...................................................................................................................170

13.4.8 Bit format .........................................................................................................................173

13.5 Operation ..................................................................................................................................174

13.5.1 IEBus control ...................................................................................................................174

13.5.2 Communication status .....................................................................................................177

13.5.3 Program flow example for IEBus controller .....................................................................179

13.5.4 Timing Diagram of Multiple Frame Transmission ............................................................186

13.5.5 Timing diaram of transmission data when an error is generated .....................................188

Chapter 14 8/16-Bit PPG ................................................................................................................................191

14.1 Outline .......................................................................................................................................191

14.2 Block Diagram ...........................................................................................................................192

14.3 Registers and Register Details ..................................................................................................194

14.3.1 PPG0 operation mode control register (PPGC0) ............................................................195

14.3.2 PPG1 operation mode control register (PPGC1) .............................................................197

14.3.3 PPG0, 1 output pin control register (PPGOE) .................................................................199

14.3.4 Reload register (PRLL/PRLH ) ........................................................................................200

14.4 Operations .................................................................................................................................201

Chapter 15 16-Bit Reload Timer (with Event Count Function) ...................................................................207

15.1 Outline .......................................................................................................................................207

15.2 Block Diagram ...........................................................................................................................208

15.3 Registers and Register Details ..................................................................................................209

15.3.1 Timer control status register (TMCSR) ............................................................................210

15.3.2 TMR (16-bit timer register)/TMRLR (16-bit reload register) .............................................213

15.4 Operation ..................................................................................................................................214

15.4.1 Internal clock operation ...................................................................................................214

15.4.2 Underflow operation ........................................................................................................215

15.4.3 Input pin functions (for internal clock mode) ....................................................................216

15.4.4 External event counter .....................................................................................................216

15.4.5 Output pin functions .........................................................................................................217

15.4.6 Intelligent I/O service (I2OS) function and interrupts .......................................................217

15.4.7 Counter operation state ...................................................................................................218

Chapter 16 A/D Converter ..............................................................................................................................219

16.1 Outline .......................................................................................................................................219

16.2 Block Diagram ...........................................................................................................................220

MB90580 Series ix

16.3 Registers and Register Details ..................................................................................................221

16.3.1 Control status registers (ADCS1 and ADCS2) ................................................................222

16.3.2 ADCR1 and ADCR0 (Data registers) ..............................................................................226

16.4 Operations .................................................................................................................................228

16.5 Notes on use .............................................................................................................................234

16.5.1 Other considerations ......................................................................................................234

Chapter 17 D/A Converter ..............................................................................................................................235

17.1 Outline .......................................................................................................................................235

17.2 Block Diagram ...........................................................................................................................236

17.3 Registers and Register Details ..................................................................................................237

17.3.1 DAT0/1 ( D/A data register) .............................................................................................238

17.3.2 DACR0/1 ( D/A control register) ......................................................................................238

17.4 Operations .................................................................................................................................239

Chapter 18 Pulse Width Counter (PWC) Timer ............................................................................................241

18.1 Outline .......................................................................................................................................241

18.2 Block Diagram ...........................................................................................................................242

18.3 Regiaters and Register Details ..................................................................................................243

18.3.1 PWC control status register (PWCSR) ............................................................................244

18.3.2 PWC data buffer register (PWCR) ...................................................................................249

18.3.3 Divide Ratio Control Register (DIVR) ..............................................................................250

18.3.4 PWC noise cancelling register (RNCR) ...........................................................................251

18.4 Operations .................................................................................................................................252

18.5 Precautions ...............................................................................................................................265

Chapter 19 Clock Monitor Function ..............................................................................................................267

19.1 Outline .......................................................................................................................................267

19.2 Block Diagram ...........................................................................................................................267

19.3 Registers and Register Details ..................................................................................................268

19.3.1 Clock output enable register (CLKR) ...............................................................................268

Chapter 20 16-Bit I/O Timer ...........................................................................................................................269

20.1 Outline .......................................................................................................................................269

20.2 Block Diagram ...........................................................................................................................271

20.2.1 Overall Block Diagram of 16-bit I/O Timer .......................................................................271

20.2.2 Block Diagram of 16-bit free-run timer .............................................................................272

20.2.3 Block Diagram of Output Comparison .............................................................................272

20.2.4 Block Diagram of Input Capture ......................................................................................273

20.3 Registers and Register Details ..................................................................................................274

20.3.1 16-bit free-run timer .........................................................................................................274

20.3.2 Output comparison ..........................................................................................................278

20.3.3 Input capture ....................................................................................................................282

20.4 Operations .................................................................................................................................285

20.4.1 16-bit free-run timer .........................................................................................................285

20.4.2 16-bit output compare ......................................................................................................286

20.4.3 16-bit input capture ..........................................................................................................287

20.5 Timing .......................................................................................................................................288

20.5.1 16-bit free-run timer count timing .....................................................................................288

20.5.2 Output compare timing ....................................................................................................289

20.5.3 Input capture input timing ................................................................................................290

Chapter 21 ROM Correction Module .............................................................................................................291

21.1 Outline .......................................................................................................................................291

x MB90580 Series

21.2 Block Diagram ...........................................................................................................................291

21.3 Registers and Register Details ..................................................................................................292

21.3.1 Program Address Detect Register 0/1 (PADR0/PADR1) ................................................292

21.3.2 Program Address detect Control Status Register (PACSR) ............................................293

21.4 Operations .................................................................................................................................294

21.5 Application Example ..................................................................................................................295

Chapter 22 ROM Mirroring Module ...............................................................................................................299

22.1 Outline .......................................................................................................................................299

22.2 Block Diagram ...........................................................................................................................299

22.3 Registers and Register Details ..................................................................................................300

22.3.1 ROM Mirror Function Select Register ..............................................................................300

Appendix A I/O Map........................................................................................................................................ 303

A.1 I/O Map .......................................................................................................................................303

Appendix B Instructions................................................................................................................................ 309

B.1 Addressing ..................................................................................................................................309

B.1.1 Effective address field .......................................................................................................309

B.1.2 Addressing Details ............................................................................................................310

B.2 Instruction Set .............................................................................................................................314

B.2.1 F2MC-16LX Instruction Set (351 Instructions) ..................................................................320

B.3 Instruction Map ...........................................................................................................................334

B.3.1 Basic Page Map ................................................................................................................336

Appendix C The Flash Memory in the MB90F583........................................................................................ 357

C.1 Outline ........................................................................................................................................357

C.2 Sector Structure of 1M Bit Flash Memory ...................................................................................358

C.3 Flash Control Register (FMCS) ..................................................................................................359

C.4 Automatic Algorithm Initiation Method ........................................................................................361

C.5 Automatic Algorithm Execution Status .......................................................................................362

C.5.1 Data polling flag (DQ7) .....................................................................................................363

C.5.2 Toggle bit flag (DQ6) .........................................................................................................364

C.5.3 Exceeded timing limits flag (DQ5) .....................................................................................365

C.5.4 Sector erase timer flag (DQ3) ...........................................................................................366

C.6 Notes on Flash Memory Program/Erase ....................................................................................367

C.6.1 Read/reset status ..............................................................................................................367

C.6.2 Data Programming ............................................................................................................368

C.6.3 Chip Erase ........................................................................................................................370

C.6.4 Sector Erase .....................................................................................................................370

C.6.5 Suspend Sector Erase ......................................................................................................372

C.6.6 Resume Sector Erase .......................................................................................................372

Autres manuels pour F2MC-16LX Series

Ce manuel convient aux modèles suivants

Table des matières

Autres manuels Fujitsu Microcontrôleur

Fujitsu

Fujitsu MB95100 Series Instructions d'installation et d'utilisation

Fujitsu

Fujitsu UTY-TFNXZ1 Manuel de service

Fujitsu

Fujitsu MB95350L Series Instructions d'installation et d'utilisation

Fujitsu

Fujitsu BBF2004 Series Manuel utilisateur

Fujitsu

Fujitsu ALL FR 460 Series Instructions d'installation et d'utilisation

Fujitsu

Fujitsu FR Family Manuel utilisateur

Fujitsu

Fujitsu F2MC-8FX Series Manuel utilisateur

Fujitsu

Fujitsu FR Series Instructions d'installation et d'utilisation

Fujitsu

Fujitsu F2MC-16LX Series Instructions d'installation et d'utilisation

Fujitsu

Fujitsu MB86R01 Instructions d'installation et d'utilisation

Fujitsu

Fujitsu F2MC-FR Series Instructions d'installation et d'utilisation

Fujitsu

Fujitsu F2MC-16L Series Manuel utilisateur

Fujitsu

Fujitsu MB91150 Series Manuel utilisateur

Fujitsu

Fujitsu F2MC-8FX MB95200H/210H Series Instructions d'installation et d'utilisation

Fujitsu

Fujitsu F2MC-8FX Series Manuel utilisateur

Fujitsu

Fujitsu F2MC-8FX Series Manuel utilisateur

Fujitsu

Fujitsu F2MC-16LX Series Manuel utilisateur

Fujitsu

Fujitsu MB95630H Series Manuel utilisateur

Fujitsu

Fujitsu F2MC-8FX Series Instructions d'installation et d'utilisation

Fujitsu

Fujitsu F2MC-8FX MB95200H/210H Series Instructions d'installation et d'utilisation

Fujitsu

Fujitsu MB90M405 Manuel utilisateur

Fujitsu

Fujitsu MB91260B Series Manuel utilisateur

Fujitsu

Fujitsu F2MC-8L Series Instructions d'installation et d'utilisation

Fujitsu

Fujitsu MB88121 SERIES Instructions d'installation et d'utilisation

Manuels Microcontrôleur populaires d'autres marques

AMS

AMS AS7261 Demo Kit Manuel utilisateur

Novatek

Novatek NT6861 Manuel utilisateur

Espressif Systems

Espressif Systems ESP8266 SDK Guide de configuration

Nuvoton

Nuvoton ISD61S00 ChipCorder Mode d’emploi

STMicrolectronics

STMicrolectronics ST7 Assembler Linker Manuel utilisateur

Texas Instruments

Texas Instruments Chipcon CC2420DK Manuel utilisateur

Lantronix

Lantronix Intrinsyc Open-Q 865XR SOM Manuel utilisateur

NEC

NEC 78GK0S/K 1+ Series Instructions d'installation et d'utilisation

Mikroe

Mikroe SEMITECH N-PLC Click Instructions d'installation et d'utilisation

Intel

Intel Agilex Manuel utilisateur

Cypress

Cypress CY4607 HX2VL Manuel utilisateur

DIGITAL-LOGIC

DIGITAL-LOGIC MICROSPACE Manuel utilisateur

Texas Instruments

Texas Instruments TMS320F2837 D Series Manuel utilisateur

CYPRES

CYPRES CY14NVSRAMKIT-001 Manuel utilisateur

Texas Instruments

Texas Instruments INA-DUAL-2AMP-EVM Manuel utilisateur

Espressif Systems

Espressif Systems ESP8266EX Mode d'emploi

Abov

Abov AC33M8128L Manuel utilisateur

Laird

Laird BL654PA Manuel utilisateur