Freescale Semiconductor MPC561 Manuel utilisateur

MPC561/MPC563 Reference Manual

Additional Devices Supported:

MPC562

MPC564

MPC561RM

REV 1.2

08/2005

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

suppor[email protected]

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

+1-800-521-6274 or +1-480-768-2130

suppor[email protected]

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

suppor[email protected]

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064, Japan

0120 191014 or +81 3 5437 9125

suppor[email protected]

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

+800 26668334

suppor[email protected]

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconduc[email protected]

Information in this document is provided solely to enable system and

software implementers to use Freescale Semiconductor products. There are

no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits or integrated circuits based on the

information in this document.

Freescale Semiconductor reserves the right to make changes without further

notice to any products herein. Freescale Semiconductor makes no warranty,

representation or guarantee regarding the suitability of its products for any

particular purpose, nor does Freescale Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or

incidental damages. “Typical” parameters that may be provided in Freescale

Semiconductor data sheets and/or specifications can and do vary in different

applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer

application by customer’s technical experts. Freescale Semiconductor does

not convey any license under its patent rights nor the rights of others.

Freescale Semiconductor products are not designed, intended, or authorized

for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other

application in which the failure of the Freescale Semiconductor product could

create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold Freescale

Semiconductor and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized

use, even if such claim alleges that Freescale Semiconductor was negligent

regarding the design or manufacture of the part.

Freescale™ and the Freescale logo are trademarks of Freescale

Semiconductor, Inc. All other product or service names are the property

of their respective owners. The described product is a PowerPC

microprocessor. The PowerPC name is a trademark of IBM Corp. and used

under license

MPC561RM

REV 1.2

08/2005

MPC561/MPC563 Reference Manual, Rev. 1.2

Freescale Semiconductor iii

Paragraph

Number Title Page

Number

About This Book lxxvii

Audience ..................................................................................................................... lxxvii

Organization ................................................................................................................ lxxvii

Suggested Reading ........................................................................................................ lxxx

Conventions and Nomenclature .................................................................................... lxxx

Notational Conventions ............................................................................................... lxxxi

Acronyms and Abbreviations ..................................................................................... lxxxii

References .................................................................................................................. lxxxiii

Chapter 1

Overview

1.1 Introduction ..................................................................................................................... 1-1

1.2 Block Diagram ................................................................................................................ 1-2

1.3 Key Features ................................................................................................................... 1-3

1.3.1 High-Performance CPU System ................................................................................. 1-3

1.3.1.1 RISC MCU Central Processing Unit (RCPU) ........................................................ 1-4

1.3.1.2 Unified System Interface Unit (USIU) ................................................................... 1-4

1.3.1.3 Burst Buffer Controller (BBC) Module .................................................................. 1-4

1.3.1.4 Flexible Memory Protection Unit ........................................................................... 1-5

1.3.1.5 Memory Controller ................................................................................................. 1-5

1.3.1.6 512-Kbytes of CDR3 Flash EEPROM Memory (UC3F) –

MPC563/MPC564 Only 1-5

1.3.1.7 32-Kbyte Static RAM (CALRAM) ........................................................................ 1-6

1.3.1.8 General Purpose I/O Support (GPIO) ..................................................................... 1-6

1.3.2 Nexus Debug Port (Class 3) ........................................................................................ 1-6

1.3.3 Integrated I/O System ................................................................................................. 1-6

1.3.3.1 Two Time Processor Units (TPU3) ........................................................................ 1-6

1.3.3.2 22-Channel Modular I/O System (MIOS14) .......................................................... 1-6

1.3.3.3 Two Enhanced Queued Analog-to-Digital Converter Modules (QADC64E) ........ 1-7

1.3.3.4 Three CAN 2.0B Controller (TouCAN) Modules .................................................. 1-7

1.3.3.5 Queued Serial Multi-Channel Module (QSMCM) ................................................. 1-8

1.3.3.6 Peripheral Pin Multiplexing (PPM) ........................................................................ 1-8

1.4 MPC561/MPC563 Optional Features ............................................................................. 1-9

1.5 Comparison of MPC561/MPC563 and MPC555 ........................................................... 1-9

1.6 Additional MPC561/MPC563 Differences ................................................................... 1-10

1.7 SRAM Keep-Alive Power Behavior ............................................................................. 1-11

1.8 MPC561/MPC563 Address Map .................................................................................. 1-11

Contents

MPC561/MPC563 Reference Manual, Rev. 1.2

Freescale Semiconductor iv

Contents

Paragraph

Number Title Page

Number

1.9 Supporting Documentation List .................................................................................... 1-14

Chapter 2

Signal Descriptions

2.1 Signal Groupings ............................................................................................................2-1

2.2 Signal Summary ..............................................................................................................2-3

2.2.1 MPC561/MPC563 Signal Multiplexing ................................................................... 2-20

2.2.2 READI Port Signal Sharing ...................................................................................... 2-21

2.3 Pad Module Configuration Register (PDMCR) ............................................................ 2-22

2.4 Pad Module Configuration Register (PDMCR2) .......................................................... 2-23

2.5 MPC561/MPC563 Development Support Signal Sharing ............................................ 2-28

2.5.1 JTAG Mode Selection .............................................................................................. 2-29

2.5.2 BDM Mode Selection ............................................................................................... 2-30

2.5.3 Nexus Mode Selection .............................................................................................. 2-30

2.6 Reset State ..................................................................................................................... 2-31

2.6.1 Signal Functionality Configuration Out of Reset ..................................................... 2-31

2.6.2 Signal State During Reset ......................................................................................... 2-31

2.6.3 Power-On Reset and Hard Reset .............................................................................. 2-32

2.6.4 Pull-Up/Pull-Down ................................................................................................... 2-32

2.6.4.1 Pull-Up/Pull-Down Enable and Disable for 5-V Only and 2.6-V Only Signals .. 2-32

2.6.4.2 Pull-Down Enable and Disable for 5-V/2.6-V Multiplexed Signals .................... 2-32

2.6.4.3 Special Pull Resistor Disable Control Functionality (SPRDS) ............................ 2-32

2.6.4.4 Pull Device Select (PULL_SEL) .......................................................................... 2-33

2.6.5 Signal Reset States .................................................................................................... 2-33

Chapter 3

Central Processing Unit

3.1 RCPU Block Diagram .................................................................................................... 3-1

3.2 RCPU Key Features ........................................................................................................ 3-3

3.3 Instruction Sequencer ..................................................................................................... 3-3

3.4 Independent Execution Units .......................................................................................... 3-4

3.4.1 Branch Processing Unit (BPU) ................................................................................... 3-5

3.4.2 Integer Unit (IU) .........................................................................................................3-5

3.4.3 Load/Store Unit (LSU) ............................................................................................... 3-6

3.4.4 Floating-Point Unit (FPU) .......................................................................................... 3-6

3.5 Levels of the PowerPC ISA Architecture ....................................................................... 3-6

3.6 RCPU Programming Model ............................................................................................ 3-7

MPC561/MPC563 Reference Manual, Rev. 1.2

Freescale Semiconductor v

Contents

Paragraph

Number Title Page

Number

3.7 User Instruction Set Architecture (UISA)

Register Set ............................................................................................................... 3-12

3.7.1 General-Purpose Registers (GPRs) ........................................................................... 3-12

3.7.2 Floating-Point Registers (FPRs) ............................................................................... 3-12

3.7.3 Floating-Point Status and Control Register (FPSCR) .............................................. 3-13

3.7.4 Condition Register (CR) ........................................................................................... 3-16

3.7.4.1 Condition Register CR0 Field Definition ............................................................. 3-17

3.7.4.2 Condition Register CR1 Field Definition ............................................................. 3-17

3.7.4.3 Condition Register CRn Field — Compare Instruction ....................................... 3-17

3.7.5 Integer Exception Register (XER) ............................................................................ 3-18

3.7.6 Link Register (LR) .................................................................................................... 3-19

3.7.7 Count Register (CTR) ............................................................................................... 3-19

3.8 VEA Register Set — Time Base (TB) .......................................................................... 3-20

3.9 OEA Register Set .......................................................................................................... 3-20

3.9.1 Machine State Register (MSR) ................................................................................. 3-20

3.9.2 DAE/Source Instruction Service Register (DSISR) ................................................. 3-22

3.9.3 Data Address Register (DAR) .................................................................................. 3-23

3.9.4 Time Base Facility (TB) — OEA ............................................................................. 3-23

3.9.5 Decrementer Register (DEC) .................................................................................... 3-23

3.9.6 Machine Status Save/Restore Register 0 (SRR0) ..................................................... 3-23

3.9.7 Machine Status Save/Restore Register 1 (SRR1) ..................................................... 3-23

3.9.8 General SPRs (SPRG0–SPRG3) .............................................................................. 3-24

3.9.9 Processor Version Register (PVR) ........................................................................... 3-25

3.9.10 Implementation-Specific SPRs ................................................................................. 3-25

3.9.10.1 EIE, EID, and NRI Special-Purpose Registers ..................................................... 3-25

3.9.10.2 Floating-Point Exception Cause Register (FPECR) ............................................. 3-26

3.9.10.3 Additional Implementation-Specific Registers ..................................................... 3-27

3.10 Instruction Set ............................................................................................................... 3-27

3.10.1 Instruction Set Summary .......................................................................................... 3-28

3.10.2 Recommended Simplified Mnemonics ..................................................................... 3-33

3.10.3 Calculating Effective Addresses ............................................................................... 3-34

3.11 Exception Model ........................................................................................................... 3-34

3.11.1 Exception Classes ..................................................................................................... 3-35

3.11.2 Ordered Exceptions ................................................................................................... 3-35

3.11.3 Unordered Exceptions ............................................................................................... 3-35

3.11.4 Precise Exceptions .................................................................................................... 3-36

3.11.5 Exception Vector Table ............................................................................................ 3-36

3.12 Instruction Timing ........................................................................................................ 3-37

3.13 User Instruction Set Architecture (UISA) .................................................................... 3-39

3.13.1 Computation Modes .................................................................................................. 3-39

3.13.2 Reserved Fields ......................................................................................................... 3-39

MPC561/MPC563 Reference Manual, Rev. 1.2

Freescale Semiconductor vi

Contents

Paragraph

Number Title Page

Number

3.13.3 Classes of Instructions .............................................................................................. 3-40

3.13.4 Exceptions ................................................................................................................. 3-40

3.13.5 Branch Processor ...................................................................................................... 3-40

3.13.6 Instruction Fetching .................................................................................................. 3-40

3.13.7 Branch Instructions ................................................................................................... 3-40

3.13.7.1 Invalid Branch Instruction Forms ......................................................................... 3-40

3.13.7.2 Branch Prediction ................................................................................................. 3-40

3.13.8 Fixed-Point Processor ............................................................................................... 3-41

3.13.8.1 Fixed-Point Instructions ........................................................................................ 3-41

3.13.9 Floating-Point Processor ........................................................................................... 3-41

3.13.9.1 General .................................................................................................................. 3-41

3.13.9.2 Optional Instructions ............................................................................................ 3-41

3.13.10 Load/Store Processor ................................................................................................ 3-42

3.13.10.1 Fixed-Point Load with Update and Store with Update Instructions ..................... 3-42

3.13.10.2 Fixed-Point Load and Store Multiple Instructions ............................................... 3-42

3.13.10.3 Fixed-Point Load String Instructions .................................................................... 3-42

3.13.10.4 Storage Synchronization Instructions ................................................................... 3-42

3.13.10.5 Floating-Point Load and Store With Update Instructions .................................... 3-42

3.13.10.6 Floating-Point Load Single Instructions ............................................................... 3-42

3.13.10.7 Floating-Point Store Single Instructions ............................................................... 3-42

3.13.10.8 Optional Instructions ............................................................................................ 3-43

3.14 Virtual Environment Architecture (VEA) .................................................................... 3-43

3.14.1 Atomic Update Primitives ........................................................................................ 3-43

3.14.2 Effect of Operand Placement on Performance ......................................................... 3-43

3.14.3 Storage Control Instructions ..................................................................................... 3-43

3.14.4 Instruction Synchronize (isync) Instruction .............................................................. 3-43

3.14.5 Enforce In-Order Execution of I/O (eieio) Instruction ............................................. 3-44

3.14.6 Time Base ................................................................................................................. 3-44

3.15 Operating Environment Architecture (OEA) ................................................................ 3-44

3.15.1 Branch Processor Registers ...................................................................................... 3-44

3.15.1.1 Machine State Register (MSR) ............................................................................. 3-44

3.15.1.2 Branch Processors Instructions ............................................................................. 3-44

3.15.2 Fixed-Point Processor ............................................................................................... 3-44

3.15.2.1 Special Purpose Registers ..................................................................................... 3-44

3.15.3 Storage Control Instructions ..................................................................................... 3-45

3.15.4 Exceptions ................................................................................................................. 3-45

3.15.4.1 System Reset Exception and NMI (0x0100) ........................................................ 3-45

3.15.4.2 Machine Check Exception (0x0200) .................................................................... 3-46

3.15.4.3 Data Storage Exception (0x0300) ......................................................................... 3-48

3.15.4.4 Instruction Storage Exception (0x0400) ............................................................... 3-48

3.15.4.5 External Interrupt (0x0500) .................................................................................. 3-48

MPC561/MPC563 Reference Manual, Rev. 1.2

Freescale Semiconductor vii

Contents

Paragraph

Number Title Page

Number

3.15.4.6 Alignment Exception (0x00600) .......................................................................... 3-49

3.15.4.7 Program Exception (0x0700) ................................................................................ 3-51

3.15.4.8 Floating-Point Unavailable Exception (0x0800) .................................................. 3-52

3.15.4.9 Decrementer Exception (0x0900) ......................................................................... 3-53

3.15.4.10 System Call Exception (0x0C00) ......................................................................... 3-54

3.15.4.11 Trace Exception (0x0D00) ................................................................................... 3-54

3.15.4.12 Floating-Point Assist Exception (0x0E00) ........................................................... 3-55

3.15.4.13 Implementation-Dependent Software Emulation Exception (0x1000) ................ 3-56

3.15.4.14 Implementation-Dependent Instruction Protection Exception (0x1300) .............. 3-57

3.15.4.15 Implementation-Specific Data Protection Error Exception (0x1400) .................. 3-58

3.15.4.16 Implementation-Dependent Debug Exceptions .................................................... 3-59

3.15.5 Partially Executed Instructions ................................................................................. 3-60

3.15.6 Timer Facilities .........................................................................................................3-61

3.15.7 Optional Facilities and Instructions .......................................................................... 3-61

Chapter 4

Burst Buffer Controller 2 Module

4.1 Key Features ................................................................................................................... 4-2

4.1.1 BIU Key Features ....................................................................................................... 4-2

4.1.2 IMPU Key Features .................................................................................................... 4-3

4.1.3 ICDU Key Features .................................................................................................... 4-3

4.1.4 DECRAM Key Features ............................................................................................. 4-4

4.1.5 Branch Target Buffer Key Features ............................................................................ 4-4

4.2 Operation Modes .............................................................................................................4-4

4.2.1 Instruction Fetch .........................................................................................................4-4

4.2.1.1 Decompression Off Mode ....................................................................................... 4-4

4.2.1.2 Decompression On Mode ....................................................................................... 4-5

4.2.2 Burst Operation of the BBC ........................................................................................ 4-5

4.2.3 Access Violation Detection ........................................................................................ 4-5

4.2.4 Slave Operation ...........................................................................................................4-6

4.2.5 Reset Behavior ............................................................................................................4-6

4.2.6 Debug Operation Mode .............................................................................................. 4-7

4.3 Exception Table Relocation (ETR) ................................................................................. 4-7

4.3.1 ETR Operation ............................................................................................................ 4-8

4.3.2 Enhanced External Interrupt Relocation (EEIR) ...................................................... 4-10

4.4 Decompressor RAM (DECRAM) Functionality .......................................................... 4-12

4.4.1 General-Purpose Memory Operation ........................................................................ 4-13

4.4.1.1 Memory Protection Violations ............................................................................. 4-14

4.4.1.2 DECRAM Standby Operation Mode .................................................................... 4-14

4.5 Branch Target Buffer .................................................................................................... 4-14

MPC561/MPC563 Reference Manual, Rev. 1.2

Freescale Semiconductor viii

Contents

Paragraph

Number Title Page

Number

4.5.1 BTB Operation .......................................................................................................... 4-14

4.5.1.1 BTB Invalidation .................................................................................................. 4-16

4.5.1.2 BTB Enabling/Disabling ...................................................................................... 4-16

4.5.1.3 BTB Inhibit Regions ............................................................................................. 4-16

4.6 BBC Programming Model ............................................................................................ 4-17

4.6.1 Address Map ............................................................................................................. 4-17

4.6.1.1 BBC Special Purpose Registers (SPRs) ............................................................... 4-17

4.6.1.2 DECRAM and DCCR Block ................................................................................ 4-18

4.6.2 BBC Register Descriptions ....................................................................................... 4-19

4.6.2.1 BBC Module Configuration Register (BBCMCR) ............................................... 4-19

4.6.2.2 Region Base Address Registers (MI_RBA[0:3]) ................................................. 4-21

4.6.2.3 Region Attribute Registers (MI_RA[0:3]) ............................................................ 4-22

4.6.2.4 Global Region Attribute Register (MI_GRA) ...................................................... 4-23

4.6.2.5 External Interrupt Relocation Table Base Address Register (EIBADR) .............. 4-25

4.6.3 Decompressor Class Configuration Registers .......................................................... 4-25

Chapter 5

Unified System Interface Unit (USIU) Overview

5.1 Memory Map and Registers ............................................................................................ 5-2

5.1.1 USIU Special-Purpose Registers ................................................................................ 5-6

Chapter 6

System Configuration and Protection

6.1 System Configuration and Protection Features .............................................................. 6-3

6.1.1 System Configuration ................................................................................................. 6-3

6.1.1.1 USIU Pin Multiplexing ........................................................................................... 6-4

6.1.1.2 Arbitration Support ................................................................................................. 6-4

6.1.2 External Master Modes ............................................................................................... 6-4

6.1.2.1 Operation in External Master Modes ...................................................................... 6-5

6.1.2.2 Address Decoding for External Accesses ............................................................... 6-6

6.1.3 USIU General-Purpose I/O ......................................................................................... 6-6

6.1.4 Enhanced Interrupt Controller .................................................................................... 6-8

6.1.4.1 Key Features ........................................................................................................... 6-8

6.1.4.2 Interrupt Configuration ........................................................................................... 6-8

6.1.4.3 Regular Interrupt Controller Operation (MPC555/MPC556-Compatible Mode) 6-10

6.1.4.4 Enhanced Interrupt Controller Operation ............................................................. 6-11

6.1.4.4.1 Lower Priority Request Masking ...................................................................... 6-14

6.1.4.4.2 Backward Compatibility with MPC555/MPC556 ............................................ 6-14

MPC561/MPC563 Reference Manual, Rev. 1.2

Freescale Semiconductor ix

Contents

Paragraph

Number Title Page

Number

6.1.4.5 Interrupt Overhead Estimation for Enhanced Interrupt Controller Mode ............ 6-16

6.1.5 Hardware Bus Monitor ............................................................................................. 6-17

6.1.6 Decrementer (DEC) .................................................................................................. 6-18

6.1.7 Time Base (TB) ........................................................................................................ 6-19

6.1.8 Real-Time Clock (RTC) ........................................................................................... 6-19

6.1.9 Periodic Interrupt Timer (PIT) .................................................................................. 6-20

6.1.10 Software Watchdog Timer (SWT) ............................................................................ 6-21

6.1.11 Freeze Operation ....................................................................................................... 6-23

6.1.12 Low Power Stop Operation ....................................................................................... 6-23

6.2 Memory Map and Register Definitions ........................................................................ 6-23

6.2.1 Memory Map ............................................................................................................ 6-23

6.2.2 System Configuration and Protection Registers ....................................................... 6-24

6.2.2.1 System Configuration Registers ........................................................................... 6-24

6.2.2.1.1 SIU Module Configuration Register (SIUMCR) .............................................. 6-25

6.2.2.1.2 Internal Memory Map Register (IMMR) .......................................................... 6-28

6.2.2.1.3 External Master Control Register (EMCR) ...................................................... 6-29

6.2.2.2 SIU Interrupt Controller Registers ........................................................................ 6-31

6.2.2.2.1 SIU Interrupt Pending Register (SIPEND) ....................................................... 6-32

6.2.2.2.2 SIU Interrupt Pending Register 2 (SIPEND2) .................................................. 6-32

6.2.2.2.3 SIU Interrupt Pending Register 3 (SIPEND3) .................................................. 6-33

6.2.2.2.4 SIU Interrupt Mask Register (SIMASK) .......................................................... 6-33

6.2.2.2.5 SIU Interrupt Mask Register 2 (SIMASK2) .................................................... 6-34

6.2.2.2.6 SIU Interrupt Mask Register 3 (SIMASK3) ..................................................... 6-35

6.2.2.2.7 SIU Interrupt Edge Level Register (SIEL) ....................................................... 6-35

6.2.2.2.8 SIU Interrupt Vector Register (SIVEC) ........................................................... 6-35

6.2.2.2.9 Interrupt In-Service Registers (SISR2 and SISR3) .......................................... 6-37

6.2.2.3 System Protection Registers ................................................................................. 6-37

6.2.2.3.1 System Protection Control Register (SYPCR) ................................................. 6-37

6.2.2.3.2 Software Service Register (SWSR) .................................................................. 6-38

6.2.2.3.3 Transfer Error Status Register (TESR) ............................................................. 6-39

6.2.2.4 System Timer Registers ........................................................................................ 6-40

6.2.2.4.1 Decrementer Register (DEC) ............................................................................ 6-40

6.2.2.4.2 Time Base SPRs (TB) ....................................................................................... 6-40

6.2.2.4.3 Time Base Reference Registers (TBREF0 and TBREF1) ................................ 6-41

6.2.2.4.4 Time Base Control and Status Register (TBSCR) ............................................ 6-42

6.2.2.4.5 Real-Time Clock Status and Control Register (RTCSC) ................................. 6-42

6.2.2.4.6 Real-Time Clock Register (RTC) ..................................................................... 6-43

6.2.2.4.7 Real-Time Clock Alarm Register (RTCAL) .................................................... 6-44

6.2.2.4.8 Periodic Interrupt Status and Control Register (PISCR) .................................. 6-44

6.2.2.4.9 Periodic Interrupt Timer Count Register (PITC) .............................................. 6-45

6.2.2.4.10 Periodic Interrupt Timer Register (PITR) ........................................................ 6-45

MPC561/MPC563 Reference Manual, Rev. 1.2

Freescale Semiconductor x

Contents

Paragraph

Number Title Page

Number

6.2.2.5 General-Purpose I/O Registers ............................................................................. 6-46

6.2.2.5.1 SGPIO Data Register 1 (SGPIODT1) ............................................................. 6-46

6.2.2.5.2 SGPIO Data Register 2 (SGPIODT2) ............................................................. 6-47

6.2.2.5.3 SGPIO Control Register (SGPIOCR) .............................................................. 6-48

Chapter 7

Reset

7.1 Reset Operation ............................................................................................................... 7-1

7.1.1 Power-On Reset .......................................................................................................... 7-1

7.1.2 Hard Reset ................................................................................................................... 7-2

7.1.3 Soft Reset .................................................................................................................... 7-2

7.1.4 Loss of PLL Lock ....................................................................................................... 7-2

7.1.5 On-Chip Clock Switch ................................................................................................ 7-3

7.1.6 Software Watchdog Reset ........................................................................................... 7-3

7.1.7 Checkstop Reset .......................................................................................................... 7-3

7.1.8 Debug Port Hard Reset ............................................................................................... 7-3

7.1.9 Debug Port Soft Reset ................................................................................................. 7-3

7.1.10 JTAG Reset ................................................................................................................. 7-3

7.1.11 ILBC Illegal Bit Change ............................................................................................. 7-3

7.2 Reset Actions Summary .................................................................................................. 7-3

7.3 Data Coherency During Reset ........................................................................................ 7-4

7.4 Reset Status Register (RSR) ........................................................................................... 7-5

7.5 Reset Configuration ........................................................................................................ 7-7

7.5.1 Hard Reset Configuration ........................................................................................... 7-7

7.5.2 Hard Reset Configuration Word (RCW) .................................................................. 7-11

7.5.3 Soft Reset Configuration .......................................................................................... 7-13

Chapter 8

Clocks and Power Control

8.1 System Clock Sources .................................................................................................... 8-3

8.2 System PLL ..................................................................................................................... 8-3

8.2.1 Frequency Multiplication ............................................................................................ 8-4

8.2.2 Skew Elimination ........................................................................................................ 8-4

8.2.3 Pre-Divider .................................................................................................................. 8-4

8.2.4 PLL Block Diagram .................................................................................................... 8-4

8.2.5 PLL Pins ..................................................................................................................... 8-5

8.3 System Clock During PLL Loss of Lock ........................................................................ 8-6

8.4 Low-Power Divider ........................................................................................................ 8-6

Ce manuel convient aux modèles suivants

Table des matières

Autres manuels Freescale Semiconductor Microcontrôleur

Freescale Semiconductor

Freescale Semiconductor i.MX53 SABRE Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor Kinetis TWR-K21D50M Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MCF52230 ColdFire Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MC9S12ZVHL64 Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor 68HC11 Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MCUSLK Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor KL02 Series Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor Kinetis K40 MCUs Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MC9S08JS16 Series Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MC9S12XE Series Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MPC5634M Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MC68332 Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor SABRE MCIMX6Q-SDP Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MMA7455L Manuel d'instructions

Freescale Semiconductor

Freescale Semiconductor HCS12 Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MCF5282 Instructions d'installation et d'utilisation

Freescale Semiconductor

Freescale Semiconductor FRDM-KL05Z Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor 56F8000E Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MC9S08PA32 Manuel d'instructions

Freescale Semiconductor

Freescale Semiconductor KV31F Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MC9S12C Family Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor FRDM-MC-LVBLDC Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor MCF52100 Manuel utilisateur

Freescale Semiconductor

Freescale Semiconductor TWR-K21F120M Manuel utilisateur

Manuels Microcontrôleur populaires d'autres marques

AMS

AMS AS7261 Demo Kit Manuel utilisateur

Novatek

Novatek NT6861 Manuel utilisateur

Espressif Systems

Espressif Systems ESP8266 SDK Guide de configuration

Nuvoton

Nuvoton ISD61S00 ChipCorder Mode d’emploi

STMicrolectronics

STMicrolectronics ST7 Assembler Linker Manuel utilisateur

Texas Instruments

Texas Instruments Chipcon CC2420DK Manuel utilisateur

Lantronix

Lantronix Intrinsyc Open-Q 865XR SOM Manuel utilisateur

NEC

NEC 78GK0S/K 1+ Series Instructions d'installation et d'utilisation

Mikroe

Mikroe SEMITECH N-PLC Click Instructions d'installation et d'utilisation

Intel

Intel Agilex Manuel utilisateur

Cypress

Cypress CY4607 HX2VL Manuel utilisateur

DIGITAL-LOGIC

DIGITAL-LOGIC MICROSPACE Manuel utilisateur

Texas Instruments

Texas Instruments TMS320F2837 D Series Manuel utilisateur

CYPRES

CYPRES CY14NVSRAMKIT-001 Manuel utilisateur

Texas Instruments

Texas Instruments INA-DUAL-2AMP-EVM Manuel utilisateur

Espressif Systems

Espressif Systems ESP8266EX Mode d'emploi

Abov

Abov AC33M8128L Manuel utilisateur

Laird

Laird BL654PA Manuel utilisateur