Espressif Systems ESP32-C3FH4 Mode d’emploi

ESP32C3 Family

Hardware Design Guidelines

Version 1.0

Espressif Systems

www.espressif.com

About This Document

The guidelines outline recommended design practices when developing standalone or add-on systems based on

the ESP32-C3 series of products, including ESP32-C3 SoCs, ESP32-C3 modules and ESP32-C3 development

boards.

Document Updates

Please always refer to the latest version on https://www.espressif.com/en/support/download/documents.

Revision History

For the revision history of this document, please refer to the last page.

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Contents

1 Overview 4

2 Schematic Checklist 5

2.1 Power Supply 6

2.1.1 Digital Power Supply 6

2.1.2 Analog Power Supply 6

2.2 Power-on Sequence and System Reset 7

2.2.1 Power-on Sequence 7

2.2.2 Reset 8

2.3 Flash 8

2.4 Clock Source 9

2.4.1 External Clock Source (compulsory) 9

2.4.2 RTC Clock (optional) 10

2.5 RF 11

2.6 UART 11

2.7 ADC 11

2.8 Strapping Pins 11

2.9 GPIO 13

3 PCB Layout Design 16

3.1 General Principles of PCB Layout 16

3.2 Placement of Module on the Base Board 16

3.3 Power Supply 19

3.4 Crystal 20

3.5 RF 21

3.6 Flash 23

3.7 UART 23

3.8 Typical Layout Problems and Solutions 24

3.8.1 Ripple in the power supply is not large, but the RF transmit (TX) performance is rather poor. 24

3.8.2 Ripple in power supply is small during packet transmission, but RF TX performance is still poor. 24

3.8.3 When ESP32-C3 family transmits data packets, the measured power is much higher or lower

than the target power, and the EVM is relatively poor. 24

3.8.4 TX performance is not bad, but the RX sensitivity is low. 24

4 Hardware Development 26

4.1 Modules Built around ESP32-C3 Family of Chips 26

4.2 Development Boards Built around ESP32-C3 Family of Chips 26

Revision History 27

Solutions, Documentation and Legal Information 28

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List of Figures

1 ESP32-C3 Family Schematic 5

2 ESP32-C3 Family Digital Power Supply Pins 6

3 ESP32-C3 Family Analog Power Supply Pins 7

4 ESP32-C3 Family Power-up and Reset Timing 8

5 ESP32-C3 Family Flash Circuit 9

6 Schematic for ESP32-C3 Family’s Crystal 9

7 Schematic for ESP32-C3 Family’s Oscillator 10

8 Schematic for ESP32-C3 Family’s External Crystal (RTC) 10

9 ESP32-C3 Family RF Matching Schematic 11

10 Setup and Hold Times for the Strapping Pin 13

11 ESP32-C3 Family PCB Layout 16

12 Placement of ESP32-C3 Modules on Base Board. Antenna Feed Point on the Right 17

13 Placement of ESP32-C3 Modules on Base Board. Antenna Feed Point on the Left 17

14 Keepout Zone for ESP32-C3 Module’s Antenna on the Base Board 18

15 ESP32-C3 Family Power Traces in a Four-layer PCB Design 19

16 ESP32-C3 Family Stub in a Four-layer PCB Design 20

17 ESP32-C3 Family Crystal Layout 21

18 ESP32-C3 Family RF Layout in a Four-layer PCB Design 21

19 ESP32-C3 RF Stub in a Four-layer PCB Design 22

20 ESP32-C3 Family PCB Stack-up Design 23

21 ESP32-C3 Family Flash Layout 23

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1 Overview

1. Overview

ESP32-C3 family is an ultra-low-power MCU-based SoC solution that supports 2.4 GHz Wi-Fi and Bluetooth®

Low Energy (Bluetooth LE). With its state-of-the-art power and RF performance, this SoC is an ideal choice for a

wide variety of application scenarios relating to Internet of Things (IoT), smart home, industrial automation, health

care, and consumer electronics.

At the core of this chip is a 32-bit RISC-V single-core processor that operates at up to 160 MHz. The chip

supports application development, without the need for a host MCU.

ESP32-C3 family provides a highly-integrated way to implement Wi-Fi and Bluetooth LE technologies using a

complete RF subsystem, including a antenna switch, RF balun, power amplifier, low noise amplifier (LNA), filter,

power management unit, calibration circuits, etc. As a result, PCB size has been greatly reduced.

With its advanced calibration circuitry, ESP32-C3 can dynamically adjust itself to remove external circuit

imperfections or adapt to changes in external conditions. As such, the mass production of ESP32-C3 family

does not require expensive and specialized Wi-Fi test equipment.

For more information about ESP32-C3 family, please refer to ESP32-C3 Family Datasheet.

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2 Schematic Checklist

2. Schematic Checklist

Thanks to high integration, ESP32-C3 family has simpler peripheral circuit design.The core circuit requires about

20 resistors, capacitors and inductors in total, as well as 1 crystal and 1 SPI flash. This document explains in

detail the schematics and PCB layout of ESP32-C3 family.

Figure 1shows the core circuit of ESP32-C3 family.

5 4 3 2 1

D D

C C

The values of C1 and C2 vary with

the selection of the crystal.

The value of R1 varies with the actual

PCB board.

GPIO19

U0RXD

GPIO18

LNA_IN

GPIO0

GPIO1

SPICS0

SPID

SPIQ

SPICLK

SPIWP

SPIHDGPIO2

RF_ANT

U0TXD

SPICS0 SPID

GND

VDD33

GNDGND GND

GND GND

VDD33

VDD_SPI

GND

GND GND

TBD

/CS

VCC

R4 0

R7 0

R6 0

R1 0

ANT1

PCB_ANT

R5 0

1uF

R2 499

R3 0

L1 2.0nH

TBD

0.1uF

L2 TBD

10uF

10nF

0.1uF

LNA_IN

VDD3P3

XTAL_32K_P

XTAL_32K_N

6 19

SPIWP

SPICS0 21

SPICLK 22

SPID 23

SPIQ 24

U0RXD 27

U0TXD 28

XTAL_N 29

XTAL_P 30

GND 33

VDDA 32

VDDA 31

GPIO19 26

GPIO18 25

40MHz(±10ppm)

XIN

GND

2XOUT 3

GND 4

5 4 3 2 1

B B

A A

The values of C8, L2 and C9

vary with the actual PCB board.

If using ESP32-C3FN4 or ESP32-C3FH4,

external flash could be removed.

CHIP_EN

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

SPIHDGPIO2

GPIO3

SPICLK

SPIHD SPIWP

SPIQ

XTAL_P

GND

GNDGND

GND GNDGND

VDD33

VDD_SPI

VDD33

GND

VDD33

GND

VDD33

L3 TBD

U3 FLASH-3V3

/CS

DO 2

/WP 3

GND

CLK

/HOLD

VCC

R7 0

C12

0.1uF

C10

0.1uF

R1 0

10nF

40MHz(±10ppm)

VCC

1GND 2

OUT 3

10K

C11

1uF

U2 ESP32-C3

XTAL_32K_N

GPIO2

CHIP_EN

MTMS

MTDI

VDD3P3_RTC

MTCK

MTDO

GPIO8

GPIO9

GPIO10

VDD3P3_CPU 17

VDD_SPI 18

SPIHD

SPIWP

GPIO3

Figure 1: ESP32C3 Family Schematic

Highlights in ESP32-C3 family circuit design may be broken down into nine major sections:

• Power supply

• Power-on sequence and system reset

• Flash

• Clock source

• RF

• UART

• ADC

• Strapping pins

• GPIO

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2 Schematic Checklist

2.1 Power Supply

For details of using power supply pins, please refer to Section Power Scheme in

ESP32-C3 Family Datasheet.

2.1.1 Digital Power Supply

Pin 11 and pin 17 are the power supply pins for RTC IO and CPU IO respectively, in a voltage range of 3.0 V ~

3.6 V. We recommend adding 0.1 µF capacitors close to each digital power supply pin.

When working as an output power supply pin, VDD_SPI can be powered by VDD3P3_CPU via RSP I (nominal 3.3

V). Therefore, there will be a voltage drop on VDD_SPI to VDD3P3_CPU. We recommend adding a 1 µF filter

capacitor between VDD_SPI and ground.

When not working as a power supply pin, VDD_SPI can be used as GPIO11.

NC: No component.

The values of C8, L2 and C9

vary with the a tual PCB board.

The values of C1 and C2 vary with

the sele tion of the rystal.

The value of R1 varies with the a tual

PCB board.

GPIO19

CHIP_EN

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

U0RXD

GPIO18

LNA_IN

GPIO9

GPIO10

GPIO0

GPIO1

SPICS0

SPID

SPIQ

SPICLK

SPIWP

SPIHDGPIO2

GPIO3

RF_ANT

U0TXD

SPICLK

SPICS0

SPIHD SPIWP

SPID

SPIQ

GND

VDD33

GND

GNDGND GND

GND GND

GND

VDD33

GND GNDGND

VDD33

VDD_SPI

VDD33

GND

VDD_SPI

GND

GND GND

TBD

U3 FLASH-3V3

/CS

DO 2

/WP 3

GND

DI 5

CLK

/HOLD

VCC 8

R4 0

R7 0

R6 0

C12

0.1uF

R1 0

ANT1

PCB_ANT

R5 0

C10

0.1uF

1uF

R2 499

R3 0

L1 2.0nH

TBD

0.1uF

L2 TBD

10uF

100pF

0.1uF

C11

1uF

U2 ESP32-C3

LNA_IN

VDD3P3

XTAL_32K_P

XTAL_32K_N

GPIO2

CHIP_EN

MTMS

MTDI

VDD3P3_RTC

MTCK

MTDO

GPIO8

GPIO9

GPIO10

VDD3P3_CPU 17

VDD_SPI 18

SPIHD 19

SPIWP 20

SPICS0 21

SPICLK 22

SPID 23

SPIQ 24

U0RXD 27

U0TXD 28

XTAL_N 29

XTAL_P 30

GND 33

GPIO3

VDDA 32

VDDA 31

GPIO19 26

GPIO18 25

40MHz(±10ppm)

XIN

GND

2XOUT 3

GND 4

10K

Figure 2: ESP32C3 Family Digital Power Supply Pins

Notice:

When VDD_SPI works as the power supply pin for embedded and external 3.3 V flash, VDD3P3_CPU should

be 3.0 V or above, so as to fall into flash’s operating voltage range.

2.1.2 Analog Power Supply

Pin 2, pin 3, pin 31, and pin 32 are the analog power supply pins, working at 3.0 V ~3.6 V. Please note that when

ESP32-C3 family works in transmission (TX) mode, the instantaneous current is higher and may cause a power

rail collapse. Therefore, it is highly recommended to add a 10 µF capacitor to the power trace, which can work in

conjunction with the 0.1 µF capacitor. In addition, a LC filter circuit needs to be added near pin 2 and pin 3 to

suppress high-frequency harmonics. The inductor’s rated current is preferably 500 mA or above. Refer to Figure

3and place the appropriate decoupling capacitor near each analog power pin.

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2 Schematic Checklist

5 4 3 2 1

D D

C C

The values of C1 and C2 vary with

the selection of the crystal.

The value of R1 varies with the actual

PCB board.

GPIO19

U0RXD

GPIO18

LNA_IN

GPIO0

GPIO1

SPICS0

SPID

SPIQ

SPICLK

SPIWP

SPIHDGPIO2

RF_ANT

U0TXD

SPICS0 SPID

GND

VDD33

GNDGND GND

GND GND

VDD33

VDD_SPI

GND

GND GND

TBD

/CS

VCC

R4 0

R7 0

R6 0

R1 0

ANT1

PCB_ANT

R5 0

1uF

R2 499

R3 0

L1 2.0nH

TBD

0.1uF

L2 TBD

10uF

10nF

0.1uF

LNA_IN

VDD3P3

XTAL_32K_P

XTAL_32K_N

6 19

SPIWP

SPICS0 21

SPICLK 22

SPID 23

SPIQ 24

U0RXD 27

U0TXD 28

XTAL_N 29

XTAL_P 30

GND 33

VDDA 32

VDDA 31

GPIO19 26

GPIO18 25

40MHz(±10ppm)

XIN

GND

2XOUT 3

GND 4

5 4 3 2 1

B B

A A

The values of C8, L2 and C9

vary with the actual PCB board.

If using ESP32-C3FN4 or ESP32-C3FH4,

external flash could be removed.

CHIP_EN

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

SPIHDGPIO2

GPIO3

SPICLK

SPIHD SPIWP

SPIQ

XTAL_P

GND

GNDGND

GND GNDGND

VDD33

VDD_SPI

VDD33

GND

VDD33

GND

VDD33

L3 TBD

U3 FLASH-3V3

/CS

DO 2

/WP 3

GND

CLK

/HOLD

VCC

R7 0

C12

0.1uF

C10

0.1uF

R1 0

10nF

40MHz(±10ppm)

VCC

1GND 2

OUT 3

10K

C11

1uF

U2 ESP32-C3

XTAL_32K_N

GPIO2

CHIP_EN

MTMS

MTDI

VDD3P3_RTC

MTCK

MTDO

GPIO8

GPIO9

GPIO10

VDD3P3_CPU 17

VDD_SPI 18

SPIHD

SPIWP

GPIO3

Figure 3: ESP32C3 Family Analog Power Supply Pins

Notice:

• If you use a single power supply, the recommended voltage of the power supply for ESP32-C3 family

is 3.3 V, and its recommended output current is 500 mA or more.

• You are suggested to add an ESD protection diode at the power entrance.

2.2 Poweron Sequence and System Reset

2.2.1 Poweron Sequence

ESP32-C3 family uses a 3.3 V system power supply. The chip should be activated after the power rails have

stabilized. This is achieved by delaying the activation of pin 7 CHIP_EN after the 3.3 V rails have been brought

up.

Figure 4shows the power-up and reset timing of ESP32-C3 family. Details about the parameters are listed in

Table 1.

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2 Schematic Checklist

VDDA,

VDD3P3,

VDD3P3_RTC,

VDD3P3_CPU

CHIP_EN

t0t1

VIL_nRST

2.8 V

Figure 4: ESP32C3 Family Powerup and Reset Timing

Table 1: Description of ESP32C3 Family Powerup and Reset Timing Parameters

Min

Parameter Description (µs)

Time between bringing up the VDDA, VDD3P3, VDD3P3_RTC, and

VDD3P3_CPU rails, and activating CHIP_EN 50

t1Duration of CHIP_EN signal level < VIL_nRST to reset the chip 50

Notice:

To ensure the power supply to the ESP32-C3 family chip is stable during power-up, it is advised to add an

RC delay circuit at the CHIP_EN pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ

and C = 1 µF. However, specific parameters should be adjusted based on the power-up timing of the power

supply and the power-up and reset sequence timing of the chip.

2.2.2 Reset

CHIP_EN can be used as the reset pin of ESP32-C3 family. When CHIP_EN is at low level, the reset voltage

(VIL_nRST ) should be (–0.3 ~0.25 × VDD) V (where VDD is the I/O voltage for a particular power domain of pins).

To avoid reboots caused by external interference, route the CHIP_EN trace as short as possible, and add a

pull-up resistor as well as a capacitor to ground whenever possible.

Notice:

CHIP_EN pin must not be left floating.

2.3 Flash

ESP32-C3 family can support up to 16 MB external flash. The ESP32-C3-WROOM-02 module uses a 4 MB SPI

flash, powered by VDD_SPI. We recommend reserving a serial resistor (initially of 0 Ω) on the SPI line, to lower the

driving current, adjust timing, reduce crosstalk and external interference, etc.

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2 Schematic Checklist

5 4 3 2 1

D D

C C

The values of C1 and C2 vary with

the selection of the crystal.

The value of R1 varies with the actual

PCB board.

GPIO19

U0RXD

GPIO18

LNA_IN

GPIO0

GPIO1

SPICS0

SPID

SPIQ

SPICLK

SPIWP

SPIHDGPIO2

RF_ANT

U0TXD

SPICS0 SPID

GND

VDD33

GNDGND GND

GND GND

VDD33

VDD_SPI

GND

GND GND

TBD

/CS

VCC

R4 0

R7 0

R6 0

R1 0

ANT1

PCB_ANT

R5 0

1uF

R2 499

R3 0

L1 2.0nH

TBD

0.1uF

L2 TBD

10uF

10nF

0.1uF

LNA_IN

VDD3P3

XTAL_32K_P

XTAL_32K_N

6 19

SPIWP

SPICS0 21

SPICLK 22

SPID 23

SPIQ 24

U0RXD 27

U0TXD 28

XTAL_N 29

XTAL_P 30

GND 33

VDDA 32

VDDA 31

GPIO19 26

GPIO18 25

40MHz(±10ppm)

XIN

GND

2XOUT 3

GND 4

5 4 3 2 1

B B

A A

The values of C8, L2 and C9

vary with the actual PCB board.

If using ESP32-C3FN4 or ESP32-C3FH4,

external flash could be removed.

CHIP_EN

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

SPIHDGPIO2

GPIO3

SPICLK

SPIHD SPIWP

SPIQ

XTAL_P

GND

GNDGND

GND GNDGND

VDD33

VDD_SPI

VDD33

GND

VDD33

GND

VDD33

L3 TBD

U3 FLASH-3V3

/CS

DO 2

/WP 3

GND

CLK

/HOLD

VCC

R7 0

C12

0.1uF

C10

0.1uF

R1 0

10nF

40MHz(±10ppm)

VCC

1GND 2

OUT 3

10K

C11

1uF

U2 ESP32-C3

XTAL_32K_N

GPIO2

CHIP_EN

MTMS

MTDI

VDD3P3_RTC

MTCK

MTDO

GPIO8

GPIO9

GPIO10

VDD3P3_CPU 17

VDD_SPI 18

SPIHD

SPIWP

GPIO3

Figure 5: ESP32C3 Family Flash Circuit

2.4 Clock Source

There are two clock sources for ESP32-C3 family, namely an external crystal clock source and an RTC clock

source.

2.4.1 External Clock Source (compulsory)

Currently, the ESP32-C3 family firmware only supports 40 MHz crystal. The specific capacitance of C1 and C2

depends on further testing of, and adjustment to, the overall performance of the whole circuit. Please add a

component in series on the XTAL_P clock trace to reduce the drive capability of the crystal and to minimize the

impact of crystal harmonics on RF performance. The value of this component (initially of 24 nH) depends on

further testing. Note that the accuracy of the selected crystal needs to be ±10 ppm.

NC: No component.

The values of C8, L2 and C9

vary with the a tual PCB board.

The values of C1 and C2 vary with

the sele tion of the rystal.

The value of R1 varies with the a tual

PCB board.

GPIO19

CHIP_EN

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

U0RXD

GPIO18

LNA_IN

GPIO9

GPIO10

GPIO0

GPIO1

SPICS0

SPID

SPIQ

SPICLK

SPIWP

SPIHDGPIO2

GPIO3

RF_ANT

U0TXD

SPICLK

SPICS0

SPIHD SPIWP

SPID

SPIQ

GND

VDD33

GND

GNDGND GND

GND GND

GND

VDD33

GND GNDGND

VDD33

VDD_SPI

VDD33

GND

VDD_SPI

GND

GND GND

TBD

U3 FLASH-3V3

/CS

DO 2

/WP 3

GND

DI 5

CLK

/HOLD

VCC 8

R4 0

R7 0

R6 0

C12

0.1uF

R1 0

ANT1

PCB_ANT

R5 0

C10

0.1uF

1uF

R2 499

R3 0

L1 2.0nH

TBD

0.1uF

L2 TBD

10uF

100pF

0.1uF

C11

1uF

U2 ESP32-C3

LNA_IN

VDD3P3

XTAL_32K_P

XTAL_32K_N

GPIO2

CHIP_EN

MTMS

MTDI

VDD3P3_RTC

MTCK

MTDO

GPIO8

GPIO9

GPIO10

VDD3P3_CPU 17

VDD_SPI 18

SPIHD 19

SPIWP 20

SPICS0 21

SPICLK 22

SPID 23

SPIQ 24

U0RXD 27

U0TXD 28

XTAL_N 29

XTAL_P 30

GND 33

GPIO3

VDDA 32

VDDA 31

GPIO19 26

GPIO18 25

40MHz(±10ppm)

XIN

GND

2XOUT 3

GND 4

10K

Figure 6: Schematic for ESP32C3 Family’s Crystal

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