EMTRION EmCON-MX8MM Manuel utilisateur

emCON-MX8MM

Hardware Manual

Rev1 / 09.09.2019

emtrion GmbH

emCON-MX8MM - Hardware Manual (Rev1) 2/33

media without written approval. The information contained in this documentation is subject to

change without prior notice. We assume no liability for erroneous information or its consequences.

Trademarks used from other companies refer exclusively to the products of those companies.

Revision: 1 / 09.09.2019

Rev

Date/Signature

Changes

09.09.2019/Sch

First revision

 
 
emCON-MX8MM - Hardware Manual (Rev1) 3/33 
Contents 
1Introduction........................................................................................................................................................4
2Block Diagram ....................................................................................................................................................5
3Handling Precautions.......................................................................................................................................5
4Functional Description.....................................................................................................................................6
1 Processor.....................................................................................................................................................6
1.1 Processor Clocks...............................................................................................................................7
1.2 Boot Mode/Boot Medium..............................................................................................................7
2 NAND Flash.................................................................................................................................................8
3 LPDDR4 SDRAM.........................................................................................................................................8
4 Ethernet.......................................................................................................................................................8
5 USB Host......................................................................................................................................................9
6 USB OTG.......................................................................................................................................................9
7 Graphic Display....................................................................................................................................... 10 
7.1 LVDS.................................................................................................................................................. 10 
8 MIPI CSI-2.................................................................................................................................................. 11 
9 Audio - Synchronous Audio Interface (SAI)..................................................................................... 11 
10 Audio - SPDIF........................................................................................................................................... 12 
11 SD-Card Interface................................................................................................................................... 12 
12 Serial Ports................................................................................................................................................ 12 
12.1 IrDA................................................................................................................................................... 12 
13 I²C- Bus ...................................................................................................................................................... 12 
14 SPI Interface............................................................................................................................................. 13 
15 PCI Express............................................................................................................................................... 13 
16 General Purpose I/Os............................................................................................................................. 13 
17 PWM........................................................................................................................................................... 14 
18 Status LED ................................................................................................................................................ 14 
19 Interrupts.................................................................................................................................................. 14 
20 Reset .......................................................................................................................................................... 15 
21 Power Supply .......................................................................................................................................... 15 
21.1 Signal Description......................................................................................................................... 15 
21.2 Power Consumption .................................................................................................................... 16 
5emCON Interface............................................................................................................................................ 17 
6Pin Assignments ............................................................................................................................................. 18 
1 J1, emCON Connector........................................................................................................................... 18 
7Signal Characteristics..................................................................................................................................... 24 
1 J1, emCON Connector........................................................................................................................... 25 
8Technical Characteristics.............................................................................................................................. 31 
1 Electrical Specifications ........................................................................................................................ 31 
2 Environmental Specifications............................................................................................................. 31 
3 Mechanical Specifications.................................................................................................................... 31 
9Dimensional Drawing.................................................................................................................................... 32 
References........................................................................................................................................................ 33 

emCON-MX8MM - Hardware Manual (Rev1) 4/33

1Introduction

The emCON-MX8MM processor module is based on the i.MX8MM processor from Freescale. It is

one of emtrion's emCON-family CPU boards. The i.MX8MM includes up to 4 ARM Cortex A53 cores

as well as an additional ARM Cortex M4 core for low-power processing.

The emCON-MX8MM processor modules are available with i.MX8MM quad core, dual core or solo

core (every configuration is also available in “lite”-version). Please contact emtrion GmbH for

further information.

The processor cores run up to 1.8 GHz in the customer version and 1.6 GHz in the industrial version.

They comprise a variety of functions which are required for multimedia or industrial applications.

These include video compression standards like VP9, VP8, H.265 and H.264, a 2D/3D graphics

accelerator, two LVDS interfaces, a MIPI-CSI2 camera interface and a SAI and S/PDIF audio interface.

The module is available in various sizes of NAND-Flash and RAM, as well as different amounts of

ARM Cortex A53 cores. The CPU has an internal Ethernet MAC and two USB controllers, which are

used as USB Host and USB Device.

All interfaces are accessible through a 315 pin MXM type III edge connector. The pin assignment is

defined in emtrion's emCON standard, which ensures a pin-to-pin compatibility with all emCON

CPU modules.

Features and interfaces of the emCON-MX8MM processor module are described in the following

table:

emCON-MX8MM

2GB/4GB LPDDR4 SDRAM

up to 32GB eMMC NAND Flash

16MB QSPI NOR Flash

1x 10/100/1000-Mbit Ethernet

1x USB 2.0 Host

1x USB 2.0 Device

1x PCIe (1 lane)

2x LVDS 24-bit max. WUXGA (1920x1200) @ 60Hz

1x MIPI CSI-2 (4 lanes)

1x SAI Audio

1x S/PDIF

4x UART (LVTTL)

1x SD Card

1x SPI

1 x Quad SPI

2x I2C

8x GPIO

1x PWM

RTC, battery buffered

JTAG

Please contact emtrion GmbH for the available processor, NAND Flash and SDRAM configurations.

The module is available in standard temperature range (0°C to 70°C) as well as extended

temperature range (-40°C to 85°C).

emCON-MX8MM - Hardware Manual (Rev1) 5/33

2Block Diagram

The following figure shows the emCON-MX8MM block diagram.

3Handling Precautions

Please read the following notes prior to installing the processor module. They apply to all ESD

(electrostatic discharge) sensitive components:

•The module does not need any configurations before installation.

•The module does not provide any on-board ESD protection circuitry –this must be

provided by the product it is used in.

•Before installing the module, it is recommended that you discharge yourself by touching a

grounded object.

•Be sure all tools required for installation are electrostatically discharged as well.

•Before installing (or removing) the module, unplug the power cable from the mains supply.

•Handle the board with care and try to avoid touching its components or tracks.

emCON-MX8MM - Hardware Manual (Rev1) 6/33

4Functional Description

4.1 Processor

The emCON-MX8MM processor module uses the i.MX processor i.MX8MM from Freescale [1]. It

includes up to 4 ARM Cortex A53 cores and runs up to 1.8 GHz.

In addition to the CPU core with MMU, FPU and Caches, this processor provides a variety of

features, such as:

•16/32-bit DRAM Controller (LP-DDR4, DDR4, DDR3-L)

•8-bit NAND Flash Controller

•eMMC 5.0 Flash and SPI NOR Flash interfaces

•Ethernet MAC 10/100/1000-Mbit with IEEE1588 support

•2 x USB 2.0 OTG controller with high-speed mode

•3 x Ultra Secure Digital Host Controller (uSDHC) interfaces

•1 x PCI Express (Single Lane)

•Two Image Processing Units, which include:

oVideo input module with camera capturing module

oLCDIF Display Controller (Support up to 1080p60 display through MIPI DSI)

o2D and 3D graphic hardware accelerator

oNEON SIMD media accelerator

•4 UARTs with 2x 32-byte FIFO

•I2C bus interfaces

•SPI interfaces

•IrDA interfaces

•Watchdog timer

•Real time clock

•5 x SAI Sound modules (Supporting I2S, AC97, TDM, codec/DSP and DSD interfaces)

•S/PDIF Sound interface (Input and Output)

•Interrupt controller

•32-bit General Purpose Timer

•JTAG debug interface

Further details of the processor can be found in the i.MX8MM Reference Manual [1].

emCON-MX8MM - Hardware Manual (Rev1) 7/33

4.1.1 Processor Clocks

The 24 MHz main clock is generated by a quartz crystal. The internal PLLs multiply the 24 MHz main

clock to the internal clocks. All clocks within the processor are derived from theses frequencies, via

various software configurable dividers.

The core clock can run up to 1,8 GHz. For power management, the core clock can be varied.

It must be considered that the core voltage should be adapted if the core frequency is varied.

More information about the i.MX8MM clock system is described in the CCM chapter of the

i.MX8MM Reference Manual [1].

The RTC_XTALI clock input of the CPU is supplied by a 32,768 kHz clock, generated by the PMIC and

used for the internal low speed clocks. The PMIC generates the clock signal by an external 32,768

kHz quartz crystal.

An additional I²C RTC Chip is used to generate a battery-backed-up Real-Time Clock.

4.1.2 Boot Mode/Boot Medium

The emCON-MX8MM Uboot can be booted either from the onboard eMMC, the NOR Flash, the SD-

Card interface or external via the USB Device interface. To switch between the options, the right

boot mode and boot device has to be configured via some Dip Switches.

The boot mode is configured via two processor pins which are available at the emCON connector.

A dip switch on the carrier board is used to configure the boot mode.

emCON Avari Baseboard (SW1):

SW1

SW2

SW3

SW[4:8]

Boot Mode

Configuration

Boot from Fuses

OFF

Serial Downloader

USB

OFF

Internal Boot

eMMC/SDC/NAND/NOR

OFF

Reserved

emCON Bvari Baseboard (SW4):

SW1

SW2

SW3

SW4

Boot Mode

Configuration

Boot from Fuses

OFF

Serial Downloader

USB

OFF

Internal Boot

eMMC/SDC/NAND/NOR

OFF

Reserved

emCON-MX8MM - Hardware Manual (Rev1) 8/33

The Boot medium is configured via a dip switch on the emCON MX8MM module.

emCON MX8MM CPU Module (SW1):

SW1

SW2

SW3

SW4

Configuration

OFF

eMMC

Na.

SDC

Na.

QSPI

Configurations for other boot devices will be coming soon.

4.2 NAND Flash

To store the operating system and application data, an eMMC-NAND Flash is provided on the

emCON-MX8MM module. It is connected to the uSDHC1 controller of the i.MX8MM.

You can choose a NAND Flash size between 4GB and 32GB, depending on your requirements.

Please contact emtrion GmbH for your required NAND Flash size.

The onboard NAND Flash controller can be reset by a logical “0” on the GPIO1_IO03 Pin.

4.3 LPDDR4 SDRAM

LPDDR4 SDRAM is available as main memory. The RAM memory has a 32-bit width interface, a

density of 4GB and can be clocked up to 1865 MHz (3733 Mb/s).

Please contact emtrion GmbH for your required RAM size.

4.4 Ethernet

The Ethernet interface is realized with the processor internal Media Access Controller (MAC) and an

external Physical Layer Interface (PHY) KSZ9031RNX from Micrel. The RGMII interface is used for

communication between the MAC and the PHY.

The Ethernet interface supports the operating modes 10, 100 and 1000BASE-TX, all half- and full

duplex. HP Auto-MDIX is also supported.

The registers of the Ethernet PHY can be configured via the Media Independent Interface (MII).

The Ethernet signal lines (GBE1_MDIO[0:3]_P, GBE1_MDIO[0:3]_N) as well as two status signals,

indicating the link status and the transfer speed, are connected to the emCON connector. An

appropriate 1:1 transformer with a 100nF capacitor to GND at each center tap pin must be added

externally. The center tap pin shall not be supplied with 3.3V!

The emCON pins GBE1_LED_10_100# and GBE1_LED_1000# are both connected to the LED2 pin of

the Ethernet PHY and indicate if a link is established. (“0” = link). Therefore, the link speed has to be

determined by the software.

emCON-MX8MM - Hardware Manual (Rev1) 9/33

The emCON pin GBE1_LED_TRAFFIC# is connected to the LED1 pin of the Ethernet PHY, it indicates

that data is being transferred (“blinking”= traffic).

The RGMII 125MHz Ethernet clock is generated by the PLL of the Ethernet PHY and routed to the

processor’s internal MAC.

The Ethernet Phy can be reset by a logical “0” on the GPIO1_IO09 Pin.

4.5 USB Host

A USB Host interface is used to connect USB devices such as a keyboard, mouse, printer or memory

stick.

The USB host interface is realized by the internal host controller of the i.MX8MM. It complies with

the USB specification Rev. 2.0, supporting data transfers at low-speed (1,5Mbps), full-speed (12

Mbps) and high-speed (480Mbps).

To switch the bus power, the control line USBH_PEN# is connected to the emCON connector. A

logical “0” at the processor’s pin GPIO1_IO14 switches the power on; a logical “1” turns the power

off. The signal USBH_OC# reports an overcurrent at the GPIO1_IO15 (“0” = overcurrent).

The data lines and the two control lines are available at the emCON connector. A USB power switch

must be added externally. The data lines are internally terminated by 15-Kpulldown resistors.

The USBH_VBUS signal on the emCON connector is only an input to detect the VBUS voltage on

the baseboard.

4.6 USB OTG

The USB OTG port can operate in Host or Device mode. The signal USBOTG_ID is used to determine

the mode of the connected device.

The interface is realized by the internal device controller of the i.MX8MM. The interface is USB 2.0

compliant, supporting data transfers at low-speed (1,5Mbps), full-speed (12 Mbps) and high-speed

(480Mbps).

To switch the bus power in USB Host mode the control line USBOTG_PEN# is connected to the

emCON connector. A logical “0” at the processor GPIO1_IO12 switches the power on; a logical “1”

turns the power off. The signal USBH_OC# reports an overcurrent at the GPIO1_IO13 (“0” =

overcurrent).

The USBOTG_VBUS signal on the emCON connector is only an input to detect the VBUS voltage on

the baseboard.

emCON-MX8MM - Hardware Manual (Rev1) 10/33

4.7 Graphic Display

The i.MX8MM includes two Graphic Processing Units (GPU) for 2D and 3D acceleration and a Video

Processing Unit (VPU) for Video decoding (H.265, VP9, H.264, VP8). More information about the

Multimedia system is described in the Multimedia, GPU and VPU chapter of the i.MX8MM

Reference Manual [1].

The enhanced Liquid Crystal Display Interface (eLCDIF) on the processor is a general-purpose

display controller which supports a wide range of display devices.

4.7.1 LVDS

The LCD controller of the i.MX8MM supports a 4-lane MIPI DSI port which drives a MIPI DSI to LVDS

Bridge (SN65DSI84 from Texas Instruments) on the CPU module, in order to generate two Single-

Link or one Dual-Link LVDS Interface with four data lanes per link.

The pixel clock is limited to 154 MHz in Single and Dual-Link mode. This results in a maximum

resolution of WUXGA (1920 x 1200 @ 60 Hz).

The SN65DSI84 from Texas Instruments can communicate via the internal I2C3 Interface. The

interrupt output of the device is connected to the GPIO3_IO22 Pin of the processor.

To enable the MIPI DSI to LVDS Bridge, set a logical “1” on the GPIO3_IO24 (pay attention to the

timing specifications of the device in the SN65DSI84 Datasheet [2] Chapter 7.4.1). A logical “0”

disables the device.

The following table describes the signals of the LVDS port 1:

Signal

Description

LVDS1_CLK_P/N

Differential LVDS clock

LVDS1_D[3:0]_P/N

Four differential LVDS data signal pairs

LVDS1_PANEL_EN

Display power enable signal, GPIO3_IO25

LVDS1_BL_EN

Backlight power enable signal, GPIO3_IO23

LVDS1_BL_CTRL

PWM signal to control the backlight, GPIO1_IO01

The following table describes the signals of the LVDS port 2:

Signal

Description

LVDS2_CLK_P/N

Differential LVDS clock

LVDS2_D[3:0]_P/N

Four differential LVDS data signal pairs

The colour mapping can be different, depending of the used display. The LVDS Output formats can

be adjusted in the MIPI DSI to LVDS Bridge registers. Use the SN65DSI84 Datasheet [2] to setup a

specific LVDS format.

Table des matières

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