
Contents
iv •Product Specification (V1.3) 05.22.2014
7.6 RAM Map for Special and Control Registers.................................................... 22
7.6.1 Special and Control Registers...........................................................................22
7.6.2 Other Unbanked General RAM .........................................................................23
7.6.3 Banked General RAM .......................................................................................24
7.7 LCD RAM Map ................................................................................................. 24
7.8 Special Function Registers............................................................................... 24
7.8.1 ACC (R0Ah): Accumulator ...............................................................................24
7.8.2 POST_ID (R33h): Post Increase / Decrease Control Register .........................25
7.8.3 BSR, FSR0, INDF0 (R02h, R01h, R00h):
Indirect Address Pointer 0 Registers.................................................................25
7.8.4 BSR1, FSR1, INDF1 (R05h, R04h, R03h):
Indirect Address Pointer 1 Registers.................................................................25
7.8.5 STKPTR (R06h): Stack Pointer Register ..........................................................27
7.8.6 PCL, PCM (R07h, R08h): Program Counter Registers.....................................27
7.8.7 TABPTRL, TABPTRM (R0Bh, R0Ch): Table Pointer Registers ........................28
7.8.8 Port A, Port B (R10h, R11h): General I/O Pin Registers...................................29
7.8.9 STBCON (R20): Strobe Output Control Register..............................................29
7.8.10 PACON (R29h): Port A Control Register ...........................................................29
7.8.11 PAWAKE (R2Ah): Port A Wake-up Control Register.........................................30
7.8.12 PAINTEN (R2Bh): Port A Interrupt Enable Control Register .............................30
7.8.13 PAINTSTA (R2Ch): Port A Interrupt Status Register .........................................30
7.8.14 DCRA (R2Dh): Port A Direction Control Register..............................................30
7.8.15 PBCON (R2Eh): Port B Pull up Resistor Control Register................................31
7.8.16 DCRB (R2Fh): Port B Direction Control Register .............................................31
8
Peripheral
......................................................................................................32
8.1
Timer 0 (16 Bits Timer with Event Counter Function)....................................... 32
8.1.1
Timer 0 Registers ..............................................................................................33
8.2
Timer 1 (8 Bits)................................................................................................. 36
8.2.1
Timer 1 Registers ..............................................................................................36
8.3
Timer 2 (8 Bits)................................................................................................. 38
8.3.1
Timer 2 Registers ..............................................................................................39
8.4
Watchdog Timer (WDT).................................................................................... 41
8.4.1
Watchdog Timer (WDT) Registers ....................................................................41
8.5
Input/Output Key .............................................................................................. 42
8.5.1 Key Functions....................................................................................................43
8.5.2 Key Strobe.........................................................................................................44
8.5.2.1 Automatic Key Scan ...........................................................................44
8.5.2.2 Software Key Scan.............................................................................45
8.5.2.3 Key Strobe Pin Function.....................................................................46
8.5.3
Input/Output Key Registers ...............................................................................46