Elan Digital Systems Ltd. 2AD125 USER’S GUIDE
CONTENTS
1. OVERVIEW..................................................................................................4
1.1 MODEL NAMING CONVENTIONS.........................................................................................5
2. ABOUT THE AD125 ....................................................................................6
2.1 QUICK THEORY OF SUCCESSIVE APPROXIMATION CONVERTERS........................6
2.2 NOISE............................................................................................................................................6
2.3 POSSIBLE SOURCES OF MEASUREMENT ERROR...........................................................8
2.4 D to A Converters.........................................................................................................................9
3. CONTROLLING THE AD125.....................................................................10
3.1 ACQUISITION MODES............................................................................................................10
3.1.1 BURST MODE......................................................................................................................10
3.1.2 FIFO MODE..........................................................................................................................11
3.1.3 SINGLE-SHOT MODE.........................................................................................................11
3.2 A to D OUTPUT FORMAT / GAIN SETTING.......................................................................12
3.3 AD125 BUFFER ADDRESSING...............................................................................................14
3.3.1 BUFFER DATA ORDER......................................................................................................14
3.3.2 CONTROLLING THE SRAM POINTERS..........................................................................14
3.3.3 PRE-TRIGGER DEPTH .......................................................................................................15
3.3.4 READING THE SRAM DATA ............................................................................................16
3.4 TRIGGERING............................................................................................................................17
3.4.1 THRESHOLD........................................................................................................................17
3.4.2 TRIGGER MODES...............................................................................................................18
3.4.3 ENABLING TRIGGER.........................................................................................................19
3.5 OTHER FEATURES..................................................................................................................20
3.5.1 SAMPLE RATE....................................................................................................................20
3.5.2 INPUT MUX CONTROL .....................................................................................................21
3.5.3 SLEEP MODE.......................................................................................................................23
3.5.4 INTERRUPTS.......................................................................................................................23
3.5.5 CONFIG OPTION REGISTER.............................................................................................25
3.5.6 DIGITAL IO..........................................................................................................................26
3.6 DAC PROGRAMMING............................................................................................................27
4. AD125 REGISTER INTERFACE ...............................................................29
4.0 SETUP REG 1 (IR 0)..................................................................................................................31
4.1 SETUP REG 2 (IR 1)..................................................................................................................32
4.2 IODATA (IR 2)...........................................................................................................................33
4.3 IODIR (IR 3)...............................................................................................................................34
4.4 DIVLO / ADDRCTLO (IR 4) ....................................................................................................35
