ECS Electronics SI54P AIO Manuel utilisateur

S

l

5

4

P

AI

O

U

se

r

'

s

M

a

nu

a

l

(

fo

r

Phoe

ni

x

B

I

OS

)

ii

All brand and product names used

in

this manual may be trademarks or

regis



tered trademarks of their respective

companies

.

Trademarks

iii

B

u

il

t

-

i

n

B

I

O

S

SETU

P

rog

ra

m

·

SETUP Program 9

System

S

etup 10

Fixed Disk

Se

tu

p



11

Advanced System Setup

13

I

nt

e

grated

P

e

rip

h

erals

1

4

Memory Cac

h

e

1

5

Me

mory

Shad

o

w 18

Advanced

C

hipset Control 19

PC

I Devices 23

Boot Options

2

6

S

ec

u

rity Setup

2

7

Green PC Feature

:

2

8

Load ROM

Defau

l

t

V

alues

3

1

Load

Valu

es from

C

MOS

'3

2

S

ave

V

al

u

es to CM

O

S

33

Quitting Setup 34

Jump

e

r

Se

tt

i

ng

s

a

nd

C

onn

e

ctor

s

Setting the Jumpers

5

Connect

o

rs 7

Board Layouts

:

8

S

y

s

te

m

M

e

mory

Cac

h

e Memory

S

ubsystems

5

I

n

trod

u

cti

o

n

General

Specificati

o

ns

1

S

y

stem Chipset 2

II

Co

nt

e

nt

s

1

Po

w

er

K

e

y

l

oc

k

&

Po

w

er

LED

Hard

w

ar

e

R

e

se

t

S

peaker

Turbo

LED

Turbo

S

witch

S

u

s

pend

HDD

LED

Bab

y

-

A

T

4

layers

Intel Pentiumn.t

75/90/l

00

S

i

s

8

5C501

(PCl/I

S

A

Cache

M

e

mory

Controll

e

r)

S

i

S

8

5C50

2

(

PCI

Local Data

Buff

e

r)

S

i

S

8

5

C

50

3

(PCI

Sy

s

tem

1/0)

CMD

PCI06

4

0B

(PCI

Bu

s

IDE

Controller)

S

M

C

3

7C665 (Super 1/0 Controller)

UM

C

8

2C865 (1/0

TIL

Integration)

2

56/51

2

KB

or

1

MB

cache

supporting

vvrit

e

ba

ck or

vvrit

e-through policies

2

banks

of

DRAM with

memory

size

capacity of

up

t

o

1

28

MB

,

a

l

s

upporting

doubl

e

-sided SIMMs

\

Phoenix

Four

1

6-bit

ISA

s

lots

Four

PCI

s

l

o

t

s

PCB

:

F

o

rm

F

a

ctor

:

Con

necto

r

s:

S

l

ots

:

BIO

S:

M

e

m

o

ry

S

ize

:

Ext

e

rna

l

C

a

c

he

:

Ch

l

ps

e

t

:

1.1

Genera

l

Spec

i

fica

ti

ons

Process

o

r:

The

SI5

4

P

AIO is a Pentium TM PCI Bus

mainbo

a

rd,

It

uses the

SiS

85C501

,

8

5C

50

2

, 85C503

s

y

s

tem

chipset

,

CMD

PCI06

4

0B PCI Bus IDETuntroller,

and

SMC

3

7

C66

5

Sup

er

1/0

Cont

r

oller

.

Other

on



board

specifications

in

-

clud

e 4

A

T

Bu

s

l

o

t

s

a

nd

4 PCI

s

l

o

ts, 2

m

e

mory banks with memory

si

zes of

up

to

1

2

8MB

,

an

d

ca

c

h

e

s

i

z

es from

2

56KB to lMB.

1

Introduction

2

•

S

I

S8

5C502

•

Thre

e

int

e

grated

p

os

t

ed write

b

uffer

s

and

two

read

buffers increase

s

ystem

p

e

rforman

ce

•

1

level

Cl'Ut

o

M

e

m

pos

te

d

wr

ite buffer with 4 Qwords deep

• 4 levels

CPU

t

o

PCI

p

o

s

t

ed

writ

e buffer with 4 Dwords deep

•

1

level

PCI



to



Mern

p

o

s

ted

w

rit

e buffer with

1

Qword deep

•

1

level

M

e

m



to



Cl'U

r

ead

buff

e

r

with

1

Qword

d

e

ep

•

1

lev

e

l

Me

mtoPCl

r

ea

d

buffe

r

with

1

Qwo

r

d

e

ep

• Provides a

64



bit

P

e

nti

u

m

TM

,

DRAM

d

at

a bus

and

3

2

bit PCI data

bus

•

Operate

s

sy

n

c

hron

o

u

s

l

y

t

o

th

e

G

G.

7

MH

z CPU

and

33

.

3MHz PCI

clocks

•

P

r

ovides

p

a

rit

y

g

ener

ati

on for

memor

y writes

S

y

ste

m

C

hip

se

t

•

S

I

S8

5C501

•

Support

s

Pen

t

ium

'

?"

p

ro

c

e

s

or

a

t

5

9

/

GO!GG

MHz bus speed

•

Inte

gr

at

e

d

s

ec

ond

lev

e

l

(L

Z

)

ca

c

he

mod

es

•

write



through

and

writeb

a

ck

ca

ch

e modes

•

dire

c

t

mapp

e

d

o

rgani

zation

•

support

s

standard

a

nd

bur

s

t

SRAM

s

•

s

upport

s

1

Z8

KB

t

o

Z

MB

cach

e

s

i

z

es

•

c

a

che

r

ea

d

/

w

r

it

e

cy

cl

e of

3Z

Z



Z

or

4



3



3



3

u

s

ing standard

SRAM at 6GMHz

• Integrated DRAM

c

ontroll

e

r

• supports

Z

MB to

1

Z

8MB of

c

ac

heable main memory

•

1

level

po

s

ted

w

rit

e

bu

ffe

r

o

f 4

Q

wo

rds deep

•

concu

r

rent

write

bac

k

•

CAS

#



before



RAS#

t

ra

nsp

ar

ent DRAM refresh

•

Z

5GK/

lM/ 4M/

1

GM

*

N

70n

s

fa

s

t

p

a

ge mode DRAM support

• programmable DRAM

s

pe

e

d

Sl54P AIO

User

's

Manual

3

•

SM

C3JC665

• Super

I/O

controller

•

Two

I6C550

c

omp

a

tible

UART

s

• One

multi



mod

e

p

a

rallel

p

o

rt

which include

EPP

and

ECP

support

•

CMD

PC

I0

640B

• Fully

compatibl

e with the

lat

es

t PCI IDE

and

ATAPI specifications

• The

mo

s

t

compl

e

te

3

2

bit driver support

in

the industry (DOS,

Windows 3.1

Pa

s

t Disk, Windows NT,

OSIZ

,

Novell

&

SCO Unix

32bit

driver support)

·

•

Progr

a

mm

a

ble

d

a

t

a transfer timing supports customized setting for

4 IDE devices

•

Read



ahead and writeback buffers enhance transfer rates

and

al



low concurrent

operation

s

•

Suitable for PCI motherboard or PCI expansion card applications

• Fully supports and

s

urpa

ss

es

enhance IDE ModeS

•

Support

s

progr

a

m

I/O

fun

c

tion

•

S

I

S85C503

•

Integrated

brid

ge between PCI Bus and

ISA

Bus

•

translates PCI

Bu

s

cycles into

ISA

Bus cycles

•

tran

s

lat

es

ISA

m

as

te

r

or DMA cycles into PCI Bus cycles

•

provid

es

PCIto



lSA

memor

y one Dword posted write buffer

• Integr

a

ted

ISA

Bu

s

c

ompatible logic

•

Supports

rerout

a

bility of four PCI interrupts to any unused IRQ

in

terrupt

• Supports Flash ROM

SJ54P AJO

User

'

s

Manual

4

Ta

ble

2



1

.

Memory

Confi

g

uration

s and

Requirement

s

Ba

n

k

O

Ba

nk1

T

o

ta

l

S

IM

3

S

IM

4

!

SIM1

S

IM

2 M

em

o

ry

S

i

ze

25

6K

x 36

256

K

~

_

36

.

J

.

N

o

ne

None

2

MB

25

6K

x

3

6

256

K

x

36

I

25

6

K

x

36

25

6Kx

36 4MB

·

-

·

r

~

·

5

1

2

K

x 36

512K

x

3

6

;

N

o

ne

None

4

MB

i

5

12K

x 36

5

1

2

K

x 36

I

5

1

2

K

x 36

5

1

2

K

x 36

8M

B

i

!

5

1

2

K

x 36

I

5

1

2

K

~

4

M

x

36

4

M

x36

36

M

B

1M x 36 1M

x

36

I

Non

e

None

8

MB

I

-

_ _

_

L

-

--

1M

x 36

1

M

x 36

i

1

M

x

36

1M

x

36 16MB

1M

x

3

6

1M

x36

·

-

1

4M

x36

4

M

x

36

MB

2

M

x36

2

M

x

36

None None

16MB

2M

x

36

2

M

x

3

6 2

M

x36

2M

x

36 32MB

2

M

x36

2

M

x 36

4

M

x

36

4

M

x

36

48

MB

·

-·

-

·

-

· f·

-

·

-·

·

4M

x

36

4M

x 36

I

4

M

x36

4

M

x

36

64M

B

8M

x

36

8

M

x

3

~

N

on

e

Non

e

64

MB

8

M

x

36

8M

x36

I

8

M

x36

8M

x

36

1

28

MB

I

S

I5

4P

AI

O

acce

pt

s

a minimum

o

f

2

MB a

nd a

maxim

um

o

f

1

28

MB

on



bo

ard.

Th

e

r

e

a

re

t

wo

m

e

m

ory banks

w

hi

c

h

s

upp

ort

2

56/

5

1

2

KB

o

r

1/

2/4

/8/

16 MB

72

ty

p

e,

s

in

g

le



and

/

or

double



d

e

n

s

ity modules.

Important

:

DRAM

in

se

rtion on

e

very bank should com

e

in

p

a

ir

a

nd

of

the same type. For instance,

if

you only

ha

v

e

two

DRAM module

s,

you cannot

in

s

tall one

DR

AM

modul

e

in

s

ocket SIM1

a

nd another

DR

AM

modul

e

of

t

h

e

sa

m

e

type on S

IM3

.

Likewise

,

memory type mixing

i

s

N

OT

a

l



low

e

d within

a

ba

nk

.

Th

e following

tabl

e

lis

t

s

all

th

e

po

ss

ib

l

e

DRAM

mo

dule

combin

a

tions

a

n

d

th

e

t

otal

m

e

mor

y

am

o

un

t

for

eac

h

op

tion.

2

S

y

s

tem Memory

SJ

54P

AJ

O

User

'

s

Ma

n

ua

l

5

Ta

b

l

e

4

1

.

Jumper

S

ett

i

ngs (Continued

..

.)

F

unction

Jum

pe

r

S

ett

i

ng

s

50MHz (for

7

5MH

z CPU)

J

P7

s

hort 2-3, 5-6, 7-8

CP

U

C

lo

c

k

S

el

e

ct

6

0MHz (for

90

MH

z CPU)

J

P7 short

2

-3, 4-5

,

8-9

66MH

z (for

100MH

z CPU)

J

P7

s

hort

1-

2,

5

-

6

,

7-8

Internal

Cach

e

Write-back

J

P

1

2

s

hort

1

-2

Interna

l

C

a

che

Write

-

J

P

1

2

short

2

-3

CP

U

S

i

g

n

al

Se

l

ec

t

hrough

Always invalidated

J

P

1

4 short

1-

2

Writ

e

to

i

nvalid

a

ted

J

P

1

4 short

2

-

3

2

56KB (with

3

2

Kx8

J

P

11

open

SRAMs)

J

P

10 open

E

xt

e

rn

a

l

Ca

ch

e 51

2

KB

(with

64

Kx8 JP11 short

M

e

mo

r

y

Sett

ing

s

SRAM

s

)

J

P

10 open

1

MB

(w

i

th

128

Kx8 SRAMs)

J

P11

short

JP10short

Th

e

tabl

e

b

e

low

summ

a

r

izes

th

e

function

s

a

nd

jump

e

r

sett

ings on

th

e

SIS4

P

AIO.

.

3.1

Sett

i

ng

t

h

e

Jumpers

3

Jumper

Settings and Connectors

T

a

b

l

e

2



2.

S

econd Level Cache Memory

C

onfigurat

i

ons

C

a

c

he

S

i

ze

Di

rt

y

RA

M

TAG

RA

M

D

a

t

a

(

U

23

-

26

)

(U28

)

(U

27

)

(U

34-

U

3

7)

2

56KB

3

2

Kx8 (5V) 32Kx8

(

5V) 32Kx8

(

3.3V)

51

2

KB

3

2

Kx8 (5V) 32Kx8 (5V) 64Kx8

(3

.

3V)

1MB

3

2Kx8

(

5

V) 32Kx8 (5V) 128Kx8

(3

.

3V)

Cac

h

e

M

e

m

o

ry

S

u

bsys

t

e

m

s

SJ

54

P AIO User's Manual

ECS Electronics SI54P AIO Manuel utilisateur

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