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IP Lock (standard pack) Users Manual - 1 - P 0602-6-01-05E
1. Introduction
Thank you very much for purchasing IP Lock. Please check that all the following items are in the
box. If anything is missing or damaged, contact your distributor or esign Gateway Co.,Ltd.
1. IP Lock device 10 or 50 pcs.
2. Users manual
3. C ROM contains :
-IP Lock users manual (IPL_UserManual1_1_E.pdf)
-IP Lock core for Xilinx (TopIPLock.vhd, iplock.ngc and iplockex.ngo)
-IP Lock core for Altera (TopIPLock.vhd, iplock.vhd)
-Example VH L design source codes (Counter.vhd, Counter32Bits.vhd)
1.1. Summary Feature
1. 128-bit AES encryption
2. IP Lock core and IP Lock device sent and receive data for checking every 200 msec
3. Xilinx FPGA support only Spartan2, Spartan2E, Spartan3, Spartan3E, Spartan6, Virtex, Virtex2,
Virtex2Pro, Virtex4, Virtex5 and Virtex6
4. Altera FPGA support only Stratix, Stratix2, Stratix3, Stratix4, ArriaGX, Arria2GX, Cyclone
Cyclone2 and Cyclone3
1.2. Minimum System Requirement
1. Pentium III or compatible processor
2. RAM 256 MB
3. Windows XP
4. Xilinx ISE 7.1 or over for Xilinx FPGA designer
5. Quartus II 4.1 or over for Altera FPGA designer
