Cypress MB90910 Series Manuel utilisateur

MB90911AS/F912BS/V950AMAS

F2MC-16LX MB90910 Series

16-bit Microcontroller

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 002-04578 Rev. *A Revised April 12, 2016

The MB90910 series, loaded 1 channel FULL-CAN controller and Flash ROM, is general-purpose Cypress 16-bit microcontroller

designing for automotive and industrial applications. Its main feature is the on-board CAN controllers, which conform to Ver 2.0 Part

A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN

approach. With the new 0.18m CMOS technology, Cypress now offers on-chip Flash ROM program memory up to 128 Kbytes.

The power supply (1.8 V) is supplied to the MCU core from an internal regulator circuit. This creates a major advantage in terms of

EMI and power consumption.

The internal PLL clock frequency multiplier provides an internal 31.25 ns instruction execution time from an external 4 MHz clock.

The unit features a 4-channel input capture unit 1 channel 16-bit free-run timer, 2-channel LIN-UART,

1-channel UART, and 16-channel 8/10-bit A/D converter as the peripheral resource.

Features

Clock

■Built-in PLL clock frequency multiplication circuit

■Selection of machine clocks (PLL clocks) is allowed among

frequency division by 2 on oscillation clock and multiplication

of 1 to 8 times of oscillation clock (for 4 MHz oscillation clock,

4 MHz to 32 MHz)

■Minimum execution time of instruction : 31.25 ns (when

operating with 4-MHz oscillation clock and 8-time multiplied

PLL clock)

Instruction system best suited to controller

■16 Mbytes CPU memory space

■24-bit internal addressing

■Wide choice of data types (bit, byte, word, and long word)

■Wide choice of addressing modes (23 types)

■Enhanced multiply-divide instructions with sign and RETI

instructions

■Enhanced high-precision computing with 32-bit accumulator

Instruction system compatible with high-level

language (C language) and multitask

■Employing system stack pointer

■Enhanced various pointer indirect instructions

■Barrel shift instructions

Increased processing speed

4-byte instruction queue

Powerful interrupt function

■Powerful 8-level, 34-condition interrupt feature

■Up to 8 channels external interrupts are supported

CPU-independent automatic data transfer func-

tion

Expanded intelligent I/O service function (EI2OS) : up to 16

channels

Low power consumption (standby) mode

■Sleep mode (a mode that halts CPU operating clock)

■Main timer mode (timebase timer mode that is transferred

from main clock mode)

■PLL timer mode (timebase timer mode that is transferred from

PLL clock mode)

■Stop mode (a mode that stops oscillation clock)

■CPU blocking operation mode

Process

CMOS technology

I/O port

General purpose input/output port (CMOS output) :

- 36 ports

Timer

■Timebase timer, watchdog timer : 1 channel

■8/16-bit PPG timer : 8-bit 6 channels or 16-bit 3 channels

■16-bit reload timer : 2 channels

■16- bit input/output timer

❐-16-bit free-run timer : 1 channel (FRT0 : ICU 0/1/2/3)

❐-16- bit input capture : (ICU) : 4 channels

FULL-CAN controller : 1 channel

■Compliant with CAN specifications Version 2.0 Part A and B

■16 message buffers are built in

■CAN wake-up function

UART (LIN/SCI) : LIN-UART2 channels, UART

1 channel

■Equipped with full-duplex double buffer

■Clock-asynchronous or clock-synchronous serial trans-

mission is available

Document Number: 002-04578 Rev. *A Page 2 of 64

MB90910 Series

DTP/External interrupt : up to 8 channels, CAN

wakeup : up to 1 channel

Module for activation of expanded intelligent I/O service (EI2OS)

and generation of external interrupt by external input

Delay interrupt generator module

Generates interrupt request for task switching

8/10-bit A/D converter : 16 channels

■Resolution is selectable between 8-bit and 10-bit

■Activation by external trigger input is allowed

■Conversion time : 3 s (at 24 MHz machine clock, including

sampling time)

Program patch function

Address matching detection for 6 address pointers

Capable of changing input voltage for port

Automotive/CMOS-Schmitt input level (initial level is Automotive

in single-chip mode)

ROM security function

The content of ROM can be protected (Only MASK ROM

product).

Flash memory security function

Protects the content of Flash memory

Document Number: 002-04578 Rev. *A Page 3 of 64

MB90910 Series

Contents

Product Lineup ................................................................ 4

Pin Assignment ................................................................ 6

Pin Description ................................................................. 7

I/O Circuit Type .............................................................. 10

Handling Devices ............................................................ 15

Block Diagrams .............................................................. 18

Memory Map .................................................................... 20

I/O Map ............................................................................. 21

CAN Controllers .............................................................. 29

Interrupt Factors, Interrupt Vectors,

Interrupt Control Register .............................................. 36

Electrical Characteristics ............................................... 38

Absolute Maximum Ratings ....................................... 38

Recommended Conditions ........................................ 40

DC Characteristics .................................................... 41

AC Characteristics ..................................................... 43

Clock Timing .............................................................. 43

Reset Standby Input .................................................. 45

Power-on Reset ......................................................... 46

UART ......................................................................... 46

Trigger Input Timing .................................................. 51

Timer Related Resource Input Timing ....................... 52

Timer Related Resource Output Timing .................... 52

CAN PLL cycle jitter .................................................. 53

A/D Converter ............................................................ 54

Definition of A/D Converter Terms ........................... 56

Flash Memory Program/Erase Characteristics ......... 59

Ordering Information ..................................................... 60

Package Dimension ........................................................ 61

Major Changes .................................................................62

Document Number: 002-04578 Rev. *A Page 4 of 64

MB90910 Series

1. Product Lineup

(Continued)

Part number

Parameter

MB90V950AMAS MB90F912BS MB90911AS

Type Evaluation product Flash memory product MASK ROM product

CPU F2MC-16LX CPU

System clock On-chip PLL clock multiplier (1, 2, 3, 4, 6, 8, 1/2 when PLL stops)

Minimum instruction execution time : 31.25 ns (4 MHz osc. PLL 8)

ROM External 128 Kbytes 64 Kbytes

RAM 30 Kbytes 8 Kbytes 4 Kbytes

Emulator-specific

power supply*1Yes 

FPGA data*2Rev 050617 

Adaptor board*2MB2147-20 Rev.04C or later 

Technology 0.35 m CMOS with built-in power

supply regulator 0.18 m CMOS with built-in power supply regulator

Operation voltage range 5 V 10 3.0 V to 5.5 V : When normal operating

Operating ambient tem-

perature 40 °C to 105 °C

Package PGA-299 LQFP-48

UART

LIN-UART 7 channels LIN-UART 2 channels, UART 1 channel

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device (Supported by LIN-UART only)

I2C (400 kbps) 2 channels 

A/D converter

24 input channels 16 input channels

10-bit or 8-bit resolution

Conversion time : Min 3 s include sample time (per one channel)

16-bit

Reload timer

4 channels 2 channels

Operation clock frequency : fsys/21, fsys/23, fsys/25(fsys Machine clock frequency)

Supports External Event Count function

16-bit

I/O timer

2 channels 1 channel

Generates an interrupt signal on overflow

Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27

(fsys Machine clock freq.)

I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1/2/3, OCU 0/1/2/3

I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU 4/5/6/7

16-bit

Output compare

8 channels 

Generates an interrupt signal when one of the 16-bit I/O timer matches the output compare register

A pair of compare registers can be used to generate an output signal.

Document Number: 002-04578 Rev. *A Page 5 of 64

MB90910 Series

(Continued)

*1: It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator hardware manual

for the details.

*2: Contact the sales or support representative if using other than those above of FPGA data and adaptor boards.

Part number

Parameter

MB90V950AMAS MB90F912BS MB90911AS

16-bit

Input capture

8 channels 4 channels

Rising edge, falling edge or rising & falling edge sensitive

Signals an interrupt upon external event

8/16-bit

PPG

8 channels (16-bit) /16 channels

(8-bit)

Sixteen 8-bit reload counters

Sixteen 8-bit reload registers for L

pulse width

Sixteen 8-bit reload registers for H

pulse width

3 channels (16-bit) /6 channels (8-bit)

Six 8-bit reload counters

Six 8-bit reload registers for L pulse width

Six 8-bit reload registers for H pulse width

Supports 8-bit and 16-bit operation modes

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler plus 8-bit reload counter

Operating clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24or 128 s@fosc 4 MHz

(fsys Machine clock frequency, fosc Oscillation clock frequency)

CAN

controller

3 channels 1 channel

Conforms to CAN Specification Version 2.0 Part A and B

Automatic re-transmission in case of error

Automatic transmission in response to Remote Frames

Prioritized 16 message buffers for data and ID’s

Supports multiple messages

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps

DTP/External

interrupt

(8 channels)

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

expanded intelligent I/O services (EI2OS)

D/A Converter 8-bit 2 channels 

I/O Ports

Virtually all external pins can be used as general purpose I/O port

All ports are push-pull outputs

Bit-wise settable as input/output or peripheral signal

Can be configured 8 as CMOS schmitt trigger/ automotive inputs (in blocks of 8 pins)

TTL input level settable for external bus (32-pin only for external bus)

Flash memory

(Flash memory product

only)

Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Boot block configuration

Erase can be performed on each block

Flash Security

Document Number: 002-04578 Rev. *A Page 6 of 64

MB90910 Series

2. Pin Assignment

■MB90F912BS, MB90911AS

(TOP VIEW)

(FPT-48P-M26)

P66/AN6/PPGC(D)

AVss

RST

Vcc

Vss

P40

P41

P82/SIN0/INT14R/TIN2

P50/AN8/SIN2

AVcc

P44/FRCK0

P80/ADTG/INT12R

P51/AN9/SOT2

P67/AN7/PPGE(F)

AVR

P60/AN0

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5/PPGA(B) P27/IN3

P26/IN2

P25/IN1

P24/IN0

P23/PPGF(E)*

P22/PPGD(C)*

P21/PPGB(A)*

P20*

MD2

MD1

MD0

P52/AN10/SCK2

P53/AN11/TIN3

P54/AN12/TOT3/INT8

P55/AN13/INT10

P56/AN14/INT11

P57/AN15/INT13

P84/SCK0/INT15R

P83/SOT0/TOT2

P42/RX1/INT9R

P43/TX1

P86/SOT1

P87/SCK1

P85/SIN1

LQFP-48

* : High current output port

Document Number: 002-04578 Rev. *A Page 7 of 64

MB90910 Series

3. Pin Description

(Continued)

Pin No. Pin name I/O circuit type* Function

1AV

CC IV

CC power input pin for analog circuit.

2 AVR Power (Vref) input pin for A/D converter.

It should be below VCC.

3 to 7

P60 to P64

General-purpose I/O port.

AN0 to AN4 Analog input pins for A/D converter.

8 to 10

P65 to P67

General-purpose I/O port.

AN5 to AN7 Analog input pins for A/D converter.

PPGA (B) ,

PPGC (D) ,

PPGE (F)

Output pins for PPG.

P80

General-purpose I/O port.

ADTG Trigger input pin for A/D converter.

INT12R External interrupt request input pin for INT12R.

P50

General-purpose I/O port.

AN8 Analog input pin for A/D converter.

SIN2 Serial data input pin for UART2.

P51

General-purpose I/O port.

AN9 Analog input pin for A/D converter.

SOT2 Serial data output pin for UART2.

P52

General-purpose I/O port.

AN10 Analog input pin for A/D converter.

SCK2 Clock I/O pin for UART2.

P53

General-purpose I/O port.

AN11 Analog input pin for A/D converter.

TIN3 Event input pin for reload timer 3.

P54

General-purpose I/O port.

AN12 Analog input pin for A/D converter.

TOT3 Output pin for reload timer 3

INT8 External interrupt request input pin for INT8.

P55

General-purpose I/O port.

AN13 Analog input pin for A/D converter.

INT10 External interrupt request input pin for INT10.

Document Number: 002-04578 Rev. *A Page 8 of 64

MB90910 Series

(Continued)

Pin No. Pin name I/O circuit

type* Function

P56

General-purpose I/O port

(Different I/O circuit type from MB90V950AMAS).

AN14 Analog input pin for A/D converter.

INT11 External interrupt request input pin for INT11.

P57

General-purpose I/O port

(Different I/O circuit type from MB90V950AMAS).

AN15 Analog input pin for A/D converter.

INT13 External interrupt request input pin for INT13.

20 MD2 D Input pin for operation mode specification.

21, 22 MD1,

MD0 C Input pins for operation mode specification.

23 RST E Reset input pin.

24 VCC Power input pin (3.5 V to 5.5 V) .

25 VSS Power input pin (0 V) .

26 C I Power supply stabilization capacitor pin. It should be connected to a higher

than or equal to 0.1 F ceramic condenser.

27 X0

Oscillation input pin.

28 X1 Oscillation output pin.

29 to 32

P27 to P24

General-purpose I/O port.

The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

IN3 to IN0 Event input pins for input capture 0 to 3.

33 to 35

P23 to P21

General-purpose I/O port.

The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

High current output port

(Different I/O circuit type from MB90V950AMAS).

PPGF (E) , PPGD

PPGB(A)

Output pins for PPG.

36 P20 J

General-purpose I/O port.

The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

High current output port

(Different I/O circuit type from MB90V950AMAS).

P85

General-purpose I/O port.

SIN1 Serial data input pin for UART1.

P87

General-purpose I/O port.

SCK1 Clock I/O pin for UART1.

P86

General-purpose I/O port.

SOT1 Serial data output pin for UART1.

Document Number: 002-04578 Rev. *A Page 9 of 64

MB90910 Series

(Continued)

* : For the I/O circuit type, refer to “I/O Circuit Type”.

Pin No. Pin name I/O circuit

type* Function

P43

General-purpose I/O port.

TX1 TX output pin for CAN1 controller.

P42

General-purpose I/O port.

RX1 RX input pin for CAN1 controller.

INT9R External interrupt request input pin for INT9R.

P83

General-purpose I/O port.

SOT0 Serial data output pin for UART0.

TOT2 Output pin for reload timer 2.

P84

General-purpose I/O port.

SCK0 Clock I/O pin for UART0.

INT15R External interrupt request input pin for INT15R.

P82

General-purpose I/O port.

SIN0 Serial data input pin for UART0.

INT14R External interrupt request input pin for INT14R.

TIN2 Event input pin for reload timer 2.

P44

General-purpose I/O port

(Different I/O circuit type from MB90V950AMAS).

FRCK0 Free-run timer 0 clock input pin.

46, 47 P40, P41 F General-purpose I/O port

48 AVSS IV

SS power input pin for analog circuit.

Document Number: 002-04578 Rev. *A Page 10 of 64

MB90910 Series

4. I/O Circuit Type

Type Circuit Remarks

AOscillation circuit :

High-speed oscillation feedback

resistor approx. 1 M

(MASK ROM product, Flash memory product)

Oscillation circuit :

High-speed oscillation feedback

resistor approx. 1 M

(Evaluation product)

BUnused

C• MASK ROM product / Evaluation

product :

CMOS hysteresis input pin

• Flash memory product :

CMOS input pin

D• MASK ROM product / Evaluation

product :

CMOS hysteresis input pin

• Flash memory product :

- CMOS input pin

- No Pull-down

Xout

Standby control signal

Xout

Standby control signal

X1A

X0A

Xout

CMOS hysteresis

inputs

Pull-down

resistor

CMOShysteresis

inputs

Ce manuel convient aux modèles suivants

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