Atmel ATtiny13A Manuel utilisateur

Features

•High Performance, Low Power AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Througput at 20 MHz

•High Endurance Non-volatile Memory segments

– 1K Bytes of In-System Self-programmable Flash program memory

– 64 Bytes EEPROM

– 64 Bytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 Years at 85°C/100 Years at 25°C (see page 6)

– Programming Lock for Self-Programming Flash & EEPROM Data Security

•Peripheral Features

– One 8-bit Timer/Counter with Prescaler and Two PWM Channels

– 4-channel, 10-bit ADC with Internal Voltage Reference

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

•Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, and Power-down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit with Software Disable Function

– Internal Calibrated Oscillator

•I/O and Packages

– 8-pin PDIP/SOIC: Six Programmable I/O Lines

– 10-pad MLF: Six Programmable I/O Lines

– 20-pad MLF: Six Programmable I/O Lines

•Operating Voltage:

– 1.8 – 5.5V

•Speed Grade:

– 0 – 4 MHz @ 1.8 – 5.5V

– 0 – 10 MHz @ 2.7 – 5.5V

– 0 – 20 MHz @ 4.5 – 5.5V

•Industrial Temperature Range

•Low Power Consumption

– Active Mode:

• 190 µA at 1.8 V and 1 MHz

–IdleMode:

• 24 µA at 1.8 V and 1 MHz

8-bit

Microcontroller

with 1K Bytes

In-System

Programmable

Flash

ATtiny13A

Rev. 8126F–AVR–05/12

28126F–AVR–05/12

ATtiny13A

1. Pin Configurations

Figure 1-1. Pinout of ATtiny13A

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

(PCINT4/ADC2) PB4

GND

VCC

PB2 (SCK/ADC1/T0/PCINT2)

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

8-PDIP/SOIC

20-QFN/MLF

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

DNC

(PCINT4/ADC2) PB4

DNC

GND

DNC

VCC

PB2 (SCK/ADC1/T0/PCINT2)

DNC

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

DNC

NOTE: Bottom pad should be soldered to ground.

DNC: Do Not Connect

10-QFN/MLF

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

DNC

(PCINT4/ADC2) PB4

GND

VCC

PB2 (SCK/ADC1/T0/PCINT2)

DNC

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

NOTE: Bottom pad should be soldered to ground.

DNC: Do Not Connect

8126F–AVR–05/12

ATtiny13A

1.1 Pin Description

1.1.1 VCC Supply voltage.

1.1.2 GND Ground.

1.1.3 Port B (PB5:PB0)

Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny13A as listed on page

55.

1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running and provided the reset pin has not been disabled. The min-

imum pulse length is given in Table 18-4 on page 120. Shorter pulses are not guaranteed to

generate a reset.

The reset pin can also be used as a (weak) I/O pin.

48126F–AVR–05/12

ATtiny13A

2. Overview The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC

architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves

throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-

sumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

SRAM

MCU CONTROL

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTER0

INSTRUCTION

DECODER

DATA DIR.

REG.PORT B

DATA REGISTER

PORT B

PROGRAMMING

LOGIC

TIMING AND

CONTROL

MCU STATUS

STATUS

ALU

PORT B DRIVERS

PB[0:5]

VCC

GND

CONTROL

LINES

8-BIT DATABUS

ADC /

ANALOG COMPARATOR

INTERRUPT

UNIT

CALIBRATED

RESET

CLKI

WATCHDOG

OSCILLATOR

DATA

EEPROM

8126F–AVR–05/12

ATtiny13A

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATtiny13A provides the following features: 1K byte of In-System Programmable Flash, 64

bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working reg-

isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-

channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft-

ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,

Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The

Power-down mode saves the register contents, disabling all chip functions until the next Inter-

rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules

except ADC, to minimize switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code

running on the AVR core.

The ATtiny13A AVR is supported with a full suite of program and system development tools

including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.

68126F–AVR–05/12

ATtiny13A

3. About

3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development

tools are available for download at http://www.atmel.com/avr.

3.2 Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

3.3 Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

8126F–AVR–05/12

ATtiny13A

4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

4.1 Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the Program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the Program memory. This concept enables instructions to be executed

in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

88126F–AVR–05/12

ATtiny13A

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash Program memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every Program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F.

4.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

4.3 Status Register

The Status Register contains information about the result of the most recently executed arithme-

tic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Reference. This will in many cases remove the need for using the

dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

8126F–AVR–05/12

ATtiny13A

4.3.1 SREG – Status Register

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful

in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

Bit 76543210

0x3F I T H S V N Z C SREG

Read/Write R/W R/W R/WR/WR/WR/WR/WR/W

Initial Value 0 0 0 0 0 0 0 0

10 8126F–AVR–05/12

ATtiny13A

4.4 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by the

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 4-2 on page 10, each register is also assigned a Data memory address,

mapping them directly into the first 32 locations of the user Data Space. Although not being

physically implemented as SRAM locations, this memory organization provides great flexibility in

access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in

the file.

4.4.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 4-3 on page 11.

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

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