APPOTECH AX2228D Manuel utilisateur

AX2228D

Audio Player Microcontroller

User Manual

[AX2228D -UM-EN]

Versions: 1.0.0

Release Date: 2015-9-2

II Table of content

AX2228D Audio Player Microcontroller Version 1.0.0

Table of content

Table of content ........................................................................................................................................ II

Figure........................................................................................................................................................ VI

Table ......................................................................................................................................................... VI

Register.................................................................................................................................................... VII

1Product Overview.............................................................................................................................. 1

1.1 Outline........................................................................................................................................ 1

1.2 Features...................................................................................................................................... 1

1.3 System Architecture................................................................................................................... 2

2Pin Definitions ................................................................................................................................... 3

2.1 AX2228D..................................................................................................................................... 3

2.1.1 Packages ............................................................................................................................. 3

2.1.2 Pin Assignment ................................................................................................................... 3

2.1.3 Pin Descriptions .................................................................................................................. 3

3CPU Core Information ....................................................................................................................... 8

3.1 Architecture ............................................................................................................................... 8

3.2 Instruction Set ............................................................................................................................ 8

3.3 Memory Mapping .................................................................................................................... 11

3.3.1 Program Memory Mapping .............................................................................................. 11

3.3.2 External Data Memory Mapping ...................................................................................... 12

3.3.3 Internal Data Memory Mapping....................................................................................... 12

3.4 Interrupt Processing................................................................................................................. 13

3.4.1 Interrupt sources .............................................................................................................. 13

3.4.2 Interrupt Priority............................................................................................................... 15

3.5 CPU and Memory related SFR Description .............................................................................. 15

4Reset Generation............................................................................................................................. 23

4.1 Power-on Reset (POR).............................................................................................................. 23

4.2 System Reset ............................................................................................................................ 23

Table of content III

AX2228D Audio Player Microcontroller Version 1.0.0

4.2.1 LVD.................................................................................................................................... 24

4.2.2 RTCC Reset........................................................................................................................ 26

4.2.3 Watchdog Reset ............................................................................................................... 26

4.2.4 Port Wakeup Reset........................................................................................................... 26

4.3 Clock System ............................................................................................................................ 26

4.3.1 Clock Control .................................................................................................................... 26

4.3.2 Phase Lock Loop (PLL)....................................................................................................... 32

5Low Power Management ................................................................................................................ 36

5.1 Power Saving Mode ................................................................................................................. 36

5.1.1 Sleep Mode....................................................................................................................... 36

5.1.2 Hold Mode........................................................................................................................ 36

5.1.3 Idle Mode.......................................................................................................................... 36

5.1.4 Deep Sleep Mode ............................................................................................................. 37

5.1.5 Power Down Mode........................................................................................................... 37

5.2 Power Supply............................................................................................................................ 38

6General Purpose Input/Output (GPIO)............................................................................................ 40

6.1 Overview .................................................................................................................................. 40

6.2 Features.................................................................................................................................... 40

6.3 Function multiplexing............................................................................................................... 40

6.4 GPIO Special Function Registers .............................................................................................. 42

6.5 Port interrupt and wakeup....................................................................................................... 55

6.5.1 Wakeup registers.............................................................................................................. 55

6.6 Operation Guide....................................................................................................................... 57

7Timers.............................................................................................................................................. 58

7.1 Timer0 ...................................................................................................................................... 58

7.1.1 Timer0 Features................................................................................................................ 58

7.1.2 Timer0 Special Function Registers.................................................................................... 58

7.2 Timer1 ...................................................................................................................................... 59

7.2.1 Timer1 Features................................................................................................................ 60

7.2.2 Timer1 Special Function Registers.................................................................................... 60

IV Table of content

AX2228D Audio Player Microcontroller Version 1.0.0

7.3 Timer2 ...................................................................................................................................... 62

7.3.1 Timer2 Features................................................................................................................ 62

7.3.2 Timer2 Special Function Registers.................................................................................... 62

7.4 Timer3 ...................................................................................................................................... 64

7.4.1 Timer3 Features................................................................................................................ 64

7.4.2 Timer3 Special Function Registers.................................................................................... 64

7.5 Watchdog Timer (WDT) ........................................................................................................... 66

7.5.1 Watchdog Wake up .......................................................................................................... 66

7.5.2 Watchdog SFR................................................................................................................... 66

7.6 Independent Power Real Time Clock Counter (IRTCC) ............................................................ 67

7.6.1 IRTCC Controller ............................................................................................................... 67

7.6.2 IRTCC Timer ...................................................................................................................... 67

7.6.3 Communication with IRTCC Timer.................................................................................... 68

7.6.4 IRTCC components description ........................................................................................ 70

7.6.5 IRTCC Special Function Registers...................................................................................... 75

7.6.6 IRTCC Operating Guide ..................................................................................................... 77

8Universal Asynchronous Receiver/Transmitter (UART) .................................................................. 79

8.1 UART0....................................................................................................................................... 79

8.1.1 Overview........................................................................................................................... 79

8.1.2 UART0 Special Function Registers .................................................................................... 79

8.2 UART1....................................................................................................................................... 81

8.2.1 Overview........................................................................................................................... 81

8.2.2 UART1 Special Function Registers .................................................................................... 81

8.2.3 UART1 Operation Guide ................................................................................................... 84

8.3 UART2....................................................................................................................................... 84

8.3.1 Overview........................................................................................................................... 84

8.3.2 UART2 Special Function Registers .................................................................................... 84

8.4 Operation Guide....................................................................................................................... 88

9SPI .................................................................................................................................................... 90

9.1 SPI0........................................................................................................................................... 90

Table of content V

AX2228D Audio Player Microcontroller Version 1.0.0

9.1.1 SPI0 Special Function Registers ........................................................................................ 91

9.1.2 SPI0 Operation Guide ....................................................................................................... 92

9.2 SPI1........................................................................................................................................... 93

9.2.1 SPI1 Special Function Registers ........................................................................................ 94

9.2.2 SPI1 Operation Guide ....................................................................................................... 96

10 External Memory Interface (EMI).................................................................................................... 97

10.1 EMI Control Registers............................................................................................................... 97

11 Audio Terminal (DAC).................................................................................................................... 101

11.1 Features.................................................................................................................................. 101

11.2 DAC Special Function Registers.............................................................................................. 101

11.2.1 DAC Register Mapping.................................................................................................... 101

11.2.2 Function of DAC Control Registers ................................................................................. 102

11.3 Operation Guide..................................................................................................................... 106

12 SARADC.......................................................................................................................................... 107

12.1 Features.................................................................................................................................. 107

12.2 ADC Pin Mapping.................................................................................................................... 107

12.3 SARADC Special Function Registers........................................................................................ 107

13 Integrated Interchip Sound (IIS) .................................................................................................... 110

13.1 Features.................................................................................................................................. 110

13.2 IIS Special Function Register .................................................................................................. 111

13.3 Operation Guide..................................................................................................................... 114

13.3.1 Master mode .................................................................................................................. 114

13.3.2 Slave mode 1 .................................................................................................................. 114

13.3.3 Slave mode 2 .................................................................................................................. 114

13.3.4 Slave mode 3 .................................................................................................................. 114

13.3.5 IIS Operation Flow .......................................................................................................... 115

14 LCD driver ...................................................................................................................................... 116

14.1 Features.................................................................................................................................. 116

14.2 LCD Function Control Registers.............................................................................................. 118

15 Characteristics ............................................................................................................................... 123

VI Table of content

AX2228D Audio Player Microcontroller Version 1.0.0

15.1 LDO Parameters ..................................................................................................................... 123

15.2 PLL Parameters....................................................................................................................... 123

15.3 I/O Parameters....................................................................................................................... 123

15.4 OSC Parameters ..................................................................................................................... 124

15.5 Audio DAC Parameters........................................................................................................... 124

16 Package Dimensions...................................................................................................................... 125

16.1 AX2228D LQFP48.................................................................................................................... 125

Appendix I Revision History........................................................................................................................ i

Figure

Figure 1-1 AX2228D system architecture............................................................................................................2

Figure 2-1 shows the pin assignments of LQFP48 package. ..............................................................................3

Figure 2-2 Pin assignment for LQFP48...............................................................................................................3

Figure 3-1 Program Memory Organization ........................................................................................................11

Figure 3-2 External Data Memory Mapping.......................................................................................................12

Figure 3-3 Internal data memory mapping.........................................................................................................13

Figure 3-4 Lowest 32 bytes in Internal data memory Lower 128.......................................................................13

Figure 4-1 Power on reset.................................................................................................................................23

Figure 4-2 Reset Sources..................................................................................................................................24

Figure 4-3 Source of XCK12V...........................................................................................................................30

Figure 5-1 Frequency compensation through external component....................................................................38

Figure 7-1 Timer1 Block Diagram......................................................................................................................60

Figure 9-1 SPI timing.........................................................................................................................................90

Figure 10-1 EMI timing......................................................................................................................................97

Figure 22-1 Timing of IIS in different mode......................................................................................................111

Figure 16-1 AX2228D LQFP48 package dimensions......................................................................................125

Table

Table 2-1 LQFP48 pin description .......................................................................................................................3

Table 3-1 AXC51-CORE Instruction Set Summary..............................................................................................8

Table 3-2 Interrupt Summary.............................................................................................................................13

Table of content VII

AX2228D Audio Player Microcontroller Version 1.0.0

Table 4-1 LVD level setting................................................................................................................................24

Table 6-1 Pad types...........................................................................................................................................40

Table 6-2 Ports multiplexed mapping.................................................................................................................41

Table 7-1 IRTCC components communication commands................................................................................68

Table 17-1 DAC registers address mapping....................................................................................................101

Table 19-1 pin used.........................................................................................................................................107

Table 22-1 IIS pin mapping..............................................................................................................................110

Table 23-1 LCD PAD groups............................................................................................................................116

Table 23-2 Support panel in auto display mode...............................................................................................116

Table 15-1 LDO Parameters............................................................................................................................123

Table 15-2 PLL Parameters.............................................................................................................................123

Table 15-3 I/O Parameters ..............................................................................................................................123

Table 15-4 OSC Parameters............................................................................................................................124

Table 15-5 Audio DAC Parameters..................................................................................................................124

Register 3-1 DPCON –Data Pointer Configure Register ..................................................................................15

Register 3-2 DPL0 –Data Pointer Low Byte .....................................................................................................16

Register 3-3 DPL1 –Data Pointer Low Byte .....................................................................................................16

Register 3-4 DPH0 –Data Pointer High Byte....................................................................................................16

Register 3-5 DPH1 –Data Pointer High Byte....................................................................................................16

Register 3-6 SP –Stack Pointer Low Byte ........................................................................................................17

Register 3-7 SPH –Stack Pointer High Byte.....................................................................................................17

Register 3-8 PSW –Processor Status Word.....................................................................................................17

Register 3-9 SPMODE –Special mode.............................................................................................................18

Register 3-10 IE0 –Interrupt Enable 0 ..............................................................................................................18

Register 3-11 IE1 –Interrupt Enable 1 ..............................................................................................................19

Register 3-12 IPH0 –Interrupt Priority high 0....................................................................................................19

Register 3-13 IP0 –Interrupt Priority 0 ..............................................................................................................20

Register 3-14 IPH1 –Interrupt Priority high 1....................................................................................................21

Register 3-15 IP1 –Interrupt Priority 1 ..............................................................................................................21

Register 4-1 LVDCON–LVD control..................................................................................................................25

Register 4-2 PCON0 –Power control 0.............................................................................................................26

Register 4-3 PCON1 –Power control 1.............................................................................................................27

VIII Table of content

AX2228D Audio Player Microcontroller Version 1.0.0

Register 4-4 PCON2 –Power control 2.............................................................................................................28

Register 4-5 PCON3 –Power control 3.............................................................................................................28

Register 4-6 CLKCON –Clock control ..............................................................................................................29

Register 4-7 CLKCON1 –Clock control 1 .........................................................................................................30

Register 4-8 CLKCON2 –Clock control 2 .........................................................................................................31

Register 4-8 CLKCON3–Clock control 3 ..........................................................................................................32

Register 4-9 PLLCON –PLL Configuration.......................................................................................................32

Register 4-10 PLLCON2 –PLL Configuration2.................................................................................................33

Register 4-11 PLLINTH –PLL integer high........................................................................................................33

Register 4-12 PLLINTL –PLL integer low..........................................................................................................34

Register 4-13 PLLFRACH –PLL fraction high...................................................................................................34

Register 4-14 PLLFRACL –PLL fraction low.....................................................................................................34

Register 5-1 PWRCON1 –Power control 1.......................................................................................................38

Register 5-2 PWRCON2 –Power control 2.......................................................................................................39

Register 6-1 P0DIR-P0 direction Register.........................................................................................................42

Register 6-2 P1DIR-P1 direction Register.........................................................................................................42

Register 6-3 P2DIR-P2 direction Register.........................................................................................................42

Register 6-4 P3DIR-P3 direction Register.........................................................................................................42

Register 6-4 P4DIR-P4 direction Register.........................................................................................................43

Register 6-1 SRCCON-Slew Rate control Register...........................................................................................43

Register 6-5 P0 –P0 data register ....................................................................................................................43

Register 6-6 P1 –P1 data register ....................................................................................................................44

Register 6-7 P2 –P2 data register ....................................................................................................................44

Register 6-8 P3 –P3 data register ....................................................................................................................44

Register 6-8 P4 –P4 data register ....................................................................................................................44

Register 6-9 P0PU0 –P0 pull-up resistor control..............................................................................................44

Register 6-10 P1PU0 –P1 pull-up resistor control............................................................................................45

Register 6-11 P2PU0 –P2 pull-up resistor control low byte ..............................................................................45

Register 6-12 P2PU1 –P2 pull-up resistor control high byte.............................................................................45

Register 6-13 P3PU0 –P3 pull-up resistor control............................................................................................45

Register 6-9 P4PU0 –P4 pull-up resistor control..............................................................................................46

Register 6-10 PU200–pull-up 200Ωresistor control..........................................................................................46

Register 6-14 P0PD0 –P0 pull-down resistor control........................................................................................47

Register 6-15 P1PD0 –P1 10KΩ pull-down resistor control..............................................................................47

Register 6-16 P2PD0 –P2 3.3KΩpull-down resistor control.............................................................................47

Table of content IX

AX2228D Audio Player Microcontroller Version 1.0.0

Register 6-17 P2PD1 –P2 0.5KΩpull-down resistor control.............................................................................47

Register 6-18 P3PD0 –P3 10KΩpull-down resistor control..............................................................................48

Register 6-19 P3PUD1 –P3 10KΩpull-down resistor control...........................................................................48

Register 6-14 P4PD0 –P4 pull-down resistor control........................................................................................48

Register 6-20 PIE0 –Port digital input enable control.......................................................................................49

Register 6-21 PIE1 –Port digital input enable control1.....................................................................................49

Register 6-21 PIE2 –Port digital input enable control2.....................................................................................50

Register 6-22 P0DRV0 –Port 0 Driving control.................................................................................................50

Register 6-23 P1DRV0 –Port 1 Driving control 0..............................................................................................51

Register 6-24 P1DRV1 –Port 1 Driving control 1..............................................................................................51

Register 6-25 P2DRV0 –Port 2 Driving control.................................................................................................52

Register 6-26 P3DRV0 –Port 3 Driving control.................................................................................................53

Register 6-27 P3DRV1 –Port 3 Driving control.................................................................................................54

Register 6-28 PMUXCON0 –Port Function MUX control 0...............................................................................54

Register 6-29 PWKEN –Port wakeup enable ...................................................................................................55

Register 6-30 PWKEDGE –Port wakeup Event select .....................................................................................56

Register 7-1 TMR0CON –Timer0 control..........................................................................................................58

Register 7-2 TMR0CNT –Timer0 Counter ........................................................................................................59

Register 7-3 TMR0PR –Timer0 Period.............................................................................................................59

Register 7-4 TMR0PWM –Timer0 PWM duty...................................................................................................59

Register 7-5 TMR1CON0 –Timer1 control 0.....................................................................................................60

Register 7-6 TMR1CON1 –Timer1 control 1.....................................................................................................61

Register 7-7 TMR1CNTH/TMR1CNTL –Timer1 Counter..................................................................................62

Register 7-8 TMR1PRH/TMR1PRL –Timer1 Period.........................................................................................62

Register 7-9 TMR1PWMH/TMR1PWML –Timer1 PWM duty ...........................................................................62

Register 7-10 TMR2CON0 –Timer2 control 0...................................................................................................62

Register 7-11 TMR2CON1 –Timer2 control 1...................................................................................................63

Register 7-12 TMR2CNTH/TMR2CNTL –Timer2 Counter................................................................................64

Register 7-13 TMR2PRH/TMR2PRL –Timer2 Period.......................................................................................64

Register 7-14 TMR2PWMH/TMR2PWML –Timer2 PWM duty .........................................................................64

Register 7-15 TMR3CON –Timer3 control........................................................................................................64

Register 7-16 TMR3CNT –Timer3 Counter ......................................................................................................65

Register 7-17 TMR3PR –Timer3 Period...........................................................................................................65

Register 7-18 TMR3PWM –Timer3 PWM duty.................................................................................................66

Register 7-19 WDTCON –Watchdog control....................................................................................................66

XTable of content

AX2228D Audio Player Microcontroller Version 1.0.0

Register 7-20 RTCON –RTCC control..............................................................................................................75

Register 7-21 RTCDAT –RTCC communication data.......................................................................................76

Register 7-22 SECCNT –IRTCC second counter.............................................................................................76

Register 7-23 RTCON1 –IRTCC control1.........................................................................................................76

Register 10-1 UARTCON –UART0 control.......................................................................................................79

Register 10-2 UARTSTA –UART0 status..........................................................................................................80

Register 10-3 UARTBAUDL –UART0 Baud Rate Low Byte .............................................................................80

Register 10-4 UARTBAUDH –UART0 Baud Rate High Byte............................................................................80

Register 10-5 UARTDATA –UART0 Data .........................................................................................................81

Register 10-6 UART1CON –UART1 control.....................................................................................................81

Register 10-7 UART1STA –UART1 status........................................................................................................82

Register 10-8 UARTDIV –UART1 baud rate high.............................................................................................82

Register 10-9 UART1BAUD –UART1 baud rate low ........................................................................................83

Register 10-10 UART1DATA –UART1 Data buffer...........................................................................................83

Register 10-11 UARTDMATXCNT –UART DMA Transmit counter....................................................................83

Register 8-14 UART2CON –UART2 control.....................................................................................................84

Register 8-15 UART2STA –UART2 status........................................................................................................85

Register 8-16 UART2DIV –UART2 divide register............................................................................................86

Register 8-17 UART2BAUD –UART2 Baud Rate register................................................................................86

Register 8-18 UART2DATA –UART2 Data .......................................................................................................86

Register 8-19 UART2DMATXCNT –UART2 DMA Transmit counter..................................................................86

Register 8-23 UART2POINTL–UART2 DMApoint by CPU read.......................................................................87

Register 8-25 UART2LOOPCNT–UART2 DMAloop count...............................................................................87

Register 8-26 UART2CNTH–UART2 DMAreceive count high byte ..................................................................88

Register 8-27 UART2CNTL–UART2 DMA receive count low byte ....................................................................88

Register 14-1 SPI0CON –SPI0 control.............................................................................................................91

Register 14-2 SPI0BAUD –SPI0 Baud Rate.....................................................................................................91

Register 14-3 SPI0BUF –SPI0 Data Buffer ......................................................................................................92

Register 14-4 SPI0DMACNT –SPI0 DMA counter............................................................................................92

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