Analog Devices AD5162 Manuel utilisateur

256-Position SPI Compatible

Dual Digital Potentiometer

Evaluation Board User Manual AD5162

5 Steps To Setup The Evaluation Board…

5. Measure Result

4. Provide Power Suppl

Use

Power from Parallel Port

GND+5V

No Programming

Skills Required!

Figure 1. Evaluation Kit Setup

2. Configure Board and Connect to Parallel Port with

Provided Parallel Cable

1. Install AD5162 Software

3. Open AD5162 RevA.exe

Rev B 11/03/03 1

256-Position SPI Compatible

Dual Digital Potentiometer

Evaluation Board User Manual AD5162

General Overview

This evaluation board provides the user with a simple and quick solution to evaluate digital potentiometers from

Analog Devices. Only one digital pot can be placed on the board at a time. For the user’s convenience, a general

purpose opamp, 2.5V voltage reference, and two power MOSFETs are included and can be configured in a variety of

flexible configurations. The digital pot can be used by itself or in conjunction with these other components.

How to Get Started

1. Click on the Install Software link in the Digital POT CD browser or setup.exe if you don’t have the CD browser.

2. Configure board to your liking(refer to “Configuring Other Components” on page 4 for more details). A two

channel opamp(AD822B), 2.5V reference(ADR03), and two power mosfets(FDV301N) are provided for your

convenience. If you would simply like to evaluate the digital pot, then ignore Step 2 and proceed to Step 3.

3. Apply a separate power supply or use power from the parallel port(refer to “Powering the AD5162” on page 4 to

avoid damaging the part).

4. Connect board to parallel port with provided parallel cable.

5. Open the AD5162 Rev A program from the Windows Start – Program. Move scroll bar to program resistance

settings. The operation is self-explanatory.

Figure 2. AD5162 Software Graphic al Interface

Rev B 11/03/03 2

256-Position SPI Compatible

Dual Digital Potentiometer

Evaluation Board User Manual AD5162

VDD

SDO

VDD

SHDN

CLK/SCL

SDI/SDA

VSS

DGND

VDD

CS/AD0

SDO

VDD

SHDN

CLK/SCL

SDI/SDA

NC/O2

VSS

DGND

RES/AD1

CS/AD0

4 5

3 4

VDD

DIS

DGND

SDI/SDA

CLK/SCL CS/AD0

RES/AD1

SHDN

SDO

NC/O2

VSS

VDD

DGND

CLK/SCL

CS/AD0

SDI/SDA

CS/AD0

SDO

SDI/SDA

VDD

DIS

DGND

CLK/SCL

VDD

DGND

CLK/SCL

CS/AD0

SDI/SDA

CS/AD0

SDI/SDA

CLK/SCL

DGND

VDD

SDI/SDA

CLK/SCL

DGND

VDD

DGND

CLK/SCL

SDI/SDA

VDD

3 4

6VDD

DGND

CLK/SCL

SDI/SDA

W1 W2

SDO

VDD

SHDN

CLK/SCL

SDI/SDA

VSS

DGND

RES/AD1

CS/AD0

DGND

VDD

RES/AD1

SDI/SDA

CLK/SCL

VDD

OUT1

-I N1

V- +IN2

-IN2

OUT2

V+

+IN1

12345

4321

VDD

GND

VSS 18

W4 19

A4 20

B4 21

W2 22

A2 23

B2 24

NC/O2 17

DIS

9SDO/O1 16

SHDN 15

RESB/AD1 14

CS/AD0 13

VLOGIC

SDI/SDA

CLK/SCL

AD5263

R13

10k

R12

10k

10u

VDD

JP4

AGND

0.1u

JP5

Temp

Vout 4

Trim 5

GND

Vin

U12

ADR03

0.1u

SDO

CS 9

A2 16

W2 15

B2 14

VDD

VL 13

SHDN

VSS 12

CLK

GND 11

SDI

PR 10

AD5 26 2

VDD

SHDN

SCL

SDA

AD1 10

GND 11

VSS 12

O2 13

B2 14

W2 15

A2 16

AD0 9

AD5 24 2

VDD

GND

CLK SDI

AD5160

CS/AD0

SDO/NC

SDI/SDA

GND

SPI/I2C

VDD

CLK/SCL

AD5161

VDD

GND

SCL SDA

AD0

AD5 24 5

VDD

GND

SCL SDA

AD5 24 7

GND

VDD

5SDA

SCL

U1 0

AD5 24 3

GND

VDD

5SDI

CLK

U11

AD5 16 2

CS/AD0

CLK/SCL

SDI/SDA

RES/AD1

0.1u

C10

0.1u

C11

0.1u

C12

0.1u

C13

0.1u

C14

0.1u

VDD

GND

SCL SDA

AD5 24 6

R11

10k

DIS

JP2

JP3

C16

0.1u

C17

10u

VSS

B4B3

FDV301

JP14

FDV301

JP15

D1 D2

CP16 CP18

DGND

DGNDPAD R15

10k

R14

10k

VREF

CP15 CP17

DB2 5

220

100

220

100

SHDN

100

R10

10k

SDO/O1

R16

10k

JP1

470

VDD

SHDN

SCL

SDA

AD1 10

GND 11

VSS 12

VL 13

B2 14

W2 15

A2 16

AD0 9

AD5282

AD0

GND

VDD

5SDA

AD1

SCL

U1 4

AD5 24 8

C15

0.1u

OUT1

-IN1

+IN1

V-

4+IN2 5

-IN2 6

OUT2 7

V+ 8

U3 A

U3 B

U13

AD822

FDV301N Power FETs

AD822 Dual Opamp

ADR03 2.5V Reference

Figure 3. Evaluation Board Schematic

Rev B 11/03/03 3

256-Position SPI Compatible

Dual Digital Potentiometer

Evaluation Board User Manual AD5162

JP12

JP13

Vin2

CP9 CP11

CP8 CP10

CP13 CP14

CP12

U3B

JP10

JP11

JP8

JP9

C20

0.1u

C21

10u

JP7

JP6

C18

0.1u

C19

10u

VCC

VEE

Vin1

U3A

CP2 CP4

CP1 CP3

CP6 CP7

CP5

+IN2

-IN2

OUT2

VDD

V+

OUT1

-IN1

+IN1

V-

confi

uration

Figure 4. Detailed Opamp Connections

Powering the AD5162: Two Options for Powering

I. Using the power from the parallel port as VDD

Simply connect JP1.

The voltage level will be whatever your parallel port operates at.

II. Using a separate supply

DO NOT connect JP1.

Connect voltage supply power and ground to the VDD and GND pads on the board.

Configuring other Components

Two Channel Opamp - AD822

Positive Supply

To use the same VDD as the AD5162, connect JP6.

To use a separate positive supply, connect JP7 and apply positive supply(no more than +15V) to the VCC

pad.

Negative Supply

To use GND, simply connect JP8.

To use a negative supply, connect JP9 and apply negative supply to VEE pad.

For more details on connecters and jumpers around the opamp, refer to Figure 4.

Rev B 11/03/03 4

256-Position SPI Compatible

Dual Digital Potentiometer

Evaluation Board User Manual AD5162

2.5V Voltage Reference – ADR03

By connecting JP5, the voltage reference is connected to the A-terminal of channel-1 of the AD5162. You don’t need

to worry about applying VDD because it is hardwired from the same source that is powering the AD5162.

Power Mosfets – FDV301N

By connecting JP14, the wiper of channel-1 is connected to the gate of Q1. CP15 can be used to place a resistor

between the drain and pad D1. CP16 can be used to place a degenerative resistor between the source and GND.

By connecting JP15, the wiper of channel-2 is connected to the gate of Q2. CP17 can be used to place a resistor

between the drain and pad D2. CP18 can be used to place a degenerative resistor between the source and GND.

Rev B 11/03/03 5

256-Position SPI Compatible

Dual Digital Potentiometer

Evaluation Board User Manual AD5162

AD5162 Parallel Port Connection (Information for Visual Basic Program Developers Only)

SHDN VDD DIS RES/AD1 CLK/SCL

CS/AD0 SDI/SDA

SDO/O1

DGND

SDA_Read

http://www.doc.ic.ac.uk/~ih/doc/par/

8 output pins accessed via the DATA Port portID = Val("&H" + "378") [378h = 888]

5 input pins (one inverted) accessed via the STATUS Port portID = Val("&H" + "379") [379h = 889]

4 output pins (three inverted) accessed via the CONTROL Port portID = Val("&H" + "37A") [37Ah = 890]

The remaining 8 pins are grounded

TIMING DEFINATION IN VISUAL BASIC SOURCE CODE cmdRUN

o Activity Latch Data

Send out

BIT_TOGO=0

Decimal Code

bit 0

(

Pin 2

)

bit 1

(

Pin 3

)

bit 2

(

Pin 4

)

Binary Code 1100 1001 1011 1000 1010 1100

12 9 11 8 10 12

SDI

CLK

/CS

Rev B 11/03/03 6

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