Alpha Micro AM-100 Manuel utilisateur

JAN

1979

....

-----

....---.

"",-,i

~~Ipha

~~rnlCra

TECHNICAL

MANUAL

FOR

AM·"

2-BOARD

B-BIT

CPU

DWM-001

00-00

~alpha

~~rnICrD

TECHNICAL

MANUAL

FOR

AM-~DD

2-BOARD

6-BIT

CPU

Manufactured

ALPHA

MICROSYSTEMS

17881

SKY

PARK

NORTH

IRVINE,

CALIFORNIA

8271

PROPIUETARY NOTICE

This document and the information

herein

disclosed

the proprietary

property

ALPHA MICRO, 17881 Sky Park

North,

Irvine, California 92714. Any persllo

or entity to whom this document

furnished

havingpossession thereof, by

ac-

ceptance,

auumes

custody thereof and agrees

that

the

document

given in con-

fidence and will

not

be copied or reproduced in whole or·in part, nor used

revealed to any person in any manner except to meet the purposes for which

was delivered. Additional rights and obligations regarding this document and its

contents

may

de(med;by aseparate written agreement with ALPHA MICRO-

SYSTEMS,

and

so, suc1t!separate

written

agreement shall be controlling.

"AMOS:'

"Alpha BASIC;" and "AM-IOO" are trademarks

products and soft·

ware

ALPHA MICROSYSTEMS.

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~alpha

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"IIIIl

17881 SkyPark North

[r\Ilne, California

92714

ATTN:

EDUCATIONAL

SERVICES

DIVISION

FOLO

FOLD

•

.........................................

.................................

•

...............

..........................................................

TABLE

CONTENTS

Paragraph

Page

1.0

1.1

1.2

2.0

2.1

2.3

2.4

2 • 5

3.0

3.1

3.2

3.2.

3.2.2

3.2.3

3.2.4

3.2.5

3.2.6

3.2.

SECTION

GENERAL

DESCRIPTION

Introduction

• . . . • . •

Circuit

Board

Description

Application

. . . . . . .

SECTION

OPERATING

DATA

Introduction

. . . . . . . . • .

Capabilities

and

Specifications

Interface

Description

and

Wiring

User

Options

• • . . . . •

Interrupt

and

DMA

Options

System

Connections

. •

SECTION

PROGRA~~ING

Introduction

. . . .

System

Configuration

Software

Overview

Operating

System

Assembly

Language

Program

Text

Editor

Utility

and

Sort

Programs

A1phabasic

Program

Accounting

Package

A1phaLisp

A1phaPasca1

1-1

2-1

2-2

2-6

3-1

3·

3-6

3-7

Paragraph

Page

SECTION

FUNCTIONAL

THEORY

OP,ERATION

4.0

Introduction

····

4-1

4.1

CPU

Configuration

4-1

4.1.

1AM-100

Two-Board

Set

4-1

4.1.

S-100

Bus

Operation

4-2

4.1.3

CPU

Chip

Set

4-16

4.1.3.1

Data

Chip

4-16

4.1.3.2

Control

Chip

4-18

4.1.3.3

Microm

Chips

4-18

4.1.3.4

Microinstruction

Bus

4-18

4.2

CPU

Operations

4-21

2. 1

Clock

Generator

4.2.2

State

Code

Decoder

Logic

4.2.

Sequencer

Operation

4.2.4

Initialization

and

Status

4-47

(

4.2.5

Data

Access

·· · ··

4-48

4.2.5.1

Addressing

Operations

4-50

4.2.5.2

Write

Operations

···

4.2.5.3

Read

Operations

···

4-51

4.2.6

DMA

and

Interrupt

Operations

4-51

4.2.6.1

CPU

Chip

Set

Interrupts

4-52

4.2.6.2

Vectored

Interrupts

4-53

4.2.6.3

DMA

Operations

· ·

4-53

4.3

CPU

Microprocessor

Chip'

Set

Description

4-54

4.3.

System

Components

· · ·...

4-58

4.3.1.1

Registers

··· · ··...

4-59

4.3.1.2

Instruction

Address

Generation

4-64

4.3.1.3

Microinstruction

Bus ··

4-65

4.3.1.4

Data

Access

Bus ····

4-66

4.3.1.5

Microinstruction

Storage

4-66

3.2

CPU

Operations,

4-66

4.3.2.1

CPU

Sequencing

4-67

4.3.2.2

Control

Lines

4-75

Microinstruction

Bus

Operation

Bus

Operation

....

'Microinstruction

Bus

Element

Description

Data

Chip

Control

Chip

Microinstruction

ROM

Data

Access

Input/Output

Instructions

Data/Address

Lines

....

Control

Lines

. . . .

Interrupt,

Reset,

and

Compute

Input/Output

Operations

Circuit

Module

Description

Four-Phase

Clock

Generator

(Board

U12).

Tri-State

4-Bit

DType

(Board

U1, U9, U10) .

High-Speed

Hex

Inverter

(Board

U7)

Tri-State

Buffers

(Board

U5, U8, U22,

U24,

U26;

Board

U45,

U46,

U48)

Hex

Tri-State

Buffers

(Board

U1l,

U47).

Eight-Line

Three-Line

Encoder

(Board

U29,

U30)

..........•.....

Data

Selector/Multiplexer

(Board

U16,

U17,

U18, U21) .

NAND

TTL-to-MOS

Driver

Board

(Board

U2,

3).

• • • • • • • • • • • . • • • . • • •

Positive-Edge-]riggered

Flip-Flops

with

Preset

and

Clear

(Board

U6, U18, U19,

23,

31,

34,

U36) . . . . . . . . .

Paragraph

4.3.3.1

4.3.3.2

3.4

,4.3.5.1

4.3.5.2

4.3.5.3

4.3.5.4

4.3.5.5

4.3.6

4.3.6.1

4.3.6.2

4.3.6.3

4.3.6.4

4.3.6.5

4.4

4.41

4.4.2

4.4.

4.4.4

4.4.5

4.4.6

4.4.

4.4.9

Programmable

Translation

Programmable

Translation

Programmable

Translation

Microinstructions

Array

(PTA) . . .

Conponents.

Operations.

Page

4-90

4-96

4-108

4-109

4-114

116

4-117

4-118

4-134

4-136

4-137

4-142

4-143

4-145

4-146

4-147

4-148

4-149

4-150

4-151

4-152

iii

Paragraph

Page

4.4.10

Dual

J-K

Negative-Edge-Triggered

Flip-Flops

With

Preset

(Board

UiO,

U28, U40,

USC,

4.4.11

4.4.12

4.4.13

4.4.14

4.4.15

51)

.. ..

•

.. .. ..

.. ..

.. .. .. ..

Dual

Retriggerable

One-Shots

With

Clear

(Board

U22)

.....•...•...

Dual

Voltage

Controlled

Oscillators

(Board

US)

.. ..

.... ....

Decoder

(Board

U7,

U8,

U42)

Flip-Flops

With

Clear

(Board

U13,

U14,

U25;

Board

UlO)

.....•....

Tri-State

Octal

Buffers

(Board

U6,

U11,

4-153

4-154

4-155

4-156

4-157

U19,

U27)

.. ..

.. .. ..

4-158

5.0

5.2

SECTION 5

MAINTENANCE

AND

TROUBLESHOOTING

Introduction

...•.

Circuit

Board

Checkout

Warranty

Procedures

SECTION 6

SCHEMATIC

AND

PARTS

LIST

5-1

5-2

Schematic

and

Parts

List

.... . .

.. ..

6-1

Figure

1-1

1-2

2-1

2-2

4-1

4-2

4-3

4-4

4-5

4-6

4-7

4-8

4-9

4-10

4-11

4-12

4-13

4-14

4-15

4-16

4-17

4-18

4-19

4-20

4-21

4-22

LIST

ILLUSTRATIONS

AM-laO

Circuit

Board

Set

Simplified

Block

Diagram

. • . . . . . . . •

AM-lOa

System

Block

Diagram

Header

Jumper

Wiring

. . .

Real

Time

Clock

Connection

S-IOO Bus

Read

Timing

S-IOO Bus

Write

Timing

S-IOO Bus

Read-Modify-Write

Timing

S-100

Bus

DMA

Timing

....

CPU

Chip

Set

. . . . . . . • . .

Microinstruction

Bus

Timing

AM-lOO

Functional

Block

Diagram

AM-lOO

System

Clocks

...

Sequencer

Flow

Diagram

. .

Sequencer

Logic

Equations

CPU

Read

Byte

Timing

•

CPU

Read

Word

Timing

CPU

Write

Byte

Timing

CPU

Write

Word

Timing

CPU

Read-Modify-Write

Byte

Timing

CPU

Read-Modify-Write

Word

Timing

AM-lOO

Power-Up

Sequence

....•

MCP

1600

Microprocessor

Block

Diagram

File

Data

Paths

Data

Paths

Data

Paths

2-7

2-10

4-5

4-6

4-8

4-17

4-20

2 3

4-34

4-40

4-42

4-43

4-44

4-45

4-46

4-49

4-55

4-61

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