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Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
GUI General Overview
The main window of the GUI is shown in Figure 4. Various set-
tings such as type of control, fault detection, etc., can be config-
ured in the GUI. Settings are grouped based on their functionality
in seven pop-up windows marked with red rectangle in Figure 4.
The summary of each configuration option is provided in this
user manual; however, if a detailed explanation of any parameter
is required, it can be easily found in the datasheet by searching
the relevant title.
For example, after clicking on the Bridge PWM button, the
window shown in Figure 5 will open. Then, if further informa-
tion about “Modulation Mode” is required, the title “Modulation
Mode” can be searched in the A4964 datasheet in order to obtain
full details about it.
Bridge PWM
The first pop-up window is the Bridge PWM (Figure 5).
Figure 5: GUI – Bridge PWM Section
The “Modulation Mode” setting defines the number of phases
that are turned on at the same time. For three-phase, all of the
phases will be driven with PWM signal, whereas for two-phase,
one of the phases is always driven low and two other phases are
driven with PWM signal. The two-phase modulation results in
lower switching loss; however, with three-phase modulation,
torque ripple is reduced, resulting in less audible noise at low
power outputs. Both trapezoidal and sinusoidal driving mode
are available in the A4964, which can be selected in the “Drive
Mode” setting. If higher driving capability is required than is
available in sinusoidal mode, the “Overmodulation” setting can
be used.
The frequency of the applied PWM signal can be controlled in
the “PWM Fixed Period” setting, and the alignment of PWM sig-
nals in the three phases can be done by using the “PWM Mode”
setting.
In order to avoid short circuit in the phase of the power MOSFET
bridge, a dead time is required between generating a low or high
side turn-off signal and a complementary turn-on signal. The
duration of the dead time can be selected using the “Dead Time”
setting.
In order to reduce the radiated and conducted electromagnetic
emission (EM), the dither frequency scheme can be used. By
stepping the PWM frequency in a triangular pattern, the EM
energy associated with the switching can be spread across a spec-
trum more effectively. The amount, duration, and the number of
steps can be controlled using “PWM Dither Freq Step”, “PWM
Dither Dwell Time”, and “PWM Dither Step Count” accordingly.
More information about dither frequency scheme can be found in
the datasheet.
In some applications, in order to comply with the EMC emis-
sion regulation, it is necessary to control the rate of change of
the phase voltage. This can usually be achieved by controlling
the FET gate charge and discharge rate. In the A4964, the slew
rate control can be used to control the FET charge and discharge
rate. The amount of the charging current applied to the gate of
the FET is controlled by two parameters, labelled IR1 and IR2.
For the duration defined by TR, the current defined by IR1 is
initially applied to the FET. Usually IR1 is set to maximum, and
turn-on duration is set to last long enough to reach the Miller
region. Once the duration TR ends, the current IR2 is sourced to
the gate of the FETs. IR2 is usually set lower than IR1 to increase
the duration of Miller region, which would therefore result in a
slower rise of the phase voltage. When the FET reaches a fully
on-state, the drive output will change from current mode to volt-
age mode in order to maintain the MOSFET in the fully on-state.
The turn-off sequence follows the same procedure in the reverse
manner, and the amount of sinking currents are determined by
IF1 and IF2. The duration of IF1 in this case is determined by
TF. More information about slew rate control can be found in the
datasheet.
The maximum current limit can be set for the system with the
help of current limit configuration. The amount of current going
through the motor can be determined by measuring the voltage
across the sense resistor, which are connected to Terminal CSP
and CSM as shown in Figure 2. Each time the output of the gate
driver changes, the current limit blank time is triggered. The
duration of blank time can be controlled by modifying OBT.
If at the end of the blank time voltage across the sense resistor
is higher than the current threshold limit defined by VILIM, all
the high-side outputs are turned off, and the phase current will
circulate through the low-side switches. This state is maintained
until the next PWM period starts. VILIM can be calculated using
the following equation:
VILIM = VMIT × VISC
where VMIT is the maximum threshold of the sense amplifier,
which can be set by MIT variable, and
VISC is the current limit scale defined by VIL.
