AKM AK4686 Manuel utilisateur

[AKD4686-B]

K4686 Evaluation Board Rev.0

AKD4686-B

FEATURE

AKD4686-B is an evaluation board for AK4686, a single chip 24bit CODEC that has one stereo ADC and

two stereo DAC. This board has interfaces with AKM’s evaluation boards for A/D converter and D/A

converter and makes easy to evaluate AK4686. Also this board has the digital audio interface and then

achieves the interface with digital audio systems via RCA connector.

Ordering guide

AKD4686-B --- Evaluation Board for AK4686

(Cable for connecting with printer port of IBM-AT compatible PC and control

software are packed with this. This control software does not operate on Windows

NT.)

FUNCTION

On-board clock generators (AK4118 x 2)

Compatible with 2 types of digital audio interface

- RCA (S/PDIF) input/output

- 10pin headers for interfacing with external data source (x2)

RCA connectors for clock input with external clock source

10pin header for register control

GND

AK4686

+5V

Regulator

LOUT1/ROUT1

LOUT2/ROUT2

+3.3V

LIN / RIN

Control Data

10pin Header

RCA OUT

RCA IN

10pin Header

PORT 1

EX1

AK4118

(DIT/DIR)

EX2

10pin Header

PORT 2

AK4118

(DIR)

RCA IN

Figure 1. AKD4686-B Block Diagram

(* Circuit diagram and PCB layout are attached at the end of this manual.)

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[AKD4686-B]

EVALUATION BOARD MANUAL

Operating sequence

1. Set up power supply lines.

Name of

Jack

Color of

Jack Voltage Used for Comment and attention Default

+5V Red

+4.5∼+5.5V Regulator T2, T5 Should be always connected +5V

AVDD1 Orange +3.0∼+3.6V AVDD1 of AK4686

Should be open when JP40

(AVDD1_SEL) is set to REG side.

Should be connected when JP40

(AVDD1_SEL) is set to AVDD1 side.

Open

AVDD2 Orange +3.0∼+3.6V AVDD2 of AK4686

Should be open when JP41

(AVDD2_SEL) is set to REG side.

Should be connected when JP41

(AVDD2_SEL) is set to AVDD2 side.

Open

DVDD Orange

+3.0∼+3.6V DVDD of AK4686

Should be open when JP42 (DVDD_SEL)

is set to REG side.

Should be connected when JP42

(DVDD_SEL) is set to DVDD side.

Open

CVDD Orange

+3.0∼+3.6V CVDD of AK4686

Should be connected when default.

Should be open in case of using regulator

T2 when R85 is short and L7 is open.

+3.3V

D3.3V Orange

+3.0∼+3.6V Power supply of

logic

Should be open when JP45 (D3.3V_SEL)

is set to REG side.

Should be connected when JP45

(D3.3V_SEL) is set to D3.3V side.

Open

VSS1 Black 0V Analog Ground Should be always connected 0V

VSS2 Black 0V Analog Ground Should be always connected 0V

VSS3 Black 0V Analog Ground Should be always connected 0V

VSS4 Black 0V Analog Ground Should be always connected 0V

DGND Black 0V Digital Ground Should be always connected 0V

Table 1. Power supply lines

Each supply line should be distributed from the power supply unit.

2. Set up evaluation mode and jumper pins. (Refer to the following item.)

3. Connect cables. (Refer to the following item.)

4. Power on.

The AK4686 (U1) should be reset once bringing SW1 (PDN) “L” upon power-up.

Keep “H” during normal operaion.

5. Set up control software registers. (Refer to the following item.)

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[AKD4686-B]

Evaluation modes

(1) DAC with external DIR (Synchronous mode)

1. Connection of connector

For digital (S/PDIF) input, RCA connectors J12 (PORT1 RX0) and J15 (PORT2 RX0) are available.

For analog output, RCA connectors J5 (LOUT1)/JP6 (ROUT1), J7 (LOUT2)/J8 (ROUT2) are available.

2. Setting of jumper pin

Setting of interface signal of PORT1: AK4118 (U4) is as follows.

JP19 JP20 JP21 JP22 JP23 JP50

Jumper XTI1 MCKO_SEL1 MCLK1_SEL BICK1_SEL LRCK1_SEL SDTI1

Setting Open MCKO1 Short Short Short Short (Default)

Table 2. Setting of interface signal of PORT1: AK4118 (U4) (1/3)

Setting of interface signal of PORT2: AK4118 (U7) is as follows.

JP26 JP27 JP28 JP29 JP30 JP31

Jumper XTI2 MCKO_SEL2 MCLK2_SEL BICK2_SEL LRCK2_SEL SDTI2_SEL

Setting Open Don’t care MCDIR1 BIDIR1 LRDIR1 SDDIR1

Table 3. Setting of interface signal of PORT2: AK4118 (U7) (1/3)

3. Setting of toggle switch

Switch SW2 SW5 SW6 SW7

Setting H L H H

Table 4. Setting of interface signal of PORT1, PORT2: AK4118 (U4,U7) (2/3)

4. Setting of DIP switch

SW3

Switch DIF0 DIF1 DIF2 CM0 OCKS0 OCKS1

Setting H L H L L H

Table 5. Setting of interface signal of PORT1: AK4118 (U4) (3/3)

SW4

Switch DIF0 DIF1 DIF2 CM0 OCKS0 OCKS1

Setting Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care

Table 6. Setting of interface signal of PORT2: AK4118 (U7) (3/3)

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[AKD4686-B]

(2) DAC with external DIR (Asynchronous mode)

1. Connection of connector

For digital (S/PDIF) input, RCA connectors J12 (PORT1 RX0) and J15 (PORT2 RX0) are available.

For analog output, RCA connectors J5 (LOUT1)/JP6 (ROUT1), J7 (LOUT2)/J8 (ROUT2) are available.

2. Setting of jumper pin

Setting of interface signal of PORT1: AK4118 (U4) is as follows.

JP19 JP20 JP21 JP22 JP23 JP50

Jumper XTI1 MCKO_SEL1 MCLK1_SEL BICK1_SEL LRCK1_SEL SDTI1

Setting Open MCKO1 Short Short Short Short (Default)

Table 7. Setting of interface signal of PORT1: AK4118 (U4) (1/3)

Setting of interface signal of PORT2: AK4118 (U7) is as follows.

JP26 JP27 JP28 JP29 JP30 JP31

Jumper XTI2 MCKO_SEL2 MCLK2_SEL BICK2_SEL LRCK2_SEL SDTI2_SEL

Setting Open MCKO1 MCDIR2 BIDIR2 LRDIR2 SDDIR2 (Default)

Table 8. Setting of interface signal of PORT2: AK4118 (U7) (1/3)

3. Setting of toggle switch

Switch SW2 SW5 SW6 SW7

Setting H H H H

Table 9. Setting of interface signal of PORT1, PORT2: AK4118 (U4, U7) (2/3)

4. Setting of DIP switch

SW3

Switch DIF0 DIF1 DIF2 CM0 OCKS0 OCKS1

Setting H L H L L H (Default)

Table 10. Setting of interface signal of PORT1: AK4118 (U4) (3/3)

SW4

Switch DIF0 DIF1 DIF2 CM0 OCKS0 OCKS1

Setting H L H L L H (Default)

Table 11. Setting of interface signal of PORT2: AK4118 (U7) (3/3)

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[AKD4686-B]

(3) ADC with external DIT

1. Connection of connector

For analog input, RCA connector JL1(LIN1), JL2(LIN2), JL3(LIN3), JL4(LIN4), JL5(LIN5), JL6(LIN6) and

JR1(RIN1), JR2(RIN2), JR3(RIN3), JR4(RIN4), JR5(RIN5), JR6(RIN6) are available.

For digital (S/PDIF) output, RCA connector J13 (PORT1 TX1) is available.

2. Setting of jumper pin

Setting of interface signal of PORT1: AK4118 (U4) is as follows.

X1 (24.576MHz) is used as Clock (512fs) .

JP19 JP20 JP21 JP22 JP23 JP24

Jumper XTI1 MCKO1_SEL MCLK1_SEL BICK1_SEL LRCK1_SEL SDTO1_SEL

Setting Open MCKO1 Short Short Short Short (Default)

Table 12. Setting of interface signal of PORT1: AK4118 (U4) (1/3)

3. Setting of toggle switch

Switch SW2 SW5

Setting H L

Table 13. Setting of reset of PORT1 AK4118 (U4) (2/3)

4. Setting of DIP switch

SW3

Switch DIF0 DIF1 DIF2 CM0 OCKS0

OCKS1 MS1

Setting H L H H L H L

Table 14. Setting of interface signal of PORT1: AK4118 (U4) (3/3)

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[AKD4686-B]

Register control

AKD4686-B can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3

(uP-I/F) to PC by 10-line flat cable packed with this. Take care of the direction of connector.

SDA

(

ACK

)

SCL

AKD4686-B

10-pin header

10-pin connector10-wire flat cable

Connect

RED

PORT3

UP-I/F

Figure 2. PORT1 pin layout

Set-up DIP switch (SW3, 4)

No. Name Content Default

SW3-1 DIF0 ON

SW3-2 DIF1 OFF

Setting of AK4118 Audio Interface Format

Table 16.)

(Refer

SW3-3 DIF2 ON

Selection of AK4118 Clock Mode (Clock Source)

SW3-4 CM0 OFF

Table 17.)

(Refer

SW3-6 OCKS0 OFF

SW3-7 OCKS1

Selection of AK4118 Master Clock Output frequency

Table 18.)(Refer ON

PORT1 Master Mode/Slave Mode Switch

SW3-8 MS1 OFF

(Refer to the AK4686’s datasheet)

SW4-1 DIF0 ON

SW4-2 DIF1 OFF

Setting of AK4118 Audio Interface Format

(Refer Table 16.)

SW4-3 DIF2 ON

Selection of AK4118 Clock Mode (Clock Source)

SW4-4 CM0 OFF

Table 17.)

(Refer

SW4-6 OCKS0 OFF

SW4-7 OCKS1

Selection of AK4118 Master Clock Output frequency

(Refer Table 18.) ON

Table 15. Set up modes of AK4118 (U4, U7) and AK4686 (U1)

LRCK BICK

Mode DIF2 DIF1 DIF0 DAUX SDTO I/O I/O

0 0 0 0 24bit, Left justified 16bit, Right justified H/L O 64fs O

1 0 0 1 24bit, Left justified 18bit, Right justified H/L O 64fs O

2 0 1 0 24bit, Left justified 20bit, Right justified H/L O 64fs O

3 0 1 1 24bit, Left justified 24bit, Right justified H/L O 64fs O

4 1 0 0 24bit, Left justified 24bit, Left justified H/L O 64fs O

5 1 0 1 24bit, I2S 24bit, I2S L/H O 64fs O <Default>

6 1 1 0 24bit, Left justified 24bit, Left justified H/L I 64-128fs I

7 1 1 1 24bit, I2S 24bit, I2S L/H I 64-128fs I

Table 16. AK4118 Audio Interface Format

Mode CM0 PLL X'tal Clock source SDTO

0 0 ON ON PLL RX <Default>

1 1 OFF ON X'tal DAUX

Table 17. AK4118 Clock Mode (Clock Source)

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[AKD4686-B]

No. OCKS1 OCKS0 MCKO1 MCKO2 X’tal fs (max)

0 0 0 256fs 256fs 256fs 96 kHz

1 0 1 256fs 128fs 256fs 96 kHz

2 1 0 512fs 256fs 512fs 48 kHz <Default>

3 1 1 128fs 64fs 128fs 192 kHz

Table 18. AK4118 Master Clock Output Frequency

Toggle switch

[SW1] PDN:

A switch for power down reset of AK4686 (U1). Keep “H” during operation of AK4686 (U1).

Power down reset of AK4686 will be done by setting SW1 to “L” once, after power on.

[SW2] AK4118 (U4)-PDN:

A switch for power down reset of AK4118 (U4). Keep “H” during operation of AK4118 (U4).

Power down reset of AK4118 (U4) will be done by setting SW2 to “L” once, after power on.

[SW5] AK4118 (U7)-PDN:

A switch for power down reset of AK4118 (U7). Keep “H” during operation of AK4118 (U7).

Power down reset of AK4118 (U7) will be done by setting SW5 to “L” once, after power on.

[SW6] MT1N:

A switch for LOUT1/ROUT1 mute control. Keep SW6 “H” during normal operation of AK4686 (U1)’s DAC1.

Analog output will be muted by setting SW6 to “L”.

Refer to Page 20 of AK4686’s datasheet for analog soft mute function of AK4686.

[SW7] MT2N:

A switch for LOUT2/ROUT2 mute control. Keep SW7 “H” during normal operation of AK4686 (U1)’s DAC2.

Analog output will be muted by setting SW7 to “L”.

Refer to Page 20 of AK4686’s datasheet for analog soft mute function of AK4686.

LED indication

[LED1] ERF:

An error detection for AK4118(U4). It turns on when output of AK4118 (U4): INT0 is “H”.

[LED2] ERF:

An error detection for AK4118(U7). It turns on when output of AK4118 (U7): INT0 is “H”.

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[AKD4686-B]

Analog Input Circuit

LIN3

JL3

MR-552LS

(short)

VSS1

RIN3

JR3

MR-552LS

(short)

VSS1

RIN5

JR5

MR-552LS

C15

(short)

VSS1

LIN5

JL5

MR-552LS

C14

(short)

VSS1

RIN4

JR4

MR-552LS

VSS1

C11

(short)

LIN4

JL4

MR-552LS

VSS1

C10

(short)

LIN1

LIN2

LIN3

LIN4

LIN5

LIN6

LIN2

JL2

MR-552LS

(short)

VSS1

RIN2

JR2

MR-552LS

(short)

VSS1

RIN1

RIN2

RIN3

RIN4

RIN5

RIN6

JR6

MR-552LS

C29

(short)

VSS1

LIN6

JL6

MR-552LS

C28

(short)

VSS1

RIN1

JR1

MR-552LS

C27

(short)

VSS1

JL1

MR-552LS

C26

(short)

VSS1

Figure 3. Analog Input Circuit

For analog input, RCA connector: JL1(LIN1), JL2(LIN2), JL3(LIN3), JL4(LIN4), JL5(LIN5), JL6(LIN6) and

JR1(RIN1), JR2(RIN2), JR3(RIN3), JR4(RIN4), JR5(RIN5), JR6(RIN6) are available to use.

Analog inputs are single-ended and input range of each channel is 2.2Vrms (typ) when AVDD1=3.3Vrms.

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[AKD4686-B]

Analog Output Circuit

VSS2 VSS2

R45

(open)

R43

(short)

C30

(short) LOUT1

LOUT1

VSS2

C32

(open)

MR-552LS

VSS2 VSS2

VSS2

R50

(open)

R48

(short)

C35

(short)

ROUT2

C37

(open)

MR-552LS

VSS2

VSS2VSS2

R46

(open)

R44

(short)

ROUT1

C31

(short) ROUT1

C33

(open)

MR-552LS

VSS2

VSS2VSS2

R49

(open)

R47

(short)

LOUT2

C34

(short) LOUT2

C36

(open)

MR-552LS

Figure 4. Analog Output Circuit

For analog output, RCA connector: J5 (LOUT1), J6 (ROUT1), J7 (LOUT2), J8 (ROUT2) are available to use.

Analog outputs are single-ended and output range of each channel is 2Vrms(typ) when AVDD1=AVDD2=3.3Vrms.

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[AKD4686-B]

Digital Input Circuit (External DIR: PORT1 RX0, PORT2 RX0)

DGND DGND

J12

MR-552LS

PORT1 RX0

C38

0.1u

R55

PORT2 RX0

J15

MR-552LS

C49

0.1u

R62

DGND DGND

Figure 5. Digital Input Circuit (External DIR)

For digital input, RCA connector: J12 (PORT1 RX0), J15 (PORT2 RX0) are available.

Digital Output Circuit (External DIT: PORT1 TX1)

R59

240

PORT1 TX1

DGND

J13

MR-552LS

R60

150

DA02F

1 5

4 8

Figure 6. Digital Output Circuit (External DIT)

For digital output, RCA connector: J13 (PORT1 TX1) is available.

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