Active-semi PAC5532EVK1 Manuel utilisateur

PAC5532EVK1 User’s Guide

Power Application Controllers

www.active-semi.com

- 2 - Rev 1.0 February 2018

ONTENTS

Contents ...............................................................................................................................................................2

Overview ..............................................................................................................................................................3

PAC5532EVK1 Resources ..................................................................................................................................5

Pinout and Signal Connectivity.........................................................................................................................5

Power Input ......................................................................................................................................................6

LED’s ................................................................................................................................................................6

SWD Debugging...............................................................................................................................................7

JTAG Debugging ..............................................................................................................................................7

Serial Communications.....................................................................................................................................7

Alternate Serial Communications .....................................................................................................................8

Hall Sensor / DAC Interface .............................................................................................................................8

PAC5532EVK1 Setup ....................................................................................................................................... 10

Power Considerations ....................................................................................................................................... 11

Maximum Current and Voltage...................................................................................................................... 11

SENSE Resistors .......................................................................................................................................... 11

Power FETs ................................................................................................................................................... 11

Increasing Output Power (Appendix) ................................................................................................................ 12

Suggested Heat Sink Profile.......................................................................................................................... 12

Clamping Mechanisms .................................................................................................................................. 13

Adding DRS Clamps .................................................................................................................................. 13

About Active-Semi ® ......................................................................................................................................... 14

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VERVIEW

Active-Semi’s PAC5532EVK1 development platform is a complete hardware solution enabling users not only

to evaluate the PAC5532 device, but also develop power applications revolving around this powerful and

versatile ARM

Cortex

-M4F based microcontroller. The module contains a PAC5532 Power Application

Controller

(MCU) and all the necessary circuitry to properly energize the MCU and its internal peripherals

once power is applied.

To aid in the application development, the PAC5532EVK1 offers access to each and every one of the

PAC5532 device’s signals by means of a series of male header connectors.

The PAC5532EVK1 also contains access to an external USB to UART module enabling users to connect the

evaluation module to a PC computer through a conventional Virtual Comm Port which can then be used in the

communication efforts by taking advantage of the PAC5532’s UART interface. Graphical User Interface (GUI)

software suites can be employed to externally control particular application features.

Finally, the PAC5532EVK1 module gives access to the PAC5532’s SWD and JTAG ports allowing users to

both program the application into the device’s FLASH memory, as well as debug the application in real time.

The provided 4 pin connector is compatible with a decent variety of SWD based debugger/programmer

modules, widely available. In parallel, a MIPI20 connector is made available that provides SWD, JTAG and

TRACE functionality, greatly expanding the existent debugging capabilities.

Active-Semi’s PAC5532EVK1 evaluation kit consists of the following:

•PAC5532EVK1 evaluation module

•PAC5532EVK1 User’s Guide

•Schematics, BOM and Layout Drawings

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Figure 1: PAC5532EVK1 Block Diagram

Solution Benefits:

•Ideal for high voltage (up to 160V Abs Max) general purpose power applications and controllers

•Single-IC PAC5532 with configurable PWM outputs, ADC inputs, I2C, UART, SPI communication

ports and GPIO.

•Gate driving for up to three half H Bridge (tri phase) inverter.

•Schematics, BOM, Layout drawings available

The following sections provide information about the hardware features of Active-Semi’s PAC5532EVK1

turnkey solution.

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PAC5532EVK1

ESOURCES

Pinout and Signal Connectivity

The following diagram shows the male header pinout for the PAC5532EVK1 evaluation module, as seen from

above:

Figure 2 PAC5532EVK1 Headers and Test Stakes Pinout

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Power Input

Power to the PAC5532EVK1 evaluation module can be applied to the VIN and GND spade connectors. Said

applied power should not exceed 160V (Abs Max).

The PAC5532EVK1 is optimized to operate with voltages ranging from 25V to 120V Nominal (160V Abs Max).

When the VIN input voltage goes above 25V, the system exits UVLO protection and all subsystems, including

voltage regulators, analog front end and microcontroller, are enabled.

LED’s

When an operational voltage is applied, LED D5 will light up. This is the LED which notifies that the VSYS

(5V) rail is up and running. VP (12V gate drive), 3.3V (for analog circuitry) and 1.2V (for CPU core) regulators

will also be operating at this point in time. The module is now ready for use.

The following table shows the available LEDs and their associated diagnostic function.

LED

Description

VSYS (5V). Lights up when the PAC5532 device is successfully powered up by VIN.

VIN. Lights up when VIN voltage is applied.

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SWD Debugging

Connector J3 offers access to the PAC5532 SWD port lines.

JTAG Debugging

Connector J13 is a standard MIPI20 offering access to the JTAG port as well as single data line TRACE

debug.

Pins

Terminal

Description

VCC VCC Power

SWDIO/TMS Serial Wire Debug Data Input Output / JTAG Test Mode Select

GND GND (System GND)

SWCLK/TCK Serial Wire Debug Clock / JTAG Clock

GND GND (System GND)

SWO/TDO Serial Wire Debug Output / JTAG Data Output

NC Not Connected

TDI JTAG Data Input

GND GND (System GND)

NC Not Connected

GND GND (System GND)

TRACE CLK ETM Trace Clock

GND GND (System GND)

TRACE DATA 0 ETM Trace Data 0

GND GND (System GND)

TRACE DATA 1 ETM Trace Data 1

GND GND (System GND)

TRACE DATA 2 ETM Trace Data 2

GND GND (System GND)

TRACE DATA 3 ETM Trace Data 3

Serial Communications

Connector J4 offers access to the PAC5532 UART port lines.

Terminal

Description

+ VCCIO (default is 3.3V)

TX MCU Transmit Line (PE3)

RX MCU Receive Line (PE2)

- GND (System Ground)

Terminal

Description

+ VCCIO (default is 3.3V)

SD SWD Serial Data

CL SWD Serial Clock

- GND (System Ground)

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Alternate Serial Communications

When enabled, connector J14 provides access to a secondary UART port lines.

Terminal

Description

+ VCCIO (default is 3.3V)

TX MCU Transmit Line (PF3 – requires 0 ohm resistor R41 to be populated)

RX MCU Receive Line (PF2)

- GND (System Ground)

Hall Sensor / DAC Interface

Connector J12 offers access to the PAC5532 resources on PORTD utilized for hall sensor based

commutation. These resources can be alternatively utilized as PWM DAC outputs for in real time debugging.

Jumpers JMP1/2/3 are used to select the preferred function.

NOTE: 2 pin shunts must be placed on the JMP1/2/3 in order for the respective PORTD resources to be

made available.

Figure 3 DAC / Hall Sensor Jumper Selection

Jumper J

MP1

Description

1:2

Hall Sensor Functionality

2:3

DAC Functionality

NOTE: J12 functionality is only available when jumpers JMP1/2/3 have been shunted on the Hall Sensor

respective position.

Terminal

Description

+ VCCIO (default is 3.3V)

Hall Sensor U PORTD0

Hall Sensor V PORTD1

Hall Sensor W PORTD2

GND GND (System Ground)

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NOTE: Test stakes DAC1/2/3 are only available when jumpers JMP1/2/3 have been shunted on the DAC

respective position

Test Stake

Description

DAC 1

PORTD0

DAC 2

PORTD1

DAC 3

PORTD2

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PAC5532EVK1

ETUP

The setup for the PAC5532EVK1 evaluation module requires up to four simple connections.

1. Connect the VIN power source via spade tab connectors VIN and GND. As VIN power is applied, the

LED D17 will light up. Once VIN voltage goes above 25V, the PAC5532’s Multi Mode Power Manager

will be engaged and the VSYS (5V) regulator will be enabled. This event will result in LED D5 lighting

up.

2. Connect the 3 Phase BLDC/PMSM motor via spade tab connectors PHASE U, PHASE V and PHASE

3. If Serial Communications are desired, connect the USB to UART module 4 pin connection to J4.

4. For debugging/programming, connect a suitable USB SWD module to J3 by using a standard 4 wire

cable.

Figure 4: PAC5532EVK1 Evaluation Module Connections

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