Actis CIO-32 Manuel utilisateur
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USER’S GUIDE
CIO-32
IP module:
Counter/Timer and parallel I/O
Edition 4003
http:// support.actis-computer.com
support@actis-computer.com
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CIO-32
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User's guide
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Table of contents
1. Introduction...........................................................................................................5
2. Summary of features ..........................................................................................5
3. Description............................................................................................................5
3.1. Block diagram...........................................................................................5
3.2. IP spaces...................................................................................................6
3.3. I/O space ................................................................................................................7
3.4. ID space ....................................................................................................7
3.5. MEM space...............................................................................................8
3.6. Wait state cycles.......................................................................................9
4. CIO-32 characteristics ........................................................................................9
5. Zilog CIO Z8536 ................................................................................................. 10
5.1. General-purpose ports.......................................................................... 11
5.2. Special-purpose port ............................................................................ 11
5.3. Counter/Timers ...................................................................................... 12
5.4. CIO Interrupt function............................................................................. 12
5.5. Interrupt timing........................................................................................ 12
5.6. Z8536 registers access........................................................................ 13
6. Connection......................................................................................................... 17
7. Component location ........................................................................................ 18
8. OEM Warranty......................................................................................................... 19
9. Ordering Information ............................................................................................ 20
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CIO-32
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For up to date documentation, please refer also to our web site at http://www.actis-computer.com .
While efforts have been made to ensure the accuracy of this document, and although the information
contained in this document is believed to be correct, ACTIS Computer S.A. can not be held
responsible for any error or for any resulting consequential losses. ACTIS Computer S.A may change
or improve the specifications of its products at any time without prior notification.
Total or partial reproduction of this document or any kinds is not allowed without the written
authorization of ACTIS Computer.
Licenses and trademarks
All licenses and trademarks are property of their respective owners.
This manual is copyrighted, all rights reserved. It may not be copied, photocopied, translated, or
reduced to any electronic medium or machine-readable form without ACTIS Computer prior permission.
© ACTIS Computer, 2001
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User's guide
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1. Introduction
The CIO-32 module of ACTIS Computer S.A. is a Counter/timer and parallel I/O unit
(CIO) compatible with the IP specification. This module provides four general-purpose
8-bit ports, two special-purpose 4-bit ports, and six 16-bit counter/timers.
An on-board 2 kByte EEPROM provides IP identification codes and module specific
data.
A complete industrial OS-9 environment is available for the CIO-32 module.
2. Summary of features
•Single-size IP module.
•Compatible with the IP specification (Rev. 0.7.1).
•Four general-purpose 8-bit ports.
•Two special-purpose 4-bit ports.
•Six 16-bit counter/timers.
•Flexible pattern-recognition logic for interrupt generation.
•All signals in TTL levels.
•2 kByte of non-volatile memory (EEPROM).
•Industrial temperature grade available (-40 to +85 °C).
3. Description
The CIO-32 IP contains two Zilog Counter/timer and parallel I/O Z8536. Each device
has two general-purpose 8-bit ports, one special-purpose 4-bit and three 16-bit
counter/timers.
All CIO-32 I/O signals, TTL levels, are directly connected from CIO controllers to the IP
50-pin I/O connector.
A 2 kByte, 8-bit data path, of non-volatile memory is present on the CIO-32 module,
this memory is divided in two sections. The first contains the identification data (64
Byte), providing the module information such as; the module type, the manufacturer
code, the module and driver revision, etc.
This information defines an auto-configuration system on each power up. The second
is less than 2 kByte (2 kByte -64 Byte) and contains specific user's data such as:
calibration data, configuration information, driver for operation system, etc.
3.1. Block diagram
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CIO-32
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The hardware architecture of the CIO-32 is divided in 3 main sections:
•The IP bus interface, controlling the timing access of the CIO controllers
and the on-board memory.
•The CIO controllers, Zilog Z8536.
•The 2 kByte of non-volatile memory including the identification ROM and
module specific data.
ID ROM
2 kB
EEPROM
IP Bus
Interface
CIO (0)
controller
Z8536
IP Bus
CIO (1)
controller
Z8536
I/O interface
Port A, B (8-bit)
Port E (4-bit)
Timer 1, 2, 3 (16-bit)
Port C, D (8-bit)
Port F (4-bit)
Timer 4, 5, 6 (16-bit)
3.2. IP spaces
The following table shows the four CIO-32 memory spaces.
MEM space (2 kByte -64 Byte) of non-volatile memory
ID space IP identification codes
I/O space CIO controllers access
INT Ack Interrupt acknowledge
The base address of these spaces is depending on the IP carrier.
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User's guide
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3.3. I/O space
The two CIO controllers are mapped into the IP I/O space. Data and command
registers of the CIO controllers are placed on 16 consecutive addresses (8-bit data
path).
I/O space adr. Register Description
CIO (0) controller
$1 PEDR Port E Data Register
$3 PBDR Port B Data Register
$5 PADR Port A Data Register
$7 CR0 Control Register 0
CIO (1) controller
$9 PFDR Port F Data Register
$B PDDR Port D Data Register
$D PCDR Port C Data Register
$F CR1 Control Register 1
All port configurations are defined with the CIO control registers. The data registers
allow the value of each ports to be accessed directly.
3.4. ID space
The identification space is defined as follows:
ID space adr. Description value
$01 Ascii "I" $49
$03 Ascii "P" $50
$05 Ascii "A" $41
$07 Ascii "C" $43
$09 Manufacturer identification $99
$0B Module type $03
$0D Revision module
$0F Reserved $00
$11 Driver ID, low byte
$13 Driver ID, high byte
$15 Number of bytes used $0C
$17 CRC
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CIO-32
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$3F
$19
User space
The fourth bytes contain the ASCII text "IPAC". This clearly identifies the ROM
beginning.
The manufacturer code identifies ACTIS IP.
The CIO-32 device is defined by the module type byte.
The next byte identifies the IP revision, in accordance with the following definition.
Revision ASCII car. hex. value
first "_" (space) $5F
next "A", "B", ... $41, $42, ...
The byte $0F is reserved for future extension.
The byte $11 and $13 allows identification of the IP software driver.
The number of bytes used in the identification space is stored at the address $15.
To verify the identification data integrity, the byte $17 contains a 8-bit Checksum
Redundant Code (CRC). This CRC covers only the number of identification codes set
by the manufacturer. The CRC used is an industry standard. It's the low 8-bit of the
FCS as described in CCITT T.30 (Fascicle VII.3) section 5.3.7.
The next bytes $19 to $3F are free for user data storage.
3.5. MEM space
As 2 kByte memory device is present on the board and only 64 Byte are used for
identification space, the rest is mapped into the IP memory space.
The first usable address of this memory is $40.
A minimum time of 2 ms must be asserted between the last write and the next read
cycle to guarantee the correct data writing. If a read cycle is produced before the
achievement of the previous writing, the data bus D7 provides an inverted value of the
last data loaded.
A minimum time of 2 ms must be asserted between the reset and the first write cycle.
Note: only IP carrier asserting no hold cycle can access this space.
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User's guide
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3.6. Wait state cycles
The following table shows the number of wait states asserted in each
IP space.
Space Wait state
Read Write
I/O 22
Identification 22
Memory 22
Interrupt acknowledge 4N.A.
4. CIO-32 characteristics
Symbol
Parameters Test conditions
Min Max Unit
VIH Input high voltage 2
Vcc + 0.3
V
VIL Input low voltage -0.3
0.8
V
VOH Output high voltage IOH=-250 µA 2.4
V
VOL Output low voltage IOL=+2 mA
IOL=+3.2 mA
0.4
0.5
V
ICC Vcc supply current
560
mA
PCLK Peripheral clock
4
MHz
Ta Operating ambient
temperature
CIO-32 (commercial)
CIO-32X (industrial)
0 to +70
-40 to +85
°C
Tstg Storage temperature
-60 to +150
°C
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