4DSP AD484 Manuel utilisateur

AD484 user manual V1.2

AD484

User Manual

4DSP Inc.

955 S Virginia Street, Suite 214, Reno, NV 89502, USA

Email: support@4dsp.com

This document is the property of 4DSP Inc. and may not be copied nor communicated to a

third party without the written permission of 4DSP Inc.

4DSP

Inc. 200

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Revision History

Date Revision Version

02-03-07 First release 1.0

03-29-07 Corrected typos 1.1

04-12-07 Added more details regarding clock synchronization 1.2

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Table of Contents

Acronyms and related documents ............................................................................. 4

1.1

Acronyms............................................................................................................... 4

1.2

Related Documents ............................................................................................... 4

1.3

General description................................................................................................ 5

Installation ................................................................................................................... 6

2.1

Requirements and handling instructions ................................................................ 6

2.2

Firmware and software........................................................................................... 6

Design .......................................................................................................................... 6

3.1

FPGA devices........................................................................................................ 6

3.1.1

Virtex-4 device A............................................................................................ 6

3.1.2

Virtex-4 device B............................................................................................ 9

3.2

FPGA devices configuration..................................................................................10

3.2.1

Flash storage ................................................................................................10

3.2.2

CPLD device.................................................................................................10

3.2.3

JTAG.............................................................................................................12

3.3

Clock tree..............................................................................................................13

3.4

Memory resources................................................................................................13

3.4.1

QDR2 SRAM.................................................................................................13

3.4.2

DDR2 SDRAM ..............................................................................................13

3.5

A/D inputs and outputs main characteristics..........................................................14

3.5.1

Analog inputs ................................................................................................15

3.5.2

Clock input and reference clock distribution ..................................................15

3.5.3

Multi-module Synchronization .......................................................................15

3.6

Front Panel optical transceivers............................................................................16

Power requirements ...................................................................................................17

4.1

External power connector for stand alone mode ...................................................18

System Side view........................................................................................................19

Environment................................................................................................................19

6.1

Temperature.........................................................................................................19

6.2

Convection cooling................................................................................................19

6.3

Conduction cooling ...............................................................................................19

Safety...........................................................................................................................19

EMC .............................................................................................................................20

Warranty......................................................................................................................20

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1 Acronyms and related documents

1.1 Acronyms

ADC Analog to Digital Converter

DAC Digital to Analog Converter

DCI Digitally Controlled Impedance

DDR Double Data Rate

DSP Digital Signal Processing

EPROM

Erasable Programmable Read-Only Memory

FBGA Fineline Ball Grid Array

FPDP Front Panel Data Port

FPGA Field Programmable Gate Array

JTAG Join Test Action Group

LED Light Emitting Diode

LVTTL Low Voltage Transistor Logic level

LVDS Low Differential Data Signaling

LSB Least Significant Bit(s)

LVDS Low Voltage Differential Signaling

MGT Multi-Gigabit Transceiver

MSB Most Significant Bit(s)

PCB Printed Circuit Board

PCI Peripheral Component Interconnect

PCI-e PCI Express

PLL Phase Locked Loop

PMC PCI Mezzanine Card

QDR Quadruple Data rate

SDRAM Synchronous Dynamic Random Access memory

SRAM Synchronous Random Access memory

Table 1: Glossary

1.2 Related Documents

IEEE Std 1386.1-2001 : IEEE Standard Physical and Environmental Layers for PCI

Mezzanine Cards (PMC).

ANSI/VITA 32-2003 : Processor PMC.

ANSI/VITA 39-2003 : PCI-X for PMC and Processor PMC.

ANSI/VITA 42.0-2005 : XMC Switched Mezzanine Card Auxiliary Standard.

IEEE Std 1386-2001 : IEEE Standard for a Common Mezzanine Card (CMC) Family.

Xilinx Virtex-4 user guide

Xilinx PCI-X core datasheet

Xilinx Virtex-4 Rocket I/O guide

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1.3 General description

The AD484 is a high performance PMC/XMC digitizer module dedicated to digital signal

processing applications with high bandwidth and complex algorithms requirements. The

AD484 can interface to a PCI-express, PCI-X and/or PCI bus. In addition to four 125MSPS

A/D channels, the AD484 offers fast on-board memory resources and two Virtex-4 FPGAs.

Up to 4x 2.5Gbps optical transceivers for serial FPDP or gigabit Ethernet applications are

available for communication with external systems. The AD484 is mechanically and

electrically compliant to the standard and specifications listed in section 1.2 of this document.

The AD484 implements a comprehensive clock circuitry that allows synchronisation among

the converters and cascading modules for multiple receiver systems as well as the use of an

external reference clock. It provides a complete conversion solution and stands as a platform

that can be part of a receive base station.

Figure 1: AD484 block diagram

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The AD484 converts 4 analogue signals into four 14-bit resolution digital data flows with a

sampling frequency up to 125MHz. The clock source can be set to external or internal using

the software and firmware settings available to users. Please note that the clock generation

on board is using low-jitter clock synthesizers.

2 Installation

2.1 Requirements and handling instructions

The AD484 must be installed on a motherboard compliant to the IEEE Std 1386-2001

standard for 3.3V PMC or on a motherboard compliant to the XMC Switched

Mezzanine Card Auxiliary Standard

Do not flex the board

Observe SSD precautions when handling the board to prevent electrostatic

discharges.

Do not install the AD484 while the motherboard is powered up.

2.2 Firmware and software

Drivers, API libraries and a program example working in combination with a pre-programmed

firmware for both FPGAs are provided. The AD484 is delivered with an interface to the Xilinx

PCI core in the Virtex-4 device A and an example VHDL design in the Virtex-4 device B so

users can start digitizing and performing data manipulation right out of the box. For more

information about software installation and FPGA firmware, please refer the AD484 Get

Started Guide and to the Programmer’s guide available online.

3 Design

3.1 FPGA devices

The Virtex-4 FPGA devices interface to the various resources on the AD484 as shown on

Figure 1. They also interconnect to each other via 86 general purpose pins and 2 clock pins.

3.1.1 Virtex-4 device A

3.1.1.1 Virtex-4 device A family and package

The Virtex-4 device A is from the Virtex-4 FX family. It can be either an XC4VFX20 or

XC4VFX60 in a Fineline Ball Grid array with 672 balls (FF672).

3.1.1.2 Power PC embedded processor

Up to two IBM PowerPC RISC processor cores are available in the Virtex-4 device A. This

core can be used to execute C based algorithms and control the logic resources

implemented in the FPGA.

3.1.1.3 Virtex-4 device A external memory interfaces

The Virtex-4 device A is connected to a 128Mbytes SDRAM bank with a 32-bit data bus

width. This memory resource can be used by the PowerPC core or can serve as data buffer.

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3.1.1.4 PCI interface

The Virtex-4 device A interfaces directly to the PCI bus via the PMC Pn1, Pn2 and Pn3

connectors or to the PCI-e bus via the Pn5. An embedded PCI core from Xilinx is used to

communicate over the PCI bus with the host system on the motherboard. PCI-e 4 lanes, PCI-

X 64-bit 66MHz/133MHz, PCI 64-bit 66MHz and PCI 32-bit 33MHz are supported on the

AD484. The bus type must be communicated at the time of the order so the right Virtex-4

device A firmware can be loaded into the flash prior to delivery.

The following performances have been recorded with the AD484 transferring data on the

bus:

PCI-X 64-bit 133MHz: 750Mbytes/s sustained

PCI-X 64-bit 66MHz: 425Mbytes/s sustained

PCI 32-bit 33MHz: 112Mbytes/s sustained

The PCI-express 4-lane is using the MGT I/Os on the Virtex-4 device A. Power filtering, low

jitter clock and special routing are used to achieve the performances required by this

standard. Please refer to the Front Panel Optical transceivers section of this document for

more details (3.6).

3.1.1.5 LED

Four LEDs are connected to the Virtex-4 device A. In the default FPGA firmware, the LEDs

are driven by the Virtex-4 device B via the Virtex-4 device A/ Virtex-4 device B interface.

The LEDs are located on side 2 of the PCB in the front panel area.

Figure 2: FPGA LED locations

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3.1.1.6 Pn4 user I/O connector

The Pn4 connector is wired to the Virtex-4 device A. The 32 lower bits are available only if an

XC4VFX60 device is mounted on board. The 32 higher bits are available only if PCI 32-bit is

used and only if specified at the time of order.

All signals are user-defined 3.3V LVTLL./LVCMOS.

Connector

pin Signal

name FPGA

pin FPGA

pin Signal

name Connector

1 Pn4_IO0 M9 M10 Pn4_IO1 2

3 Pn4_IO2 N11 M11 Pn4_IO3 4

5 Pn4_IO4 N7 N8 Pn4_IO5 6

7 Pn4_IO6 N6 P6 Pn4_IO7 8

9 Pn4_IO8 P10 P11 Pn4_IO9 10

11 Pn4_IO10

P9 N9 Pn4_IO11

13 Pn4_IO12

R8 P8 Pn4_IO13

15 Pn4_IO14

R6 R7 Pn4_IO15

17 Pn4_IO16

N21 M21 Pn4_IO17

19 Pn4_IO18

M20 M19 Pn4_IO19

21 Pn4_IO20

P19 N19 Pn4_IO21

23 Pn4_IO22

N18 N17 Pn4_IO23

25 Pn4_IO24

P16 N16 Pn4_IO25

27 Pn4_IO26

R18 P18 Pn4_IO27

29 Pn4_IO28

P21 P20 Pn4_IO29

31 Pn4_IO30

R17 R16 Pn4_IO31

33 Pn4_IO32

L9 M5 Pn4_IO33

35 Pn4_IO34

L5 AD11 Pn4_IO35

37 Pn4_IO36

AD10 L4 Pn4_IO37

39 Pn4_IO38

L3 AB11 Pn4_IO39

41 Pn4_IO40

AC11 M4 Pn4_IO41

43 Pn4_IO42

N4 T9 Pn4_IO43

45 Pn4_IO44

T8 P5 Pn4_IO45

47 Pn4_IO46

R5 AA10 Pn4_IO47

49 Pn4_IO48

AB10 P4 Pn4_IO49

51 Pn4_IO50

R3 W10 Pn4_IO51

53 Pn4_IO52

Y10 N3 Pn4_IO53

55 Pn4_IO54

P3 U6 Pn4_IO55

57 Pn4_IO56

U5 T4 Pn4_IO57

59 Pn4_IO58

T3 U7 Pn4_IO59

61 Pn4_IO60

V6 U4 Pn4_IO61

63 Pn4_IO62

V4 U9 Pn4_IO63

Table 2 : Pn4 pin assignment

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3.1.2 Virtex-4 device B

3.1.2.1 Virtex-4 device B family and package

The Virtex-4 device B is dedicated to interfacing to the A/D circuitry and can also perform

Digital Signal Processing algorithms. It is available in the Virtex-4 SX or LX family devices

and is packaged in a 1148-ball Fineline Ball Grid array. In terms of logic and dedicated DSP

resources, The FPGA B can be chosen in 5 different sizes: SX55, LX40, LX60, LX80, LX100

and LX160.

3.1.2.2 Virtex-4 device B external memory interfaces

The Virtex-4 device B interfaces to four 8Mbytes QDR2 SRAM devices with 32-bit data bus,

Please note that the four QDR2 SRAM devices are only available with the LX80, LX100 and

LX160 devices. For smaller Virtex-4 FPGAs (LX40, LX60 and SX55) only three QDR2 SRAM

devices are connected to the FPGA.

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3.2 FPGA devices configuration

3.2.1 Flash storage

The FPGA firmware is stored on board in a flash device. The 128Mbit device is partly

used to store the configuration for both FPGAs. In the default CPLD firmware

configuration, the Virtex-4 devices A and B are directly configured from flash if a valid

bitstream is stored in the flash for each FPGA. The flash is pre-programmed in factory

with the default firmware example for both FPGAs.

Figure 3 : Configuration circuit

3.2.2 CPLD device

As shown on Figure 2, a CPLD is present on board to interface between the flash device and

the FPGA devices. It is of type CoolRunner-II. The CPLD is used to program and read the

flash. The data stored in the flash are transferred from the host motherboard via the PCI bus

to the Virtex-4 device A and then to the CPLD that writes the required bit stream to the

storage device. A 31.25 MHz clock connects to the CPLD and is used to generate the

configuration clock sent to the FPGA devices. At power up, if the CPLD detects that an

FPGA configuration bitstream is stored in the flash for both FPGA devices, it will start reading

programming the devices in SelecMap mode.

Do NOT reprogram the CPLD without 4DSP approval

The CPLD configuration is achieved by loading with a Xilinx download cable a bitstream from

a host computer via the JTAG connector. The FPGA devices configuration can also be

performed using the JTAG.

3.2.2.1 DIP Switch

A switch (J1) is located next to the JTAG programming connector (J6) see Figure 4. The

switch positions are defined as follows:

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