ZiLOG Z8 Encore! Manuel utilisateur

Z8 Microcomputer

Technical Manual

April 1983

c·

Z8 Microcomputer

Technical

Manual

part

this publication

may

reproduced without the written

permission of Zilog, Inc.

The

information

this publication

subject to change

without notice.

Table

Conlents

Chapter

Family Overview

1.1

Introduction

1.2

Fe~tures

.2.

1 I

nstruction

Set

1.2.2

Architecture

•••

1.3

Microcomputers (Z8601/11)

••

1.4

Development Device (Z8612)

1.5

Protopack Emulator (Z8603/13)

1.6

BASIC/Debug

Interpreter

(Z8671) •

1.7

ROMless

Microcomputer (Z8681/82)

1.8

Applications

Chapter

Architectural

Overview

2.1

Introduction

2.2

Address Spaces

2.3

File

••

2.3.1

Pointer.

2.3.2

Instruction

Set

2.3.3

Data Types

••••

2.3.4

Addressing

Modes.

2.4

I/O

Operations

2.4.1

Timers

••

2.4.2

Interrupts

2.5

Oscillator

2.6

Protopack.

Chapter

Address Spaces

3.1

Introduction

3.2

CPU

File

•

3.3

3.4

3.5

3.6

3.2.1

Error

Conditions

CPU

Control

and

Peripheral

Registers

CPU

Program

Memory

CPU

Data

Memory

•

CPU

Stacks

• 1-1

1-1

1-3

• 1-3

•

1-4

•

1-4

•

1-4

••••

1-4

• 2-1

•••

2-2

• 2-2

• • 2-2

• 2-2

•••

2-3

• 2-3

3-1

3-2

3-3

3-5

3-6

iii

Table

Contents

(Continued)

Chapter

Address Hodes

4.1

4.2

4.3

4.4

4.5

4.6

4.7

Introduction

• • • • • • • •

Addressing

(R)

• • • • • •

Indirect

Addressing (IR) •

Indexed Addressing

(X)

Direct

Addressing

(DA)

Relative

Addressing

(RA)

Immediate Data Addressing

(1M)

Chapter

Instruction

Set

5.1

5.2

5.3

5.4

Functional

Summary

Processor

Flags

••

5.2.1

Carry

Flag

(C)

•

5.2.2

Zero

Flag

(Z)

5.2.3

Sign

Flag

(S)

5.2.4

Over

flow

Flag

(V)

5.2.5

Decimal-Adjust

Flag

5.2.6

Hal

f-Carry

lag

(H)

Condition

Codes • •

(D)

Notation

and Binary Encoding

5.4.1

Assembly Language Syntax

•••••

5.4.2

Condition

Codes

and

Flag

Settings

5.5

Instruction

Summary

••••••

5.6

Instruction

Descriptions

and Formats

Chapter

External

Interface

(Z8601, Z8611)

6.1

6.2

6.3

6.4

6.5

6.6

Introduction

Description

••••••••

Configuring

for

External

Memory

External

Stacks

•

Data

Memory

•

Bus

Operation • •

6.6.1

Address

Strobe

(AS)

6.6.2

Data

Strobe

(DS)

••

6.6.3

External

Memory

Operations.

6.7

Shared

Bus

•••••

6.8

Extended

Bus

Timing •

6.9

Instruction

Timing

6.10

Reset

Conditions

• • 4-1

• • 4-2

• 4-2

• 4-3

• •

4-3

• •

4-4

• • 5-1

• 5-2

• • 5-2

• 5-3

•••

5-3

• •

5-3

•

5-3

• • 5-3

•

5-4

•

5-4

• • 5-6

• 5-7

• 6-1

••••

6-1

•••

6-2

• •

6-3

• 6-3

• •

6-3

•

6-4

•

6-/~

• •

6-4

•

••

6-5

• 6-6

•

6-7

•

6-10

Chapter

External

Interface

(Z8681, Z8682)

7.1

Introduction

7.2

Descriptions

7.3

Configuring

Port

7.3.1

Z8681

Initialization

••

7.3.2

Z8682

Initialization.

7.3.3

Read/Write

Operations

7.4

External

Stacks

7.5

Data

Memory

••

7.6

Bus

Operation.

7.7

7.8

7.9

7.10

7.6.1

Address

Strobe

(AS)

7.6.2

Data

Strobe

(OS)

Extended

Bus

Timing

Instruction

Timing

Z8681

Reset

Conditions

Z8682

Reset

Conditions

Chapter

Reset and Clock

8.1 Reset

•••••••••

8.2

Clock

••••••••••••••••

8.3

Power-down

Operation

8.4

Test

Mode

••••

" •

8.4.1

8.4.2

Interrupt

Testing

ROMless

Operation

Chapter

I/O

Ports

9.1

9.2

9.3

Introduction

9.1.1

Mode

Registers

••••••

9.1.2

Input

and

Output

Registers.

Port

9.2.1

Read/Write

Operations

9.2.2

Handshake

Operation

Port

9.3.1

Read/Write

Operations

9.3.2

Handshake

Operation

• 7-1

• • 7-1

• 7-2

•

7-3

•

7-4

•.••

7-4

•

7-4

• 7-5

•

7-5

•

7-5

7-6

• • 8-1

• • 8-2

• 8-3

•

8-4

• • 8-5

• 8-5

9-1

• 9-1

• • 9-1

9-1

•

9-3

•

9-3

9-4

•

9-4

• •

9-4

Table

Contents

(Continued)

9.4

9.5

Port

9.4.1

Read/Write

Operations

9.4.2

Handshake Operation

Port

9.5.1

9.5.2

Read/Write

Operations

Special

Functions

9.6

Port

Handshake

•••••

9.7

I/O

Port

Reset

Conditions.

Chapter

10.

Interrupts

10.1

Introduction

10.2

Interrupt

Sources •

10.2.1

External

Interrupt

Sources

10.2.2

Internal

Interrupt

Sources

10.3

Interrupt

Request

Logic and Timing •

10.4

Interrupt

Initialization

•••••

10.4.1

10.4.2

10.4.3

Interrupt

Priority

Initialization

Interrupt

Mask

Initialization

Interrupt

Request

Initialization

•

10.5

IRQ

Software

Interrupt

Generation • •

10.6

Vectored

Processing

•••••••

10.7

10.8

10.6.1

10.6.2

Vectored

Interrupt

Cycle Timing

Nesting

Vectored

Interrupts

Polled

Processing

Reset Conditions

9-5

• 9-5

9-5

9-6

9-7

9-8

9-10

10-1

10-3

10-4

10-5

10-6

10-7

Chapter

11.

Counter/T imers

11.1

Introduction

11.2

Prescalers

and

Counter/Timers

••

11.3 Counter/Timer Operation

11.3.1

Load

and Enable Count

Bits

11.3.2

Prescaler

Operations

11.4

TOUT

Modes

•••

11.5

TIN

Modes.

11.5.1

External

Clock Input Mode.

11.5.2

Gated

Internal

Clock Mode.

11.5.3

Triggered

Input

Mode

11.5.4

Retriggerable

Input

Mode

11.6 Cascading Counter/Timers.

11.7 Reset

Conditions

Chapter

12.

Serial

I/O

12.1

Introduction

12.2

Bit

Rate Generation

12.3 Receiver

Operation.

12.4

12.5

12.3.1

Receiver

Shift

12.3.2

Overwrites

12.3.3

Framing

Errors

12.3.4

Parity

Transmitter

Operation •

12.4.1

Overwrites

12.4.2

Parity

Reset

Conditions

Appendix

Descriptions

and

functions

A.1

Development Device (Z8612)

A.2 Protopack Emulator (Z8603/13)

Appendix B.

Control

Registers

Appendix C. Opcode

Hap

• • • •

11-1

• 11-2

11-3

• 11-4

• 11-5

11-6

11-8

• 11-8

••

11-8

•••

12-1

• 12-1

• 12-3

12-3

• 12-4

12-4

• 12-5

12-6

•

A-1

•

A-1

B-1

C-1

vii

Table

Contents

(Continued)

List

Illustrations

Figure

2-1

Block Diagram

Figure

2-2

Bits

•

Figure

3-1

Figure

3-2

Figure

3-3

Figure

3-4

Figure

3-5a

Figure

3-5b

Figure

3-5c

Figure

3-5d

Figure

3-6a

Figure

3-6b

Figure

3-6c

Figure

3-7

Figure

3-8

Figure

4-1

Figure

4-2

Figure

4-3

Figure

4-4

Figure

4-5

Figure

4-6

Figure

4-7

Figure

4-8

Figure

5-1

Figure

6-1

Figure

6-2

Figure

6-3

Figure

6-4

Figure

6-5

Figure

6-6a

Figure

6-6b

Figure

6-7

Figure

6-8

Figure

6-9a

Figure

6-9b

Figure

6-10

Figure

6-11

Figure

6-12

Figure

6-13

Figure

7-1

Figure

7-2

Figure

7-3

Figure

7-4

viii

File

• • • • • •

16-Bit

Addressing •

Working

Groups

Working

Addressing

Z8601

Program

Memory

Map

Z8611

Program

Memory

Map

Z8681

Program

Memory

Map

•

Z8682

Program

Memory

Map

Z8601

Z8682

Data

Memory

Map

•

Z8611

Data

Memory

Map

Z8681

Data

Memory

Map

Stack

Pointer

Stack Operations • •

Addressing

Working-Register Addressing

Indirect

Addressing

File

Indirect

Addressing

Program or Data

Memory

Indexed Addressing •

Direct

Addressing

Relative

Addressing

Immediate Data Addressing

Flag

Z8601/11 Pin Functions

•••••••••

Z8601/11 Pin Assignments

••••••••

Ports

0 and 1

External

Memory

Operation

Ports

and

1 Stack

Selection

• • • • •

Data

Memory

Operation

External

Instruction

Fetch,

Memory

Read

Cycle •

External

Memory

Write Cycle

Shared

Bus

Operation • • • • • •

Extended

Bus

Timing • • • • • •

••••

Extended

External

Instruction

Fetch,

Memory

Read

Cycle

Extended

External

Memory

Write Cycle

Instruction

Pipe

lining

• • • • • • • • • • • •

Instruction

Cycle Timing

(One

Byte

Instructions)

•

Instruction

Cycle Timing

(Two

and

Three Byte

Instructions

Ports

and

1 Reset

Z8681/82 Pin Functions • • • • •

Z8681/82 Pin Assignments • • •

Example

Z8681/Memory

Interface

•

Example

Z8681/Memory

Interface

•

• 2-1

• • 2-2

• • 3-1

•

••

3-1

•

••

3-2

• • 3-2

• 3-3

• • 3-4

3-4

• • 3-5

• 3-5

• • 3-5

•

••

3-6

• • 4-1

• • 4-2

4-3

• • 4-3

• • •

4-4

5-2

6-1

• • 6-1

• 6-2

6-3

• 6-3

• • • • 6-4

6-5

• 6-5

6-6

• • 6-6

• • 6-7

• • 6-8

• 6-9

• • 6-9

• 6-10

7-1

• • 7-1

• • 7-2

7-3

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