Transcend SSD25S Manuel utilisateur

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2.5” Solid State Disk

Transcend Information Inc.

V1.08

Description

Due to smaller size (fit the standard dimensions of

2.5” SATA Hard Disk Drives), huge capacity, high

speed, and low power consumption, Solid State Disk

is perfect replacement storage device for PCs,

Laptops, gaming systems, and handheld devices.

Placement

Features

•RoHS compliant

•Fully compatible with devices and OS that support the

SATAⅡ3.0Gbps standard

•Non-volatile Flash Memory for outstanding data

retention

•Built-in ECC (Error Correction Code) functionality and

wear-leveling algorithm ensures highly reliable of data

transfer

•Shock resistance

Dimensions

Side Millimeters Inches

A 100.00 ±0.40 3.937 ±0.016

B 69.85 ±0.20 2.750 ±0.008

C 9.50 ±0.15 0.374 ±0.004

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2.5” Solid State Disk

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V1.08

Specifications

Physical Specification

Form Factor 2.5-inch HDD

Storage Capacities 8 GB to 192 GB

Length 100.0 0 ±0.40

Width 69.85 ±0.20

Dimensions (mm)

Height 9.50 ±0.15

Input Voltage 5V ±5%

Weight 55g ±5g

Connector SATA 7+15 pins combo connector

Environmental Specifications

Operating Temperature 0 ℃to 70 ℃

Storage Temperature - 40 ℃to 85 ℃

Power Requirements

Input Voltage 5V ±5% @25℃

Mode Max. (mA) Max. (W)

Write(peak) 476.1 2.4

Read(peak) 426.2 2.1

Power Consumption

(8/16/32/64GB) Idle(peak) 144.0 0.7

Write(peak) 541.6 2.7

Read(peak) 461.2 2.3

Power Consumption

(128GB) Idle(peak) 142.1 0.7

Write(peak) 573.3 2.9

Read(peak) 483.1 2.4

Power Consumption

(192GB) Idle(peak) 146.2 0.7

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2.5” Solid State Disk

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V1.08

Performance

Model P/N Sequential Read(Max.) Sequential Write(Max.)

TS8GSSD25S-S 150 MB/s 90 MB/s

TS16GSSD25S-M 150 MB/s 50 MB/s

TS16GSSD25S-S 150 MB/s 100 MB/s

TS32GSSD25S-M 150 MB/s 90 MB/s

TS32GSSD25S-S 150 MB/s 120 MB/s

TS64GSSD25S-M 150 MB/s 90 MB/s

TS64GSSD25S-S 170 MB/s 140 MB/s

TS128GSSD25S-M 150 MB/s 90 MB/s

TS192GSSD25S-M 150 MB/s 90 MB/s

Actual Capacity

Model P/N User Max. LBA Cylinder Head Sector

TS8GSSD25S-S 15,621,984 15,498 16 63

TS16GSSD25S-M 31,277,056 16,383 16 63

TS16GSSD25S-S 31,277,056 16,383 16 63

TS32GSSD25S-M 62,586,880 16,383 16 63

TS32GSSD25S-S 62,586,880 16,383 16 63

TS64GSSD25S-M 125,206,528 16,383 16 63

TS64GSSD25S-S 125,206,528 16,383 16 63

TS128GSSD25S-M 250,445,824 16,383 16 63

TS192GSSD25S-M 375,685,120 16,383 16 63

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2.5” Solid State Disk

Transcend Information Inc.

V1.08

* Note: Reference to the IEC 60068-2-6 Testing procedures; Operating-Sine wave, 5-800Hz/1 oct., 1.5mm, 3g, 0.5

hr./axis, total 1.5 hrs.

* Note: Reference to the IEC 60068-2-27 Testing procedures; Operating-Half-sine wave, 1500g, 0.5ms, 3 times/dir., total

18 times.

Reliability

Data Reliability Supports BCH ECC 8 bits in 512 bytes

Data Retention 10 years

MTBF 1,000,000 hours

Vibration

Operating 3.0G, 5 - 800Hz

Non-Operating 3.0G, 5 - 800Hz

Shock

Operating 1500G, 0.5ms

Non-Operating 1500G, 0.5ms

Regulations

Compliance CE, FCC and BSMI

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2.5” Solid State Disk

Transcend Information Inc.

V1.08

Package Dimensions

Below figure illustrates the Transcend 2.5” SATA Solid State Disk. All dimensions are in mm.

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2.5” Solid State Disk

Transcend Information Inc.

V1.08

Pin Assignments

Pin No. Pin Name Pin No. Pin Name

01 GND 02 A+

03 A- 04 GND

05 B- 06 B+

07 GND 08 NC

09 NC 10 NC

11 GND 12 GND

13 GND 14 5V

15 5V 16 5V

17 GND 18 GND

19 GND 20 NC

21 NC 22 NC

Pin Layout

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2.5” Solid State Disk

Transcend Information Inc.

V1.08

Block Diagram

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2.5” Solid State Disk

Transcend Information Inc.

V1.08

Reliability

Wear-Leveling algorithm

The controller supports static/dynamic wear leveling. When the host writes data, the controller will find and use the block

with the lowest erase count among the free blocks. This is known as dynamic wear leveling. When the free blocks' erase

count is higher than the data blocks', it will activate the static wear leveling, replacing the not so frequently used user

blocks with the high erase count free blocks.

ECC algorithm

The controller use BCH8 ECC algorithm per 512 bytes. BCH8 can correct up to 8 random error bits within 512 data

bytes.

Bad-block management

When the flash encounters ECC failed, program fail or erase fail, the controller will mark the block as bad block to

prevent the used of this block and caused data lost later on.

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2.5” Solid State Disk

Transcend Information Inc.

V1.08

SATA Interface

Out of bank signaling

There shall be three Out Of Band (OOB) signals used/detected by the Phy: COMRESET, COMINIT, and COMWAKE.

COMINIT, COMRESET and COMWAKE OOB signaling shall be achieved by transmission of either a burst of four Gen1

ALIGNP primitives or a burst composed of four Gen1 Dwords with each Dword composed of four D24.3 characters, each

burst having a duration of 160 UIOOB. Each burst is followed by idle periods (at common-mode levels), having durations

as depicted in Figure 4 and Table 2.

Figure 4 : OOB signals

Table 2 : OOB signal times

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2.5” Solid State Disk

Transcend Information Inc.

V1.08

COMRESET

COMRESET always originates from the host controller, and forces a hardware reset in the device. It is indicated by

transmitting bursts of data separated by an idle bus condition. The OOB COMRESET signal shall consist of no less than

six data bursts, including inter-burst temporal spacing. The COMRESET signal shall be:

1) Sustained/continued uninterrupted as long as the system hard reset is asserted, or

2) Started during the system hardware reset and ended some time after the negation of system hardware reset, or

3) Transmitted immediately following the negation of the system hardware reset signal.

The host controller shall ignore any signal received from the device from the assertion of the hardware reset signal until

the COMRESET signal is transmitted. Each burst shall be 160 Gen1 UI’s long (106.7 ns) and each inter-burst idle state

shall be 480 Gen1 UI’s long (320 ns). A COMRESET detector looksfor four consecutive bursts with 320 ns spacing

(nominal). Any spacing less than 175 ns or greater than 525 ns shall invalidate the COMRESET detector output. The

COMRESET interface signal to the Phy layer shall initiate the Reset sequence shown in Figure 5 below. The interface

shall be held inactive for at least 525 ns after the last burst to ensure far-end detector detects the negation properly.

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