Texas Instruments TMS3705A Guide d'installation

J.A.G Aug 2006

LF Technical Training

TMS3705A Transceiver IC

J.A.G Aug 2006

z5V device

zAutomatic sleep mode (TXCT idle for 100 ms)

zTransponder resonance frequency measurement

zInternal Full Bridge antenna driver

zDigital demodulator

zDiagnosis function

zSeveral operating modes

♦self adapting or fixed frequency charge-up

♦automatic or fixed demodulator threshold

♦asynchronous or synchronous data to µP

zReduced additional component count

zPLL for internal clock generation

z2/4 MHz crystal or low cost ceramic resonator can

be used

16 Pin SO Package

►Main Features

9.35 mm

6.12 mm

J.A.G Aug 2006

►A Transceiver Module with antenna

J.A.G Aug 2006

►Pin Names & Functions

SENSE

SFB

D_TST

A_TST

ANT1

VSSA

ANT2

VDDA

TXCT

F_SEL

SCIO

VSSB

VSS

OSC1

OSC2

VDD

PIN NAME I/O DESCRIPTION

1 SENSE

2 SFB

3 D_TST

4 A_TST

5 ANT1

6 VSSA

7 ANT2

8 VDDA

9 VDD

10 OSC2

11 OSC1

12 VSS

13 VSSB

14 SCIO

15 FSEL

16 TXCT

Input of RF amplifier

Output of RF amplifier

Test output for digital signals

Test output for analog signals

Antenna output 1

Ground for full bridge drivers

Antenna output 2

Voltage supply for full bridge drivers

Voltage supply for non-power blocks

Oscillator output

Oscillator input

Ground for non-power blocks

Ground for PLL

Data output to microprocessor

Control input for frequency selection

Control input for microprocessor

D Package

(Top view)

J.A.G Aug 2006

SCI-

Encoder

►Block Diagram

Band Pass

Limiter

Vref

ANT1

ANT2

VDDA

VSSA

Control Logic

with Mode Control

Pre-

drivers

Full Bridge

Amplifier

SFB

SENSE

Diagnosis

Power-

on reset

Controlled

Frequency Divider

VDD

VSS

OSC1

OSC2

TXCT

F_SEL

SCIO

PLL

D_TST

A_TST

VSSB

10k

Digital

Demodulator

Tag Resonant -

Freq. Measurement

J.A.G Aug 2006

►Generic Circuit Diagram

SENSE

SFB

D_TST

A_TST

ANT1

VSSA

ANT2

VDDA

TXCT

F_SEL

SCIO

VSSB

VSS

OSC1

OSC2

VDD

4 MHz

116

TXCT (input)

SCIO (output)

Supply Voltage

Ground

ANTENNA

J.A.G Aug 2006

►Power Supply and Blocking Capacitance

VDD

VDDA VDD

zConnect the blocking capacitors as

close as possible to the supply pins

zTantalum capacitors are recommended

zTo prevent uncontrolled radiation it is

recommended to connect the supply

voltage symmetrically to VDDA and VDD

J.A.G Aug 2006

►Oscillator - PLL

zIf a Ceramic Oscillator is to be used, one with an internal load

capacitance of around 56 pF is recommended

zAn external oscillator signal can be fed into OSC1. OSC2 has

to be left open - a decoupling capacitor is recommended.

OSC1

OSC2

F_SEL

PLL

VSSB

J.A.G Aug 2006

►The Digital

Demodulator

zThe input frequency is measured by counting the oscillation clock for the time

period of the input signal.

zThe demodulator distinguishes between the high-bit frequency and the low-bit

frequency by the shift values and not by the absolute values.

zThe threshold between the high-bit and the low-bit is defined as 6.5 kHz lower

than that measured for the low-bit frequency

zAfter the charge phase, the transponder response frequency is measured to

determine the counter state for the low-bit and high-bit threshold

VDD

SCIO

Digital

Demodulator

Transponder Resonance -

Frequency Measurement

SCI-

Encoder

J.A.G Aug 2006

►Tag Resonant Frequency Measurement

z1.6 ms after TXCT goes high, an internal measuring cycle of 100 µs

will start to measure the low bit frequency of the 16 tag pre-bits.

100 µs

1.6 ms 1.7 ms

TXCT

SCIO Start Bit

Frequency measuring

starts (Pre-bits)

Begins looking for start

byte (0x7E, 0x7F))

zWhen TXCT goes high, the module enters the read phase

z1.7 ms after TXCT goes high, the IC starts looking for a valid

start byte.

Table des matières

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