Texas Instruments THS3215EVM Manuel utilisateur

SBOU161A–February 2016–Revised April 2016

THS3215EVM and THS3217EVM

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User's Guide

SBOU161A–February 2016–Revised April 2016

THS3215EVM and THS3217EVM

This user guide describes the characteristics, operation, and use of the THS3215EVM and THS317EVM

(THS321xEVM). This evaluation module (EVM) is a demonstration fixture for the THS3215 andTHS3217

family of wideband, differential DAC to single-ended line drivers. The EVM provides 50-Ωinput and output

termination for easy evaluation with common 50-Ωtest equipment. A complete circuit description,

schematic diagram, printed circuit board (PCB) layout, and bill of materials are included.

Throughout this document, the terms demonstration kit, evaluation board, evaluation module, and EVM

are synonymous with the THS321xEVM.

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Contents

1 Introduction ................................................................................................................... 3

2 Design Considerations...................................................................................................... 4

3 Schematic, PCB Layout, and Bill of Materials ........................................................................... 8

List of Figures

1 THS321x Power-Supply Schematic....................................................................................... 4

2 Logic Control Switches...................................................................................................... 4

3 Midscale Buffer Configuration Options.................................................................................... 5

4 D2S Input Connection Options............................................................................................. 6

5 200-MHz Butterworth Filter Before D2S Inputs.......................................................................... 7

6 OPS Input and Output Connection Options.............................................................................. 8

7 EVM Schematic.............................................................................................................. 9

8 Layer 1: Top Signal Layer................................................................................................. 10

9 Layer 2: GND Plane ....................................................................................................... 10

10 Layer 3: Power Plane, ±VCC............................................................................................... 10

11 Layer 4: Power Plane, ±VCC............................................................................................... 10

12 Layer 5: GND Plane ....................................................................................................... 11

13 Layer 6: Bottom Signal Layer............................................................................................. 11

List of Tables

1 Bidirectional Switch Settings ............................................................................................... 4

2 Bill of Materials, THS321x EVM ......................................................................................... 13

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Introduction

SBOU161A–February 2016–Revised April 2016

THS3215EVM and THS3217EVM

1 Introduction

This section provides a general description of the THS3215 and THS3217 devices and the EVM.

1.1 THS3215 and THS3217 Description

The THS3215 and THS3217 (THS321x) combine the key signal-chain components required to interface

with a complementary-current output, digital-to-analog converter (DAC). These two-stage devices deliver

the low-distortion, dc-coupled, single-ended signal required by a wide range of applications. The input

stage buffers the DAC resistive termination, and converts the signal from differential to single-ended with a

fixed gain of 2 V/V. The differential to single-ended output is available externally for direct use, and can

also be connected through an RLC filter or attenuator to the input of an internal output power stage (OPS).

The wideband, current-feedback, OPS provides all pins externally for flexible gain setting.

An internal 2 × 1 multiplexer (mux) to the OPS noninverting input provides an easy means to select

between the internal differential-to-single ended stage (D2S) output or an external input. More information

on the THS3215 and THS3217 can be found in their respective product data sheets, SBOS780 and

SBOS766.

1.2 EVM Description

The THS321xEVM enables performance evaluation of each individual subblock within these devices. The

PCB provides various flexible options to also test either the THS3215 or THS3217 as a complete system.

The EVM provides placeholders to insert filters at different points within the system to allow for more

realistic end-application evaluation.

The following list describes key EVM components:

• Power input: ±6 VDC (typical) at +VCC (P3, TP1) and –VCC (P1, TP2)

• Common reference: GND (P2, TP3 and TP13)

• Interface to the midscale buffer input pin, VMID_IN, through J3 (TP8).

• Interface to the midscale buffer output pin, VMID_OUT, through J4 (TP9).

• Interface to the D2S noninverting signal input pin, IN+, through J1 (TP4).

• Interface to the D2S inverting signal input pin, IN–, through J2 (TP5).

• Interface to the D2S output pin, VO1, through J5 (TP14)

• Interface to the D2S reference input, VREF, through J4. SMA connector J4 is shared with the midscale

buffer output. Depending on the components populated on the board, the appropriate signal is

available at the SMA connector.

• PATHSEL control though switch CS_SW (TP12). Section 2.2 describes the operation of the switch

logic.

• Interface to the OPS external, noninverting input pin, VIN+, through J8.

• DISABLE control though switch PD_SW (TP11). Section 2.2 describes the operation of the switch

logic.

• Interface to the OPS output pin, VOUT, through J7 (TP10).

• Interface to the OPS inverting input pin, VIN–, through J6.

+Vcc2

TP3

2.2F

L1 L3

1000ohm

2.2F

C11

0.022F

1000ohm

GND

TP1

TP2

0.22F

-VCC

+VCC

P 3

P 2

0.22F

0.01F

-Vcc1

+Vcc1

C12

0.022F

GND

0.22F

0.01F

C10

0.01F

-Vcc2

1000ohm 1000ohm

Design Considerations

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2 Design Considerations

This section discusses general design considerations and options when setting up and configuring the

various blocks in THS321xEVM.

2.1 Power Supplies

Power is applied to the board through connectors P1, P2, and P3, as shown in Figure 1. Both bipolar and

single-sided supplies can be used. The typical supplies are ±6 V.

CAUTION

Supplies beyond ±8.1 V can damage the device.

Figure 1. THS321x Power-Supply Schematic

2.2 Digital Logic Control

There are two bidirectional switches on the THS321xEVM that control the status of the PATHSEL and

DISABLE control pins. Figure 2 shows the control logic with respect to the switch position. For brevity, the

PATHSEL control is shown as CS and the DISABLE control is shown as PD on the PCB. The full switch

settings are listed in Table 1.

Figure 2. Logic Control Switches

Table 1. Bidirectional Switch Settings

Switch Set to +VCC Set to GND

CS_SW (PATHSEL control) OPS external, noninverting path Internal path from D2S to OPS

PD_SW (DISABLE control) OPS off OPS on

+Vcc2 -Vcc1

Junc Vneg

Junc Vocm

GND

+Vcc1+Vcc2

GND Junc Vneg

Junc Vocm

GND

-Vcc2 -Vcc1

VBuf_In

Vref/Vmid_Out

PA_In-

PA_Out

TP7

DNP

CM_In

TP8

DNP

Vmid_In

TP9

DNP

Vmid_Out

TP10

DNP

VPA_Out

0.22µF

C29

0.22µF

C19

DNP

0.22µF

C22

0.22µF

C30

49.9

R33

49.9

R34

49.9

R51

49.9

R6349.9

R16

DNP

10.0k

R17

10.0k

R49

10.0k

DNP

10.0k

DNP

10.0

R10

10.0

R11

1.00k

R13

1.00k

R15

R14

DNP

R54

R60

R56

DNP

R55

DNP

R53

DNP

R48

DNP

R38

20k

R36

249

R40

162

R42

0.01µF

C23

DNP

1.00

R37

DNP

1.00

R50

DNP

75.0

R47

DNP

56.2

R39

DNP

56.2

R61

DNP

150

R46

DNP

4.02k

R62

DNP

DISABLE

GND 7

+IN

-IN

PAD 17

PATHSEL

VIN- 12

+VCC2

16 +VCC1

-VCC1

8-VCC2

VIN+ 9

VMID_IN

VMID_OUT 15

VO1 6

VOUT 11

VREF 14

THS3215IRGVR

THS3217IRGVR

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Design Considerations

SBOU161A–February 2016–Revised April 2016

THS3215EVM and THS3217EVM

2.3 Midscale or Reference Buffer

The EVM is configured by default to drive a ground-centered signal. In cases where a different output

common-mode voltage is required, use the midscale buffer to provide a low impedance path. This buffer is

also used in applications where a servo loop is required to set the dc offset of the system to a desired

value. Alternatively, the buffer can also be used to set the reference voltage in single-supply applications

where the inputs to the D2S are ac-coupled. The midscale buffer input defaults to the midsupply voltage.

In cases where a different input voltage is required, adjust the R14 potentiometer (uninstalled by default)

to achieve the desired offset voltage. Resistor R62 must be appropriately sized, and resistor R63

uninstalled in order to set the correct voltage at the input of the midscale buffer. The EVM allows for

connecting the output of the midscale buffer to various nodes of the THS321x. The different options are:

1. In single-supply and ac-coupled applications, the common-mode input of the D2S is configured in one

of two ways. The first way is by installing R56 = 0 Ω. This setting connects the output of the buffer to

the Junc_Vocm node on the board. Components R5, R6, R11, and C19 must be appropriately sized

and installed. The second way is by applying an external common-mode voltage through test-point

TP7.

2. If the output common-mode voltage of the D2S must be set to any voltage other than GND, uninstall

resistors R54 and R51, and install R48 instead. This configuration connects the output of the midscale

buffer to VREF (pin 14).

3. If the OPS is configured in the noninverting mode with a common-mode dc offset voltage from the

D2S, then the D2S provides the necessary dc bias to the noninverting pin of the OPS. However, if the

OPS RGis grounded, the dc common-mode offset voltage from the D2S is amplified by (1 + RF/ RG),

and may result in limited output headroom from the OPS. To prevent this limitation, connect RGto the

midscale buffer output so that the common-mode gain is 0 dB by setting R55 to the desired value of

the gain resistor and uninstalling R42. Installing R55 connects the output of the midscale buffer to

Junc_Vneg enabling configuration of the OPS in a level-shifted, common-mode, noninverting

configuration. Make sure that R54 and R60 are uninstalled, and R51 = R53 = 0 Ωin this configuration.

The areas within the dashed boxes in Figure 3 show the described configurations.

Figure 3. Midscale Buffer Configuration Options

+Vcc2 -Vcc1

GND

+Vcc1+Vcc2

TP4

DNP

GND

Junc Vocm

GND

-Vcc2 -Vcc1

GNDGND

GND

Vin+

Vin-

VBuf_In

D2S_Out

TP5

DNP

+V_In

-V_In

TP7

DNP

CM_In

TP8

DNP

Vmid_In

TP14

DNP

D2S_Out

GND

0.22µF

C15

DNP

0.22µF

C16

DNP

0.22µF

C19

DNP

0.22µF

C22

0.22µF

C24

49.9

R33

49.9

R6349.9

R16

DNP

10.0k

R17

10.0k

DNP

10.0k

DNP

10.0

R10

10.0

R11

1.00k

R13

1.00k

R15

R14

DNP

73.2

R21 0

R22

R27

DNP

20k

R24

169

R25

0.01µF

C23

DNP

2.2pF

C26

DNP

11pF

C27

DNP

1.00

R23

DNP

4.02k

R62

DNP

DISABLE

GND 7

+IN

-IN

PAD 17

PATHSEL

VIN- 12

+VCC2

16 +VCC1

-VCC1

8-VCC2

VIN+ 9

VMID_IN

VMID_OUT 15

VO1 6

VOUT 11

VREF 14

THS3215IRGVR

THS3217IRGVR

72nH

DNP

R18

R19

R12

Uninstall all the RLC filter components if

not used in the application to prevent

loading the D2S output

Design Considerations

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2.4 Differential to Single-Ended Stage (D2S)

The D2S inputs are driven by an external differential signal through SMA connectors J1 and J2. Standard

lab equipment usually provides only a single-ended output. The LMH3401, a very wideband, single-ended

to differential amplifier, was used during product evaluation to drive a differential signal into the D2S. The

spacing of the SMA connectors on the THS321xEVM is designed to interface directly with the output of

the LMH3401EVM through standard SMA barrel connectors. The THS321xEVM provides a standard 100-

Ωdifferentially-terminated resistive network to GND, dc-coupled to the D2S input pins. Figure 4 shows the

EVM schematic of the D2S input/output network with the default passive components installed. The output

of the D2S can also be measured externally at J5.

Figure 4. D2S Input Connection Options

49.9 

IN±

IN+

10 mA

IDIFF

Complementary

Output DAC

15 pF

72 nH

49.9 14.4 pF

15 pF 49.9 

14.4 pF

D2S Input

72 nH

49.9 

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Design Considerations

SBOU161A–February 2016–Revised April 2016

THS3215EVM and THS3217EVM

The EVM allows for flexibility in the D2S input network configuration. The different options are:

1. In order to reduce the high-frequency noise and distortion components from the previous stage driving

the D2S, a passive RLC filter can be inserted prior to the D2S inputs. Figure 5 shows an example of a

third-order, 200-MHz, Butterworth filter placed between the DAC output and D2S input. The

THS321xEVM is able to evaluate system performance with similar RLC-filter architectures installed on

the board.

Figure 5. 200-MHz Butterworth Filter Before D2S Inputs

2. In single-supply and ac-coupled applications, use R18 and R19 to install the appropriately-sized, ac-

blocking capacitors (see Figure 4). Use the midscale buffer output in conjunction with R56, R11, R5,

and R6 to set the desired dc common-mode voltage for the D2S input.

3. The output of the D2S is fed into the internal, noninverting input pin of the OPS by driving PATHSEL

low through switch CS_SW.

4. Certain applications may require an interstage filter inserted between the D2S and OPS to reduce

overall system noise, and prevent high-frequency harmonics from previous stages propagating to the

OPS output. In such situations, use C26, L8, and C27 to insert a third-order, RLC filter into the signal

path of the THS321x (see Figure 4). The output of the filter then drives the external noninverting input

of the OPS, VIN+ (pin 9).

GND

+Vcc1+Vcc2

Junc Vneg

GND

-Vcc2 -Vcc1

GND

PA_In-

PA_Out

PA_In+

TP10

DNP

VPA_Out

0.22 µF

C29

49.9

R33

49.9

R34

R31

R27

DNP

R38

20k

R36

169

R25

249

R40

162

R42

2.2pF

C26

DNP

11pF

C27

DNP

1.00

R37

DNP

75.0

R32

DNP

75.0

R47

DNP

56.2

R39

DNP

150

R46

DNP

DISABLE

GND 7

+IN

-IN

PAD 17

PATHSEL

VIN- 12

+VCC2

16 +VCC1

-VCC1

8-VCC2

VIN+ 9

VMID_IN

VMID_OUT 15

VO1 6

VOUT 11

VREF 14

THS3217IRGVR

72nH

DNP

THS3215IRGVR

THS3217IRGVR

Uninstall the RLC filter when configuring the

OPS as a standalone amplifier

Design Considerations

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2.5 Output Power Stage (OPS)

As described in option 3 and option 4 of Section 2.4, the OPS can be driven internally or externally. The

OPS can be also used as a standalone amplifier in an inverting or noninverting configuration. The output

of the OPS is available at SMA connector J7. Figure 6 shows the EVM schematic of the OPS input/output

network with the default passive components installed. The different options are:

1. When configuring the OPS as a standalone-noninverting amplifier, apply the external input at J8. Set

termination resistor R33 = 49.9 Ω.

2. When configuring the OPS as a standalone-inverting amplifier, apply the external input at J6. Set R46

as the RGresistor, and R47 as the termination resistor. R42 must be uninstalled in this configuration.

3. To conserve power, disable the OPS by setting the DISABLE control low through switch PD_SW.

Figure 6. OPS Input and Output Connection Options

3 Schematic, PCB Layout, and Bill of Materials

This section provides a complete schematic diagram, PCB layout, and bill of materials (BOM) for the

THS321xEVM.

3.1 Schematic

Figure 7 shows the schematic.

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Schematic, PCB Layout, and Bill of Materials

SBOU161A–February 2016–Revised April 2016

THS3215EVM and THS3217EVM

Figure 7. EVM Schematic

Schematic, PCB Layout, and Bill of Materials

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3.2 PCB Layout

The PCB layers are shown in Figure 8 through Figure 13.

Figure 8. Layer 1: Top Signal Layer Figure 9. Layer 2: GND Plane

Ce manuel convient aux modèles suivants

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