Texas Instruments LMK00338EVM Manuel utilisateur

LMK00338EVM

User's Guide

Literature Number: SNAU155

November 2013

User's Guide

SNAU155–November 2013

LMK00338EVM User Guide

This user guide describes how to set up and operate the LMK00338 evaluation module (EVM). The

LMK00338 is a 400 MHz, 8-output HCSL clock buffer intended for high frequency, low additive jitter clock

distribution and level translation. The EVM allows the user to verify the functionality and performance

specifications of the device. Refer to the LMK00338 datasheet for the functional description and

specifications.

Topic ........................................................................................................................... Page

1 General Description ............................................................................................ 3

2 Features ............................................................................................................. 3

3 Quick Setup ....................................................................................................... 3

4 Signal Path and Control Switches ......................................................................... 4

5 Power Supplies ................................................................................................... 5

6 Clock Inputs ....................................................................................................... 6

7 Crystal Oscillator Interface ................................................................................... 7

8 Clock Outputs .................................................................................................... 7

9 Schematics ........................................................................................................ 8

10 Board Layout .................................................................................................... 11

11 Bill of Materials ................................................................................................. 13

All trademarks are the property of their respective owners.

2LMK00338EVM User Guide SNAU155–November 2013

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LMK0033x

EVALUATION

MODULE

CLKinX

CLKinX*

VCC_EXT

GND

Bank A Outputs

(DC Coupled HCSL)

REFout

(LVCMOS)

Bank B Outputs

(DC Coupled HCSL)

Bottom side:

25 MHz Crystal

(Default Input)

CLKoutBn

CLKoutBn*

CLKoutAn

CLKoutAn*

O-SCOPE

(50Ω inputs)

50Ω TERM

Note: Terminate unused

output traces (or disconnect

from output pin on PCB)

CLOCK

SOURCE

(OPTIONAL)

50Ω TERM

4 to 6 V

GND

POWER

SUPPLY

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General Description

1 General Description

2 Features

• Low-noise clock fan-out via two banks of four HCSL outputs and one LVCMOS output

• 3:1 input multiplexer with two universal input buffers and one crystal oscillator interface

• DIP switch control of device configuration

• 3.3 V core and 3 independent 3.3 V/2.5 V output supplies (one per output bank) using external supply

inputs or optional LP3878-ADJ LDO or LMZ10500 switching regulator on board

• AC- or DC-coupled input & output interface with low-skew, controlled-impedance traces and edge SMA

connectors

3 Quick Setup

To quickly set up and operate the board with basic equipment, refer to the setup procedure below and test

setup shown in Figure 1.

Figure 1. LMK00338 Evaluation Board Quick Start Setup

SNAU155–November 2013 LMK00338EVM User Guide

Signal Path and Control Switches

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Setup Procedure:

1. Verify the output mode control switches, S1[1:5], match the states shown in Table 1 to reflect the

default output clock interfaces configured on the EVM.

Table 1. Default Clock Output Modes

SW Position/Name SW State Default Clock Output Modes

S1[2] / CLKoutB_A_EN OFF Bank A outputs enabled

S1[4] / CLKoutB_B_EN OFF Bank B outputs enabled

S1[5] / REFout_EN ON REFout (CMOS) enabled

2. Connect a 4 to 6 V power supply to VCC_EXT and GND terminals of the power block labeled J2. This

powers the on-board LDO regulator to supply 3.3 V to the VCC and VCCO rails of the IC. Both VCC &

VCCO status LEDs should be lit green when ON.

3. Set the desired clock input using the input selection control switches, S1[6:7], as seen in Table 2. The

onboard 25 MHz crystal (Y1) can be selected, so an external clock source is not required. A differential

clock source can be connected to SMAs labeled CLKin0/0* or CLKin1/1*. By default, these differential

inputs are AC coupled and terminated near the device with 100 Ωdifferential. To configure the EVM for

a single-ended input, refer to the Clock Inputs section.

Table 2. Input Selection

Selected Input Default Input Mode S1[6] CLKin_Sel1 State S1[7] CLKin_Sel0 State

CLKin0/0* Differential clock OFF OFF

CLKin1/1* Differential clock OFF ON

OSCin 25 MHz XTAL onboard ON Don't care

4. Connect and measure any clock output SMA labeled CLKoutA#/A#*, CLKoutB#/B#*, or REFout to an

oscilloscope or other test instrument using SMA cable(s). The output clock will be a level-

translated/buffered copy of the selected clock input or crystal oscillator. Note: All output clocks are DC-

coupled to the SMA connectors.

Note: Any active output trace(s) without proper load termination can cause signal reflections on the

board, which can couple onto nearby outputs and degrade signal quality and measurement accuracy.

To minimize these effects, be sure to properly terminate any unused output trace with a 50 ΩSMA

load, or else disconnect any unused output trace from the device output pin by removing the series 0 Ω

resistor. An unused output or output bank may also be disabled using the output mode control switch.

4 Signal Path and Control Switches

The LMK00338 supports single-ended or differential clocks on CLKin0 and CLKin1. A third input, OSCin,

has an integrated crystal oscillator interface that supports a fundamental mode, AT-cut crystal or an

external single-ended clock. To achieve the maximum operating frequency and lowest additive jitter, it is

recommended to use a differential input clock with high slew rate (>3 V/ns) on either CLKin0 or CLKin1

port.

The device provides up to 8 HCSL outputs with pin-selectable output enable (HCSL, or Hi-Z). An

additional output, REFout, has a fixed LVCMOS buffer with output enable input.

All control pins are configured with the control DIP switch, S1. The input selection logic is shown in

Table 2. The output enable selection logic for Bank A and Bank B are shown in Table 1. The REFout

enable logic is shown in Table 3.

Table 3. REF out Enable Selection

REFout Enable Mode S1[5] REFout_EN State

Disabled/Hi-Z OFF

Enabled ON

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Power Supplies

5 Power Supplies

The power supply section on the EVM provides flexibility to power the device using the onboard

regulator(s) or direct supply input(s). A combination of 0 Ωresistor options allows the user to modify the

EVM power supply configuration, if desired.

By default, 3.3 V is supplied to both VCC and VCCO rails by the onboard LDO regulator, U3. To power

the regulator, connect a 4 V to 6 V input voltage and ground from an external power source to the terminal

block, J2, or SMA input labeled VCC_EXT.

To modify the EVM with a different power supply configuration, populate the resistor options as shown in

Table 4. Then, apply the appropriate voltage(s) to the EVM power input(s).

If the EVM is configured for dual direct supplies, connect the 3.3 V supply and ground to VCC_EXT and

the 2.5 V supply and ground to the SMA input labeled VCCO_EXT.

Decoupling capacitors and 0 Ωresistor footprints, which can accommodate ferrite beads, can be used to

isolate the EVM power input(s) from the device power pins.

Table 4. EVM Power Supply Configuration Options

LP3878 LDO LMZ10500 Single Dual

Regulator (U3) Switcher (U2) Direct Supply Direct Supplies

3.3 V (DEFAULT) 3.3 V 3.3 V 3.3 V & 2.5 V

VCC_EXT port Apply 4 V to 6 V Apply 4 V to 5.5 V Apply 3.3 V ± 5% Apply 3.3 V ± 5%

(J2 or SMA)

VCCO_EXT port Not used Not used Not used Apply 2.5 V ± 5%

(SMA)

U2 Vout Not used 3.3 V (VCC & VCCO) Not used Not used

U3 Vout 3.3 V (VCC & VCCO) Not used Not used Not used

R131 OPEN OPEN OPEN 0

R132 0 0 0 0

R134 OPEN 0 OPEN OPEN

R145 OPEN 0 OPEN OPEN

R153 OPEN OPEN 0 0

R155 0 OPEN OPEN OPEN

R156 0 OPEN OPEN OPEN

5.1 Independent Output Supply Voltages

On the bottom side of the EVM, resistor options provide flexibility to power each of the three individual

output supply pins (VCCOA, VCCOB, and VCCOC) from either VCC or VCCO rail. This is useful when 3.3

V and 2.5 V are both needed for separate output supplies.

The EVM power supply needs to be modified to get 2.5 V on the VCCO rail, either using the VCCO_EXT

input or LMZ10500 switcher, as seen in Table 4. To configure LMZ10500 with 2.5 V output, set R138 to

150k and R139 to 118k.

Note: When the LMZ10500 switcher is used to power the DUT and an ultra-low-noise clock source is

used, the higher output noise voltage of the switcher (compared to the LP3878-ADJ) can cause an slight

increase in the output phase noise floor at low offset frequencies as well as low-level spurs. The high

PSRR of the device helps to minimize supply-induced jitter.

SNAU155–November 2013 LMK00338EVM User Guide

Clock Inputs

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6 Clock Inputs

The SMA inputs labeled CLKin0 & CLKin0* and CLKin1 & CLKin1* can be configured to receive a

differential clock or single-ended clock. Best performance is achieved with a differential input clock, which

is the default configuration for both CLKin ports.

Both CLKin0 and CLKin1 paths include footprint options to provide the user with flexibility in configuring

the termination, biasing, and coupling for the device inputs.

6.1 Configuring CLKinX+ for a Single Ended Input

To configure an AC-coupled or DC-coupled single-ended clock input on CLKin0, follow the steps below.

CLKin1 can be modified similarly.

1. Remove R24 (100 Ωdifferential termination).

2. Terminate CLKin0 (driven input) by installing 51 Ωon R30.

3. Install 0.1 uF on C10 as a bypass capacitor.

4. Modify for AC or DC coupled input:

(a) AC-coupled input: Install 0 Ωon R23, so CLKin0* input pin is AC coupled to ground via C17.

(b) DC-coupled input:

(i) Replace R22 and R28 with 0 Ωto DC couple the input path.

(ii) Bias CLKin0*(non-driven input) with a reference voltage near the common-mode voltage of the

DC-coupled input signal (on CLKin0) using R21 and R23 to form a voltage divider from VCC.

For example, if CLKin0 will be driven by a single-ended, DC-coupled LVCMOS signal with a common-

mode voltage of 1.65 V, then 1 kΩresistors can be installed on R21 and R23 to bias CLKin0* to VCC/2.

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Crystal Oscillator Interface

7 Crystal Oscillator Interface

The LMK00338 has an integrated crystal oscillator interface (OSCin/OSCout) that supports a fundamental

mode, AT-cut crystal. If the crystal input is selected, the onboard XTAL on either footprint Y1 or Y2 will

start- up and the oscillator clock can be measured on any enabled output.

By default, a 25.000 MHz XTAL is populated on Y1, which uses a HC49 footprint on the bottom side of the

PCB. Alternatively, a 3.2 x 2.5 mm XTAL or 3.3 V XO (3.3 V CMOS or clipped sinewave) can be

populated on Y2, located on the top side. Only one XTAL footprint should be used at a time.

When using a XTAL, the external load capacitor values of C18 and C22 (CEXT) depend on the specified

load capacitance (CL) for the crystal, as well as the device’s OSCin input capacitance (CIN = 1 pF typical)

and the PCB stray capacitance (CSTRAY ~ 1 pF). The selected 25 MHz crystal is specified for CLof 18 pF.

Assuming equal external load capacitor values for optimum symmetry, CEXT can be calculated as follows:

• CEXT = (CL- CIN - CSTRAY)x2

• CEXT =(18pF-1pF-1pF)x2

• CEXT ~ 33 pF (nearest standard value)

To limit crystal power dissipation, a 1 kΩresistor is placed between the OSCout pin and the crystal.

7.1 Configuring OSCin for a Single Ended Input

To configure a single-ended clock input on OSCin, remove R34 and R37 to disconnect the crystal. Install

0.1 uF on C24 to provide an AC-coupled path from the SMA input labeled OSCin to the device input,

which has internal biasing. Note that the OSCin path includes a 51Ωtermination on R42.

8 Clock Outputs

By default, Bank A and B are configured as enabled HCSL outputs, source-terminated with 50 Ωresistors,

and DC coupled to the SMA connectors labeled CLKoutA#+ / CLKoutA#, or CLKoutB#+ / CLKoutB#–.

REFout is a LVCMOS output and is AC coupled to its SMA connector.

As noted before, active output traces should be properly terminated; otherwise any unused output pin can

be disconnected from the output trace by removing the 0 Ωseries resistor.

SNAU155–November 2013 LMK00338EVM User Guide

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LMK00338EVMProject Title:

Designed for: Public Release

Assembly Variant:001

Drawn By:

Engineer:

Not shown in title block

Julian Hagedorn

Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do

not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or

its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your

application.

Not in version controlSVN Rev:

SV601035Number: Rev: A

Revision History

Revision Notes

LMK00338 Evaluation Board

R153

DNP

R155

VCC_EXT

ADJ 6

GND 3

DAP

OUT 5

BYP 1

LP3878SD-ADJ

10µF

C67

1µF

C68

0.01µF

C69

VCC

10µF

C72 10µF

C71

2200pF

C70

0.01µF

C73

51k

R157

2.00k

R158

866

R159

R156

R134

DNP

R145

DNP

1µF

C61

0.01µF

C62

VCCO

10µF

C60

R132

R131

DNP

270

R154

270

R133

VCC_EXT

VCCO_EXT

VCC

EN_REFout

2.0k

R140

2.0k

R141

2.0k

R142

2.0k

R143 2.0k

R135

3.9k

R150

DNP

3.9k

R146

DNP 3.9k

R147

DNP 3.9k

R148

DNP 3.9k

R149

DNP

CLKoutB_EN

CLKoutA_EN

CLKin_Sel1

CLKin_Sel0

Control Pin Switches and Header

VCC and VCCO Power Supplies

Default Switch Settings for Control Input Pins

S1[2] = 1'b ==> Output Bank B is Enabled

S1[4] = 1'b ==> Output Bank A is Enab led

S1[5] = 1'b ==> REFout is Enabled

S1[6:7] = 10'b ==> OSCin is Selected (25 MHz XTAL)

Switch States

0 = Switch Open / OFF (Control pin tied low via internal

pulldown)

1 = Switch Closed / ON (Control pin connected high to VCC)

A combination of 0 ohm resistor options allows flexibility in powering

the VCC and VCCO rails of the device using onboard LDO regulators

(U2, U3) or external supply(ies).

By default, one of the LDO regulators (U3) provides a low-noise 3.3 V

supply to both supply rails of the device. To power the device in single

supply operation from regulator U1, apply a single external input

voltage (4 V to 16 V) on VCC_EXT via the SMA input or terminal block

J2.

To power the device in single supply operation from an external 3.3 V

supply (bypass LDO regulators), open R131, R134, R145, R155,

R156, and install 0 ohms on R132 and R153. Then, apply 3.3 V to

VCC_EXT.

To power the device in split supply operation (3.3V, 2.5V) from both

onboard regulators (U3, U2), open R131, R132, and R153, and install

0 ohms on R134, R155, R156, and R156. Then, apply 4 V to 16 V on

VCC_EXT.

To power the device in split supply operation from external 3.3 V and

2.5 V supplies, open R132, R134, R145, R155, R156, and install 0

ohms on R131 and R153. Then, apply 3.3 V to VCC_EXT and 2.5 V

to VCCO_EXT.

10µF

C65

118k

R138

150k

R139

470pF

C63

10µF

C64

SV601035

PCB Number:

PCB Rev:

1592820000

VCCO ON

VCC ON

TCBS-6-01

8 9

219-8MST

LDO_OUT

VCC EXT

VCC

VCCO EXT

SSW OUT

1 2

3 4

5 6

7 8

9 10

HEADER_2X5

DNP

PVIN 7

PGND 6

VOUT 5

NC 10

VCON

VDD 8

NC 11

SGND

LM3218SEE/NOPB

DNP

Schematics

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9 Schematics

Figure 2. Schematic Sheet #1

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A A

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LMK00338EVMProject Title:

Designed fo r: Public Release

Assembly Variant:001

Drawn By:

Engineer:

Not shown in title block

Julian Hagedorn

Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do

not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Te xas Instruments and/or

its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your

application.

Not in version controlSVN Rev:

SV601035Number: Rev: A

CLKin1

SMA_C1_P

CLKin1-

DNP

CLKin1+

DNP

SMA_C1_N

U1_C1_P

U1_C1_N

CLKin0+

142-0701-806

CLKin0-

142-0701-806

SMA_C0_P

CLKin0

C0_P

C0_N

U1_C0_P

SMA_C0_N

U1_C0_N

CLKin+/CLKin- can accept a differential or single-ended input

clock. By default, CLKin is configured to accept a differential

clock expecting a 100 ohm differential load. The input is DC

coupled to the device.

Footprint options (0603 size) are included to achieve the

desired input termination, biasing, and coupling to the device.

XTAL Circuit

OSCin Single-Ended Clock Input

Only one XTAL footprint (Y1 or Y2) should be used at a time.

Y1 is HC49 SMD footprint, and Y2 is 3.2 x 2.5 mm SMD footprint.

If an external single-ended clock will be used to drive OSCin, then install

C24 with 0.1 uF and remove R34 and R37 to disconnect the XTAL.

CLKin_Sel0

CLKoutA_EN

CLKin_Sel1

CLKoutB_EN

Bank A Outputs

U1_A0_P

U1_A0_N

U1_A1_P

U1_A1_N

U1_A2_P

U1_A2_N

U1_A3_P

U1_A3_N

Bank B Outputs

U1_B0_P

U1_B0_N

U1_B1_P

U1_B1_N

U1_B2_P

U1_B2_N

U1_B3_P

U1_B3_N

REFout

A2_P

A1_N

A0_N

A0_P

A3_P

A3_N

A2_N

A1_P

B0_P

B0_N

B1_P

B1_N

B2_P

B2_N

B3_P

B3_N

10µF

1µF

10µF

1µF

0.1µF

VCCO

VCC

VCCO

VCC

C1_N

C1_P

REFout_EN Single-Ended Input

By default REFout_EN is driven by SW1 or J1.

If an external single-ended signal will be used

to drive REFout_EN remove R18 and place in

R19 spot.

0.1µF

0402 6.3V

C12

0.1µF

0402 6.3V

100

R24

R26

DNP

VCC

0.1µF

0402

6.3V

C15

DNP

0402

R28

R30

DNP

R21

DNP

VCC

0.1µF

0402

6.3V

C10

DNP

0402

R22

R23

DNP

0.1µF

0402 6.3V

C14

0.1µF

0402 6.3V

C17

100

R31

R25

DNP

R32

DNP

VCC

0.1µF

0402

6.3V

C13

DNP

0.1µF

0402

6.3V

C19

DNP

0402

R27

0402

R33

R35

DNP

R29

DNP

25.000 MHz

18 pF

33pF

C22

33pF

C18 0

R34

R37

OSCin

DNP

R40

DNP

0402

R41

0.1µF

0402

6.3V

C24

DNP

R42

OSCinSMA_OSCin

REFout_EN

DNP

SMA_REFout_EN

0402

R19

DNP

0402

R18

49.9

DNP

U1_REFout_EN

0.01µF

0.01µF C16

0.01µF C26

0.01µF

C27

0.01µF

C20

0.01µF

C21

0402

R45

0402

R46

0402

R47

0402

R48

0402

R49

0402

R50

0402

R51

0402

R52

0402

U1_OSCin

REFout

142-0701-806

U1_REFout

R39

DNP

0402

R36

10pF

C25

DNP

0.1µF

0402 6.3V

C23REFout SMA_REFout

R129

R130

DNP

R123

R124

DNP

R128

R117

R118

DNP

R122

EN_REFout

49.9

R53

DNP 49.9

R60

DNPDNP DNP DNP DNP DNP DNP

49.9

R10

DNP 49.9

R17

DNPDNP DNP DNP DNP DNP DNP

CLKOUTB3 22

CLKOUTB2 23

CLKOUTB2 24

VCC

CLKOUTA0 1

CLKOUTA0 2

CLKOUTA1 4

CLKOUTA1 5

VCCOA 3

CLKOUTA2 7

CLKOUTA2 8

CLKOUTA3 9

CLKOUTA3 10

CLKOUTA_EN

VCC

OSCIN

OSCOUT

GND 20

CLKIN0

CLKIN_SEL1

CLKOUTB_EN

GND 31

CLKOUTB3 21

CLKIN_SEL0

CLKOUTB1 26

CLKOUTB1 27

CLKOUTB0 29

CLKOUTB0 30

VCC

CLKIN1

DAP 41

VCCOA 6

VCCOB 25

VCCOB 28

CLKIN1

REFOUT 36

VCCOC 37

REFOUT_EN

VCC

GND 40

MUX

SYNC

VccoA

VccoC

VccoB

LMK00338RTA GND1 GND2 GND3

GND

REF

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Schematics

Figure 3. Schematic Sheet #2

SNAU155–November 2013 LMK00338EVM User Guide

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B B

A A

3 3

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LMK00338EVMProject Title:

Designed fo r: Public Release

Assembly Variant:001

Drawn By:

Engineer:

Not shown in title block

Julian Hagedorn

Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do

not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Te xas Instruments and/or

its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your

application.

Not in version controlSVN Rev:

SV601035Number: Rev: A

CLKoutA0+

CLKoutA0-

CLKoutA1+

DNP

CLKoutA1-

DNP

CLKoutA2+

DNP

CLKoutA2-

DNP

CLKoutA3+

CLKoutA3-

CLKoutB0+

CLKoutB0-

CLKoutB1+

DNP

CLKoutB1-

DNP

CLKoutB2+

DNP

CLKoutB2-

DNP

CLKoutB3+

CLKoutB3-

Clock Output Interface Options (Termination/Biasing/Coupling)

SMA_B0_P

SMA_B0_N

SMA_B1_P

SMA_B1_N

SMA_B2_P

SMA_B2_N

SMA_B3_P

SMA_B3_N

SMA_A0_P

SMA_A0_N

SMA_A1_P

SMA_A1_N

SMA_A2_P

SMA_A2_N

SMA_A3_P

SMA_A3_N

B0_P

A0_N

Output Bank B Output Bank A

Each output should be DC coupled and drive a 50-ohm load at the destination. The 0 ohm series

resistor near the outputs can be replaced with 10-33 ohms to reduce ringing/overshoot.

Each output should be DC coupled and drive a 50-ohm load at the destination. The 0 ohm series

resistor near the outputs can be replaced with 10-33 ohms to reduce ringing/overshoot.

A0_P

B0_N

B1_P

B1_N

A1_P

A1_N

B2_P

B2_N

B3_P

B3_N

A2_P

A2_N

A3_P

A3_N

R228

R232

R234

R238

R240

R244

R246

R250

R229

R233

R235

R239

R241

R245

R247

R251

Schematics

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Figure 4. Schematic Sheet #3

10 LMK00338EVM User Guide SNAU155–November 2013

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