Texas Instruments ADS1271EVM Manuel utilisateur

User's GuideSBAU107 – November 2004

ADS1271EVM & ADS1271EVM-PDK

This user's guide describes the characteristics, operation, and use of theADS1271EVM, both by itself and as part of the ADS1271EVM-PDK. This EVM is a24-bit analog-to-digital converter evaluation module. A complete circuit description,schematic diagram, and bill of materials are also included.

The following related documents are available through the Texas Instruments web siteat www.ti.com .

EVM-Compatible Device Data Sheets

LiteratureDevice Number

ADS1271 SBAS306OPA350 SBOS099BOPA1632 SBOS286REF1004 SBVS002REF3125 SBVS046ASN74AVC1T45 SCES530CSN74AVC2T45 SCES531DSN74LVC1G125 SCES223LSN74LVC2G66 SCES325GSN74LVC2G157 SCES207ITPS71550 SLVS338H

Contents1 EVM Overview ............................................................................................................... 22 Analog Interface .............................................................................................................. 23 Digital Interface .............................................................................................................. 34 Power Supplies .............................................................................................................. 45 EVM Operation ............................................................................................................... 66 Kit Operation ................................................................................................................. 87 EVM Bill of Materials and Schematic .................................................................................... 12

List of Figures

1 ADS1271EVM Switch and Jumper Locations ............................................................................ 62 ADS1271EVM-PDK Block Diagram ...................................................................................... 93 Default Software Screen .................................................................................................. 10

List of Tables

1 Analog Interface Pinout (J1) ................................................................................................ 32 Auxiliary Analog Input 1 Pinout (J4) ....................................................................................... 33 Auxiliary Analog Input 2 Pinout (J5) ....................................................................................... 3

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1 EVM Overview

1.1 Features

1.2 Introduction

2 Analog Interface

EVM Overview

4 Digital Interface Pinout (J2) ................................................................................................. 45 Power Supply Pinout ........................................................................................................ 46 Reference Selection Options - S3 and S5 ................................................................................ 57 Buffer Amplfier Options - S1 and S2 ...................................................................................... 68 ADC Analog Input Options - S4 and S6 .................................................................................. 69 ADS1271EVM Bill of Materials ........................................................................................... 12

•Full-featured evaluation board for the ADS1271 24-bit Analog-to-Digital Converter•Two ADS1271 converters on board illustrate use of daisy-chain mode•On-board reference and oscillator circuits•Modular design for use with a variety of DSP and microcontroller interface boards.•ADS1271EVM-PDK is a complete evaluation kit, which includes a USB-based motherboard andevaluation software for use with a personal computer running Microsoft Windows™ operating systems.

The ADS1271EVM is built in Texas Instruments' modular EVM form factor, which allows direct evaluationof the ADS1271 performance and operating characteristics, and eases software development and systemprototyping. This EVM is compatible with the 5-6K Interface Board (SLAU104) from Texas Instrumentsand additional third-party boards such as the HPA449 demonstration board from SoftBaugh, Inc.(www.softbaugh.com ) and the Speedy33™ from Hyperception, Inc. (www.hyperception.com ).

The ADS1271EVM-PDK is a complete evaluation/demonstration kit, which includes a USB-enabledDSP-based motherboard (the MMB0) and evaluation software for use with a PC.

The ADS1271EVM features several analog input options. Signals can be routed directly to the convertersor can pass through the on-board buffer amplifiers (U5, U6). Signals can be applied to the board throughthe standard modular EVM analog connector (J1) or brought in through the auxiliary input connectors (J4,J5). A set of switches selects which analog connector source is used and whether the buffer amplifiers arein the signal path. These switches enable several configurations for evaluation. Switch operation andanalog path configuration are described in Section 5.1 .

For maximum flexibility, the ADS1271EVM is designed for easy interfacing to multiple analog sources.Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin,dual-row, header/socket combination at J1. This header/socket provides access to the analog input pins ofthe ADS1271. Consult Samtec at www.samtec.com or call 1-800-SAMTEC-9 for a variety of matingconnector options. Table 1 through Table 3 summarize the standard and auxiliary analog pinoutconfigurations.

Speedy33 is a trademark of Hyperception, Inc..Windows is a trademark of Microsoft Corp..WinZip is a trademark of WinZip Computing, Inc..

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3 Digital Interface

Digital Interface

Table 1. Analog Interface Pinout (J1)

Pin Number Signal Description

J1.1 AIN0N ADS1271 (U7) AINNJ1.2 AIN0P ADS1271 (U7) AINPJ1.3 AIN1N ADS1271 (U8) AINNJ1.4 AIN1P ADS1271 (U8) AINPJ1.5 UnusedJ1.6 UnusedJ1.7 UnusedJ1.8 UnusedJ1.15 UnusedJ1.18 REF(-) External reference source low sideJ1.20 REF(+) External reference source input (2.5V NOM)J1.9-J1.19 (odd) GND Analog ground connections (except J1.15)J1.10-J1.16 (even) Unused

Table 2. Auxiliary Analog Input 1 Pinout (J4)

Pin Number Signal Description

J4.1 AUX1P Auxiliary Signal Input 1 - Positive terminalJ4.2 AUX1N Auxiliary Signal Input 1 - Negative terminalJ4.3 AUXREF1P Auxiliary Reference Input 1 - Positive terminalJ4.4 AUXREF1N Auxiliary Reference Input 1 - Negative terminalJ4.5 GND Ground

Table 3. Auxiliary Analog Input 2 Pinout (J5)

Pin Number Signal Description

J5.1 AUX2P Auxiliary Signal Input 2 - Positive terminalJ5.2 AUX2N Auxiliary Signal Input 2 - Negative terminalJ5.3 AUXREF2P Auxiliary Reference Input 2 - Positive terminalJ5.4 AUXREF2N Auxiliary Reference Input 2 - Negative terminalJ5.5 GND Ground

The ADS1271EVM is designed to easily interface with multiple control platforms. Samtec part numbersSSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row, header/socketcombination at J2. This header/socket provides access to the digital control and serial data pins of theADS1271. Consult Samtec at www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connectoroptions.

Because the ADS1271 devices are capable of daisy-chaining, this EVM has been designed to permitstacking; up to 4 EVMs can be stacked, allowing for 8 devices to be placed in a signal chain. Toaccomodate stacking of EVMs, J2 has some different connections on the top and the bottom side of theboard. Differences between top and bottom connectors are highlighted in Table 4 .

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4 Power Supplies

Power Supplies

Table 4. Digital Interface Pinout (J2)

Pin Number Signal Description

J2.1 SYNC Synchronization ControlJ2.2 MODE0 0 = High-Speed Mode1 = Low-Power Mode(In either case, only if Mode1=1)J2.3 CLKX CLKXMODE = 1: master clock outputCLKXMODE = 0: no connectionJ2.4 DGND Digital groundJ2.5 SCLK Serial ClockJ2.6 MODE1 0 = High-Resolution Mode1 = Mode determined by MODE0J2.7 Unused.J2.8 FSDIR Indicates FSR direction:0 = Output (DRDY in SPI mode)1 = Input (FSYNC mode)J2.9 Top: FSOUT FSOUT: in FSYNC mode, copy of FSR; in SPI mode, not connectedBottom: FSR FSR: in FSYNC mode, frame-sync input; in SPI mode, DRDY output from U8J2.10 DGND Digital groundJ2.11 UnusedJ2.12 CLKRMODE 0 = Use CLKR for SPI Clock1 = Use ADC Clock for SPI clockJ2.13 Top: DIN Top: Serial data inputBottom: DOUT Bottom: Serial data outputJ2.14 CLKXMODE 0 = CLKX is High Z1 = CLKX outputs ADC master clockJ2.15 UnusedJ2.16 SCL I

C bus serial clockJ2.17 EXTCLK External ADC clock inputJ2.18 DGND Digital groundJ2.19 OBCLKSEL Onboard Clock Select:High to select onboard clock instead of external clock.J2.20 SDA I

C bus data line

J3 provides connection to the common power bus for the ADS1271EVM. Power is supplied on the pinslisted in Table 5 .

Table 5. Power Supply Pinout

Signal Pin Number Signal

+AVDD: +15V to power buffer amplifier section 1 2 –AVDD: –15V to power buffer amplifier section+5VA 3 4 UnusedDGND 5 6 AGND+1.8VD 7 8 Unused+3.3VD 9 10 +5VD

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4.1 ADC Power

4.2 Stand-Alone Operation

4.3 Reference Voltage

Power SuppliesWhen power is supplied to J3, J6 allows for either 3.3V or 1.8V to be applied to the digital sections of theADS1271. J6 also provides for a method of measuring AVDD and DVDD supply currents if the shunts onJ6.1-2, J6.3-4, J6.5-6, and J6.7-8 are removed and a current meter is connected between the appropriatepins. See the schematic and printed circuit board silkscreen for details.

Power for the ADS1271 analog supply voltage (AVDD) comes from +5V

, which is supplied through J3.3.The shunt from J6 pins 1 to 2 applies this supply to the U7 ADS1271 device, while the shunt from J6 pins5 to 6 applies this supply to the U8 ADS1271.

The ADS1271 digital supply voltage (DVDD) is selected using J6. When a shunt is applied from J6 pins 9to 10, +1.8VD is selected, and this power comes from J3.7. If a shunt is placed from J6 pins 11 to 12 (thedefault factory setting), +3.3V

is selected, which is provided from J3.9. J6 pins 13 and 15 provide ameans of connecting analog and digital grounds to the EVM; these grounds come from J3.6 and J3.5,respectively. These grounds are always connected together at the EVM.

CAUTIONVerify that all power supplies are within the safe operating limits shown onthe ADS1271 data sheet before applying power to the EVM. Note that ashunt should only be connected between J6 pins 9 and 10 OR pins 11 and12, but never both; doing so would short the +3.3V supply to the +1.8Vdigital supply.

When used as a stand-alone EVM, the analog power can be applied to J6.2 and J6.6, referenced toJ6.13. DVDD can be applied to J6.4 and J6.8, referenced to J6.15. Note that this EVM uses only a singleground plane.

The ADS1271 requires an external voltage reference. Two switches, S3 and S5, select the source of thereference for the two ADS1271s on the EVM. An external reference may be supplied through J1 pin 20 onthe ADS1271EVM, or through J4 and J5, the auxiliary analog input connectors. A 2.5V reference isprovided on the EVM for convenience. These different reference sources can be selected using S3 andS5, as shown in Table 6 .

CAUTIONVerify that the external reference voltage is within the safe operating limitsshown on the ADS1271 data sheet before applying power to the EVM.

Table 6. Reference Selection Options - S3 and S5

S3/S5 Position Reference Inputs

Left Onboard 2.5V referenceMiddle External Reference from J1.20 (REFP) referenced to J1.18(REFN)Right S3: AUXREF1 from J4.3 referenced to J4.4S5: AUXREF2 from J5.3 referenced to J5.4

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5 EVM Operation

LEFT MIDDLE

RIGHT

5.1 Analog Input

EVM Operation

The following section provides information on the analog input, digital control, and general operatingconditions of the ADS1271EVM. Refer to Figure 1 for switch and jumper locations, and the meanings ofleft,middle and right for switch settings in the following discussion.

Figure 1. ADS1271EVM Switch and Jumper Locations

The analog input sources can be applied directly to J1 (top or bottom side) or through the auxiliaryconnectors J4 and J5. The analog input signals can be routed directly to the two ADS1271s on the EVM,or they can be routed through an optional buffer amplifier stage built around U5 or U6. Consult theADS1271 data sheet to determine the maximum analog input range. Table 7 summarizes the position ofswitches S1 and S2. S4 and S6 can be used to select the routing of the ADS1271 analog inputs as shownin Table 8 .

Table 7. Buffer Amplfier Options - S1 and S2

S1/S2 Position Analog Inputs

Top Input from J1Middle Input from J4/J5 auxiliary inputsBottom No connection

Table 8. ADC Analog Input Options - S4 and S6

S4/S6 Position Analog Inputs

Left Input from Buffer AmplifierMiddle Input from J1Right Input from J4/J5 auxiliary inputs

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5.2 Digital Control

5.3 Communication Modes

EVM Operation

5.1.1 Buffer Amplifiers

The buffer amplifiers on this EVM are OPA1632s (U5, U6). These amplifiers are optimized for ACperformance and are configured as fully-differential unity gain buffers. They require ±15V supplies, whichare provided from J3 pins 1 and 2.

The OPA1632 requires a common mode voltage, which is provided on this EVM by U2 and U3. Someusers may not wish to use the buffer amplifier section and provide the ±15V supplies. If the ±15V suppliesare not connected, then having a voltage on the V

OCM

pins of the amplifiers would exceed their maximumratings. Thus, U2 and U3 provide a separate 2.5V reference for the buffer amplifier section rather thanusing the same reference as the ADS1271, which would always be powered. For this reason, U2 and U3power is provided through a separate regulator, U11.

The digital control signals can be applied directly to J2. The modular ADS1271EVM can also beconnected directly to a DSP or microcontroller interface board, such as the HPA449. For a current list ofcompatible interface and/or accessory boards for the EVM or the ADS1271, see the relevant productfolder on the TI web site.

The ADS1271EVM has a digital routing network which can help simulate several possible systemconnections. The routing network also provides level-shifting, which allows the ADS1271 to be operated atany supported logic level regardless of the logic level used on J2. Note that you are not required to includethis circuitry in your own designs; typically no glue logic is required to connect one or more ADS1271s to aprocessor.

5.3.1 Routing control

Routing is controlled by pins CLKRMODE, CLKXMODE, and OBCLKSEL on J2. CLKRMODE controls thedirection and connection of CLKR. When CLKRMODE is low, CLKR is an input connected only to SCLK.When CLKRMODE is high, CLKR becomes an output connected to SCLK, and SCLK is tied to CLK. Thisconnection can be useful in both FSYNC and SPI modes. A pulldown on CLKRMODE makes FSYNCmode the default setting.

When CLKXMODE is high, CLKX is an output connected to CLK. This setting is primarily useful for certainconfigurations using TI's McBSP, where CLKX can be used as a reference clock input for the serial port.When CLKXMODE is low, CLKX on J2 is unconnected. A pulldown on CLKXMODE makes thisconfiguration the default.

OBCLKSEL selects between one of two master clock sources. When OBCLKSEL is high, the on-boardclock is active and used for the master clock. When OBCLKSEL is low, the master clock is taken fromEXTCLK on J2, and the on-board oscillator is disabled. A pulldown on OBCLKSEL makes this setting thedefault.

5.3.2 Using the ADS1271 communication modes

You can use either of the two ADS1271 interface modes with the ADS1271EVM. The interface modes arechosen manually using switch S7, and cannot be selected electrically.

The FSR and FSOUT pins on J2 operate differently depending on the communication mode. In SPI mode,FSR, which is on the socket on the bottom side of the board, carries the DRDY output signal from the firstADC (U8), the second ADC (U7) DRDY line is not connected, and the FSOUT pin on the header on thetop side of the board is not connected. In FSYNC mode, the FSYNC pins of both ADCs are tied together,and the signal on FSR is copied to the top connector on pin FSOUT.

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5.4 Clock Source

6 Kit Operation

Kit Operation

This arrangement allows the ADS1271EVM to be stacked with other ADS1271EVMs in either mode, aslong as all boards in the stack are in the same mode.

A motherboard can sense which state the switch is in and configure itself appropriately by monitoring theFSDIR pin on J2. This pin is high when FSOUT is active and FSR is an input, and low when FSOUT isdisconnected and FSR is an output (that is, it carries the DRDY signal).

5.4.1 Onboard Oscillator

The ADS1271 requires a clock. A 25MHz clock oscillator is provided on the EVM, and is selected as theclock source for the device when OBCLKSEL (J2.19) is high.

5.4.2 External Oscillator

When OBCLKSEL (J2.19) is low, the clock source for the ADS1271 is provided from J2.17, and theon-board clock oscillator is shut down.

The following section provides informationon using the ADS1271EVM-PDK, including setup, programinstallation, and program usage.

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6.1 ADS1271EVM-PDK Block Diagram

C5507

DSP USB

EVM Connectors

ADS1271EVM

Control and Data

Interface

MMB0

6.2 Quick Start

Kit Operation

A block diagram of the ADS1271EVM-PDK is shown in Figure 2 . The evaluation kit consists of two printedcircuit boards connected together. The motherboard is designated as the MMB0, while the daughtercard isthe ADS1271EVM described previously in this manual.

Figure 2. ADS1271EVM-PDK Block Diagram

Ensure that the ADS1271EVM is installed on the MMB0. Place the CD-ROM into your PC CD-ROM drive.Locate the Setup program on the disk and execute it. The Setup program installs the ADS1271 evaluationsoftware on your PC. Follow the instructions and prompts given.

After the main program is installed, a dialog box appears with instructions for installing NI-VISA 3.1Runtime, a self-extracting archive. Click OK to proceed. A WinZip™ dialog appears. Click Unzip, and thearchive extracts itself and automatically runs the NI-VISA 3.1 Runtime installer.

Follow the instructions in the NI-VISA 3.1 Runtime Installer. When prompted for which features to install,do the following:

1. Click on the disk icon next to NI-VISA 3.12. Select, Do not install this feature.3. Click on the disk icon next to USB.4. Select the option which installs this feature.5. Click Next.

Accept the license agreement, and continue the installation.

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6.3 Program Description

Kit Operation

When the installation completes, click Finish on the ADS1271EVM installer window. You may be promptedto restart your computer.

When installation is complete, attach a USB cable from your PC to the MMB0. Supply power to J14 on theMMB0, following the silkscreen markings or schematic; this will supply the ADS1271EVM power throughthe J3 connector on the ADS1271EVM.

The software should automatically find the ADS1271EVM, and a screen similar to the one in Figure 3should appear.

Figure 3. Default Software Screen

Once the ADS1271EVM-PDK software (described in Section 6.2 ) is installed, evaluation and developmentwith the ADS1271 can begin.

6.3.1 Basic Usage

When the program runs, it checks to see whether an MMB0 is connected. If it is, the program downloadsthe firmware to it, and runs; otherwise, it shows a dialog box telling you that it cannot find an MMB0. If yousee this, make sure the MMB0 is connected and powered on, correct this if necessary, and click Retry. Ifyou cannot fix the problem, click Cancel to quit.

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